PSB2186N Infineon Technologies AG, PSB2186N Datasheet

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PSB2186N

Manufacturer Part Number
PSB2186N
Description
ISDN Subscriber Access Controller for Terminal Applications
Manufacturer
Infineon Technologies AG
Datasheet

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ICs for Communications
ISDN Subscriber Access Controller for Terminals
ISAC ® -S TE
PSB 2186
User’s Manual 10.94

Related parts for PSB2186N

PSB2186N Summary of contents

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ICs for Communications ISDN Subscriber Access Controller for Terminals ISAC ® PSB 2186 User’s Manual 10.94 ...

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PEB 2186 Revision History: 10.94 Previous Releases: 11.88; 3.89; 12.89; 02.95 Page Subjects (changes since last revision) The present documentation is an editorial update of the Technical Manual 12.89 Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding only ...

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Table of Contents 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents 2.4.7.6 FAinfD_kfr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents 4.1.4 Mask Register MASK Write Address 20H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents 4.2.15 Additional Feature Register 1 ADF1 Write Address 38H . . . . . . . . . . . . . . . . . . . 170 4.2.16 Additional Feature Register 2 ADF2 Read/Write Address ...

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Introduction ® The PSB 2186 ISAC -S TE implements the four-wire S/T interface used to link voice/data terminals to an ISDN. The PSB 2186 combines the functions of the S-Bus Interface Circuit (SBC: PEB 2080) and the ISDN Communications Controller ...

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ISDN Subscriber Access Controller for Terminals (ISAC ® -S TE) Preliminary Data 1 Features ® Terminal IOM -2 terminal specific version of the PEB 2086: Pin and software compatible to PEB 2086 Compatible to PEB 2085 (Symmetrical Receiver) Full duplex ...

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Pin Configuration (top view) N. SDS1 52 N.C. 53 RST EAW SSD DCL 58 FSC1 59 N. SSD N. SDS1 N.C. ...

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Pin Configuration (top view) Semiconductor Group P-DIP-40 AD4 1 40 AD5 2 39 AD6 3 38 AD7 SDS1 RST 8 33 EAW SSD PSB 2186 ...

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Pin Definitions and Functions Pin No. Pin No. Pin No. P-DIP-40 P-MQFP-64 P-LCC- ...

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Pin Definitions and Functions (cont'd) Pin No. Pin No. Pin No. P-DIP-40 P-MQFP-64 P-LCC- – – – – – ...

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Pin Definitions and Functions (cont'd) Pin No. Pin No. Pin No. P-DIP-40 P-MQFP-64 P-LCC- 10, 14 11 ...

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Logic Symbol + IDP0 R IOM -2 IDP1 EAW FSC DCL Clock Frame Synchronization BCL SDS AD0...7 (D0...7) *) Terminating resistors only at the far ends of the connection Figure 1 ® Logic Symbol ...

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Functional Block Diagram B-Channel Switching D-Channel Handling FIFO P Interface P Figure 2 Block Diagram of the ISAC Semiconductor Group R IOM -2 Buffer R IOM Interface Control ® Features S ISDN - Basic Access Layer-1 ...

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System Integration 1.4.1 ISDN Applications The reference model for the ISDN-basic access according to CCITT I series recommendations consists of – an exchange and trunk line termination in the central office (ET, LT) – a remote network termination in ...

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S TE(1) TE(8) TE(1) TE(1) TE(8) Figure 4 ® Applications of the ISAC -S TE (ISDN-Basic Access) Terminal Applications The concept of the ISDN basic access is based on two circuit-switched 64 kbit/s B channels and a message oriented 16 ...

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D,C/I R ISAC -S TE ICC PSB 2186 PEB 2070 µC Data Module Figure 5 ® Example of an ISDN -S TE Voice/Data Terminal Up to eight D-channel components (ICC: ISDN Communication Controller PEB 2070) may be connected to the ...

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PSB 2165 ARCOFI LCD Control LCD Display Figure 6 ISDN-Feature Telephone 1.4.2 Microprocessor Environment The ISAC especially suitable for cost-sensitive applications with single-chip microcontrollers (e.g. 8048, 8031, 8051). However, due to its programmable micro- processor interface and non-critical ...

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INT(INTX ALE 80C51 (80C188) (PSCX) A15 ... A8 AD ... AD0 Figure 7 ® Connecting the ISAC - Siemens/Intel Microcontroller Semiconductor Group + 5 V INT ALE ALE CS AD7 ... AD0 ...

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Functional Description 2.1 General Functions and Device Architecture The functional block diagram of the ISAC shown in figure 8. The left-hand side of the diagram contains the layer-1 functions, according to CCITT I series recommendations: – S-bus ...

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The right-hand side consists of: – the serial interface logic for the IOM-2 interfaces, with B-channel switching capabilities – the logic necessary to handle the D-channel messages (layer 2). The latter consists of an HDLC receiver and an HDLC transmitter ...

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The operating mode in relation to the timing recovery is illustrated in figure 9. TE Mode, Terminal Timing Mode CLOCK MASTER V/D Module Figure 9 ® Operating Modes of ISAC Semiconductor Group 768 kbit/s IDP0 (DD) 768 kbit/s IDP1 (DU) ...

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IOM -2 Mode Functions ® 2.3.1 Basic IOM -2 Frame Structure The IOM generalization and enhancement of the IOM-1. While the basic frame structure is very similar, IOM-2 offers further capacity for the transfer of maintenance ...

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IOM -2 TE Frame Structure The frame is composed of three channels (figure 11): Channel 0 contains 144 kbit/s (for 2B+D) plus MONITOR and command/indication channels for the layer-1 device. Channel 1 contains two 64-kbit/s intercommunication channels plus MONITOR ...

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IOM -2 Interface Connections Output Driver Selection The type of the IOM output is selectable via bit ODS (ADF2 register). Thus when inactive (not transmitting) IDP0, 1 are either high impedance (ODS=1) or open drain "1" (ODS=0). Normally ...

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IOM Data Ports in Terminal Mode In this case the IOM has the 12-byte frame structure consisting of channels 0, 1 and 2 (see figure 11): – IDP0 carries the 2B+D channels from the S/T interface, and the MONITOR ...

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ISAC S/T Interface IDP0 Layer 1 (SBC) IDP1 R ISAC - Master Mode (IDC = 0) Master Figure 12a ® IOM Data Ports Terminal Mode (SPCR:SPM=0) Semiconductor Group IOM -2 Interface IDP0 ...

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Master Mode (IDC = 0) CH0 IPD0 B1 B2 MON0 (DD) R S/T IOM -2 Layer 1 IPD1 B1 B2 MON0 (DU) R IOM -2 S/T Layer 2 (b) Slave Mode (IDC = 1) CH0 IPD0 B1 B2 MON0 ...

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P Access to B and IC Channels The microprocessor can access the B and IC (intercommunication) channels at the IOM-2 interface by reading the B1CR/B2CR or by reading and writing the C1R/C2R registers. Furthermore it is possible to loop ...

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S/T Interface Layer-1 Functions Figure 13 Principle of B/IC-Channel Access Semiconductor Group Functional Description R ISAC -S TE ADF1 : IOF R (IOM off) Register: C1R/C2R B1CR/B2CR SPCR µ P Interface ITS05416 31 R IOM -2 Interface IDP0 (DD) IDP1 ...

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S/T Interface Layer-1 Functions FSC IDPO B1 B2 IC1 IC2 (DD) B1CR C2R B2CR C1R IDP1 B1 B2 IC1 IC2 (DU) Figure 14 Access to B and IC Channels in IOM (a) SPCR:C C1 monitoring, ...

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S/T Interface Layer-1 Functions FSC IDPO B1 B2 IC1 (DD) B1CR B2CR C1R IDP1 B1 B2 IC1 IC2 (DU) (b) SPCR:C C1 monitoring, IC looping (SQXR:IDC=0) Semiconductor Group Bx ICx BxCR CxR P µ IC2 ...

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S/T Interface Layer-1 Functions FSC IDPO B1 B2 IC1 (DD) B1CR C1R B2CR IDP1 B1 B2 IC1 IC2 (DU) (c) SPCR:C C1 access from/to S/T transmission of constant value to S/T Semiconductor Group Bx Bx ...

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S/T Interface Layer-1 Functions FSC IDPO B1 B2 IC1 (DD) B1CR B2CR IDP1 B1 B2 IC1 IC2 (DU) (d) SPCR:C C1 looping from/to S/T transmission of variable pattern to S/T Semiconductor Group Bx CxR P ...

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MONITOR Channel Handling In IOM-2 mode, the MONITOR channel protocol is a handshake protocol used for high speed information exchange between the ISAC-S TE and other devices, in MONITOR channel "0" or "1" (see figure 11). In the non-TE ...

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R IOM -2 Data Communication (MONITOR1) V/D Module R ITAC PSB 2110 C µ Figure 15 Examples of MONITOR Channel Applications in IOM The MONITOR channel operates on an asynchronous basis. While data transfers on the bus take place synchronized ...

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P µ MON FF MXE = 1 MOX = ADR FF MXC = 1 ADR MAC = 1 ADR MDA Int. DATA1 MOX = DATA1 DATA1 DATA1 DATA1 MDA Int. MOX = DATA2 DATA2 DATA2 DATA2 DATA2 MDA Int. MXC ...

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Before starting a transmission, the microprocessor should verify that the transmitter is inactive, i.e. that a possible previous transmission has been terminated. This is indicated by a "0" in the MONITOR Channel Active MAC status bit. After having written the ...

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C/I-Channel Handling The command/indication channel carries real-time status information between the ISAC-S TE and another device connected to the IOM. 1) One C/I channel (called C/I0) conveys the commands and indications between the layer-1 and the layer-2 parts of ...

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D-Channel Telemetry/ Packet Communication B-Channel Voice/Data Communication with D-Channel Signaling B-Channel Voice/Data Communication with D-Channel Signaling Figure 17 Applications of TIC Bus in IOM 2.3.6 TIC-Bus Access In IOM-2 interface mode the TIC-bus capability is only available in TE mode. ...

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ISAC-S TE itself (transmission of an HDLC frame). A software access request to the bus is effected by setting the BAC bit (CIX0 register) to "1". In the case of an access request, the ISAC-S TE ...

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B1 B2 MON0 D CI0 Figure 19 Structure of Last Octet of CH2 on IDP0 (DD) The stop/go bit is available to other layer-2 devices connected to the IOM to determine if they can access the S/T bus D channel. ...

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Layer-1 Functions for the S/T Interface – line transceiver functions for the S/T interface according to the electrical specifications of CCITT I.430; – conversion of the frame structure between IOM and S/T interface; – conversion from/to binary to/from pseudo-ternary ...

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R ISAC - ISAC -S TR LT-T 1) The maximum line attenuation toleratet by the ISAC TR TE1 < < ISAC -S TE TE1 TE8 Figure 20 ...

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S/T Interface According to CCITT recommendation I.430 pseudo-ternary encoding with 100% pulse width is used on the S/T interface. A logical "1" corresponds to a neutral level (no current), whereas logical "0" ’s are encoded as alternating positive and ...

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Analog Functions For both receive and transmit direction, a 2:1 transformer is used to connect the ISAC-S TE transceiver to the 4 wire S/T interface. The corrections are shown in figure 23 µF GND Figure ...

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Symmetrical S-Bus Receiver The S-bus receiver of the PSB 2186 is a symmetrical one. This results in a simplification of the external circuitry and PCB layout to meet the I.430 receiver input impedance specification. 2.4.3 S/T-Interface Circuitry In order to ...

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SR1 ISAC -S TE GND PSB 2186 1.8 k SR2 47 pF Figure 26 External Receiver Circuitry 2.4.4 S/T Interface Pre-Filter Compensation To compensate for the extra delay introduced into the received signal by a filter, ...

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Receiver Functions 2.4.5.1 Receive Signal Oversampling In order to additionally reduce the bit error rate in severe conditions, the ISAC-S TE performs oversampling of the received signal and uses majority decision logic. As illustrated in figure 27, each received ...

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Adaptive Receiver Characteristics The integrated receiver uses an adaptively switched threshold detector. The detector controls the switching of the receiver between two sensitivity levels. The hysteresis characteristics of the receiver are shown in figure 28 SR2 ...

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Level Detection Power Down In power down state, (see chapter 3.3.1) only an analog level detector is active. All clocks, including the IOM interface, are stopped. The data lines are "high", whereas the clocks are "low". An activation initiated ...

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Activation/Deactivation An incorporated finite state machine controls ISDN layer-1 activation/deactivation according to CCITT (see chapter 3.4). Loss of Synchronization / Resynchronization The following section describes the behaviour of the PSB 2186 in respect to the CTS test procedures for ...

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FAinfB_1fr This test uses a frame which has no framing and balancing bit. Info 4 Info 3 Device Settings PSB 2186 V1.1 none 2.4.7.3 FAinfD_1fr This test uses a frame which remains at binary ’1’ until the first code ...

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FAinfA_kfr This test uses a number of IX_96 kHz frames to check the loss of synchronization. Info 4 Info 3 Device Settings PSB 2186 V1 2.4.7.5 FAinfB_kfr This test uses a number of IX_I4noflag frames to ...

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FAinfD_kfr This test uses a number of IX_I4voil16 frames to check the loss of synchronization. The first Info 3 frame with the F -bit set to one looks like a i3_SFAL frame but correct info 3 ...

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D-Channel Access The D channel is submitted to the D-channel access procedure according to CCITT recommendation I.430. The D-channel access procedure according to CCITT I.430 including priority management is fully implemented in the ISAC-S: If collision detection is programmed ...

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Table 4 Priority Commands/Indications Command (upstream) Activate request, set priority 8 Activate request, set priority 10 Indication (downstream) Activate indication with priority class 8 Activate indication with priority class 10 2.4.9 S- and Q-Channel Access Access to the received/transmitted S- ...

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Table 5 S- and Q-Bit Position Identification and Multiframe Structure S- and Q-Channel Structure Frame Number NT-to-TE F -Bit A Position 1 ONE 2 ZERO 3 ZERO 4 ZERO 5 ZERO 6 ONE 7 ZERO 8 ZERO 9 ZERO 10 ...

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Terminal Specific Functions Watchdog and External Awake In addition to the ISAC-S TE standard functions supporting the ISDN-basic access, the ISAC-S TE contains optional functions, useful in various terminal configurations. The terminal specific functions are enabled by setting bit ...

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The RSS bit should be set to "1" by the user when the ISAC power-up to prevent an edge on the EAW line or a change in the C/I code from generating a reset pulse. Switching RSS ...

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Test Functions The ISAC-S TE provides several test and diagnostic functions which can be grouped as follows: digital loop via TLP (Test Loop, SPCR register) command bit: IDP1 is internally connected with IDP0, output from layer 1 (S/T) on ...

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Layer-2 Functions for the ISDN-Basic Access LAPD, layer 2 of the D-channel protocol (CCITT I.441) includes functions for: – Provision of one or more data link connections channel (multiple LAP). Discrimination between the data link connections ...

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Message Transfer Modes The HDLC controller can be programmed to operate in various modes, which are different in the treatment of the HDLC frame in the receive direction. Thus, the receive data flow and the address recognition features can ...

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In case of a 1-byte address, TEI1 and TEI2 will be used as compare registers. According to the X.25 LAPB protocol, the value in TEI1 will be interpreted as command and the value in TEI2 as response. The control field ...

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Protocol Operations (auto-mode) In addition to address recognition all S and I frames are processed in hardware in the auto- mode. The following functions are performed: – update of transmit and receive counter – evaluation of transmit and receive ...

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Reception of Frames byte FIFO buffer (receive pools) is provided in the receive direction. The control of the data transfer between the CPU and the ISAC handled via interrupts. There are two different interrupt ...

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Address Flag High Auto-Mode SAP1,SAP2 FE,FC (U-and - -Frames) (Note 1) SAP1,SAP2 Non-Auto FE,FC Mode (Note Transparent SAPR Mode 1 Transparent Mode 2 SAP1,SAP2 Transparent FE,FC Mode 3 Description of Symbols: Figure 32 Receive Data Flow Note 1Only if a ...

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When 32 bytes of a message longer than that are stored in the RFIFO, the CPU is prompted to read out the data by an RPF interrupt. The CPU must handle this interrupt before more than 32 additional bytes are ...

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Information about the received frame is available for the P when a RME interrupt is generated, as shown in table 6. Table 6 Receive Information at RME Interrupt Information Register (adr. First byte after flag SAPR (SAPI of LAPD address ...

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Transmission of Frames byte FIFO buffer (transmit pools) is provided in the transmit direction. If the transmit pool is ready (which is true after an XPR interrupt or if the XFW bit in STAR is set), ...

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If a 2-byte address field has been selected, the ISAC-S TE takes the contents of the XAD 1 register to build the high byte of the address field, and the contents of the XAD 2 register to build the low ...

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The termination of the transmission operation may be indicated either with: – XPR interrupt positive acknowledgement has been received, – XMR interrupt negative acknowledgement has been received, i.e. the transmitted message must be repeated (XMR = ...

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Documentation of the Auto Mode The auto mode of the ICC and ISAC only applicable for the states 7 and 8 of the LAPD protocol. All other states ( have to be performed in Non-Auto ...

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There is 1 symbol at a path b.1. marks the beginning of a path, for which a.3 applies. c.Symbols at an internal or external message box. There are 2 symbols at a message box. This symbol ...

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The text describes an interrupt associated with the contents of the e.1. Text box. The interrupt is always associated with the box contents, if the Box interrupt name is not followed by a ...

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Additional General Considerations when Using the Auto Mode a)Switching from auto-mode to non-auto mode. As mentioned in the introduction the auto mode is only applicable in the states 7 and 8 of the LAPD. Therefore whenever these states have ...

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The occurence of an XMR interrupt in auto-mode after an XIF command indicates that the I frame sent was either rejected by the Peer Entity or that a collision occured on the S interface. In both cases the I frame ...

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Q921: Invalid Frames and Frame Abortion Paragraphs 2.9 and 2.10 of the Q.921 deal with Invalid Frames and Frame Abortion. In the following the original text is given. Q.921 § 2.9: Invalid Frames An invalid frame is a frame which: ...

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The reaction to § 2.10 has been already discussed under a) Necessary Software Actions The software should read the Register RSTA after a RME-interrupt. After having read RAB = 1 or CRC = 0, all frame contents read from the ...

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For a better understanding we insert the text of § 3.6.1, which is referred to in § 5.8.5 and which reads: § 3.6.1 Commands and responses The following commands and responses are used by either the user or the network ...

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Table 7 Q.921 (Table 5) Application Format Information Transfer Supervisory Unacknowledged and Multiple- Frame acknowledged Information Transfer Unnumbe- red Connection Management *Note: Use of the XID frame other than for parameter negotiation procedures (see § 5.4) is for further study. ...

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Reaction of the ISAC the following various possible actions to be taken according to § 5.8.5 parts a) through c) are discussed separately. a) There are different types of undefined frames: 1) I-frame which is not a command ...

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The processor should read RBCH, RBCL after each RPF, RME interrupt. If after an RPF or RME the byte count exceeds 528 then CMDR:RRES should be written (abort of frame). The frame was invalid in this case but it was ...

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Further Criteria Leading to a Re-Establishment Q.921 § 5.7.1: Criteria for Re-Establishment § 5.7.1 Criteria for re-establishment The criteria for re-establishing the multiple frame mode of operation are defined in this section by the following conditions: a) The receipt while ...

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Further Possible Error Conditions Appendix II of Q.921: Further Possible Error Conditions Table 8 Q.921 Management Entity Actions for MDL Error Indications Error Type Error Error Code Condition Receipt of A Supervisory unsolicited ( response B DM(F = ...

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Table 8 Q.921 Management Entity Actions for MDL Error Indications (cont’d) Error Type Error Error Code Condition Other J N(R) Error K Receipt of FRMR response L Receipt of non implemented frame M Receipt of I-field (see not permitted Note ...

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I-frame CMDR:RMC Cont. -> Layer 3 Figure 35 Interrupt Service Routine after RME Semiconductor Group RME & /TIN & /PCE = 1 RSTA:RAB CRC RSTA:RDO ISTA:RFO ...

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TIN or PCE Re-establishment of the link Figure 36 Interrupt Service Routines after RPF (top), TIN or PCE (middle left), RSC (middle right), and XDU or RFO (bottom) Semiconductor Group RPF & /TIN & /PCE Y RBCL > 528 RBCH, ...

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XPR & /TIN & /PCE Has a frame been sent since last CMDR:XRES ? Y A frame is currently transmitted ? N Last frame written to XFIFO was an I-frame ? N SRC * ? Y ACK1 & ACK2 * ...

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Figure 38 Interrupt Service Routine after XMR Semiconductor Group XMR & /TIN & /PCE N SRC ? Y Re-transmit the - frame sent last 91 Functional Description Re-transmit the frame sent last ITD05894 ...

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MULTIPLE FRAME ESTABLISHED DL ESTABLISH RELEASE REQUEST REQUEST DISCARD DISCARD I QUEUE I QUEUE ESTABLISH DATA LINK SET TX DISC LAYER 3 XFIFO INITIATED CMDR XTF MODE NAM STOP T203 5 RESTART T200 ...

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MULTIPLE FRAME ESTABLISHED TIMER T200 EXPIRY YES PEER BUSY GET LAST TRANSMIT TRANSMITTED ENQUIRY I FRAME V( COMMAND V( CLEAR ACKNOWLEDGE PENDING START ...

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STORE STAR2: WFA Figure 39c Semiconductor Group 7 MULTIPLE FRAME ESTABLISHED RME RME SABME DISC RCHR: RCHR: DISCARD F=P I QUEUE XFIFO CMDR XTF CLEAR TX UA EXCEPTION XFIFO CONDITIONS CMDR XTF MDL-ERROR DL-RELEASE INDICATION ...

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MULTIPLE FRAME ESTABLISHED RME DM RHCR YES RHCR NO MDL-ERROR MDL-ERROR INDICATION INDICATION (E) (B) 7 ESTABLISH MULTIPLE DATA LINK FRAME ESTABLISHED CLEAR LAYER 3 INITIATED MODE NAM 5 AWAITING ESTABLISHM. Note: These signals are generated ...

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MULTIPLE FRAME ESTABLISHED RR RSC / CLEAR PEER RECEIVER BUSY STAR:RRNR NO COMMAND YES YES ENQUIRY RESPONSE STAR2:SDET Figure 39 f Figure 39e Semiconductor Group YES YES ...

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NO < _ < _ V(A) N(R) V(S) YES NO N(R) = V(S) YES XPR / V(A) = N(R) STAR2:WFA STOP T200 START T203 7 MULTIPLE FRAME ESTABLISHED Figure 39f Semiconductor Group N(R) ERROR RECOVERY MODE NAM 5 YES ...

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MULTIPLE FRAME ESTABLISHED RNR RSC / SET PEER RECEIVER BUSY STAR:RRNR NO COMMAND YES YES ENQUIRY RESPONSE STAR2:SDET XPR / STAR2:WFA Figure 39g Semiconductor Group YES MDL-ERROR- INDICATION (A) NO < ...

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MULTIPLE FRAME ESTABLISHED I COMMAND OWN YES RECEIVER BUSY NO NO N(S) = V(R) YES V( CLEAR REJECT EXCEPTION RME DL-DATA INDICATION RFIFO, RHCR YES YES ACKNOWLEDGE PENDING NO ACKNOWLEDGE PENDING ...

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NO < < < < V(A) N(R) V(S) YES PEER NO RECEIVER BUSY YES XPR / V(A) = N(R) STAR2:WFA Figure 39i Semiconductor Group NO N(R) = V(S) YES XPR / V(A) = N(R) N(R) ...

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Figure 39j Semiconductor Group Functional Description 7 MULTIPLE FRAME ESTABLISHED ACKNOWLEDGE PENDING NO ACKNOWLEDGE PENDING YES CLEAR ACKNOWLEDGE PENDING STAR2:SDET 7 MULTIPLE FRAME ESTABLISHED ITD02374 101 ...

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TIMER RECOVERY DL ESTABLISH REQUEST DISCARD I QUEUE ESTABLISH DATA LINK SET LAYER 3 INITIATED MODE NAM 5 AWAITING ESTABLISHM. Figure 40a Semiconductor Group DL DL-DATA ESTABLISH REQUEST REQUEST DISCARD PUT IN I QUEUE I QUEUE I FRAME RC ...

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TIMER RECOVERY TIMER T200 EXPIRY YES RC = N200 NO YES V(S) = V(A) NO YES PEER BUSY GET LAST TRANSMIT TRANSMITTED ENQUIRY I FRAME V( COMMAND V( CLEAR ACKNOWLEDGE PENDING ...

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STORE STAR2: WFA Figure 40c Semiconductor Group 8 TIMER RECOVERY RME RME SABME DISC RHCR: RHCR: DISCARD QUEUE XFIFO CMDR XTF CLEAR TX UA EXCEPTION XFIFO CONDITIONS CMDR XTF MDL-ERROR DL-RELEASE ...

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TIMER RECOVERY RME DM RHCR YES RHCR NO MDL-ERROR MDL-ERROR INDICATION INDICATION (E) (B) ESTABLISH DATA LINK CLEAR LAYER 3 INITIATED MODE NAM 5 AWAITING ESTABLISHM. Note: These signals are generated outside of this SDL representation, ...

Page 106

TIMER RECOVERY RR RSC / CLEAR PEER RECEIVER BUSY STAR:RRNR NO COMMAND YES YES ENQUIRY RESPONSE STAR2:SDET NO < < < < V(A) N(R) V(S) YES XPR / V(A) = N(R) ...

Page 107

TIMER RECOVERY RNR BUSY STAR:RRNR NO COMMAND YES YES ENQUIRY RESPONSE STAR2:SDET NO < < V(A) N(R) V(S) YES XPR / V(A) = N(R) STAR2:WFA 8 TIMER RECOVERY Figure 40f Semiconductor Group RSC ...

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TIMER RECOVERY I COMMAND OWN YES RECEIVER BUSY NO NO N(S) = V(S) YES V( INFORMATION CLEAR REJECT EXCEPTION RME DL-DATA INDICATION RFIFO, RHCR YES YES ACKNOWLEDGE PENDING NO ACKNOWLEDGE PENDING ...

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V(A) N(R) YES V(A) = N(R) 8 TIMER RECOVERY Figure 40h Figure 40i Semiconductor Group NO V(S) XPR / N(R) ERROR RECOVERY STAR2:WFA MODE NAM 5 AWAITING ESTABLISHM. 8 TIMER RECOVERY ACKNOWLEDGE PENDING NO ACKNOWLEDGE ...

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RELEVANT STATES (NOTE 1) DL UNIT DATA REQUEST PLACE IN UI QUEUE UI FRAME QUEUED UP NOTE 2 Note 1: The relevant states are as follows 4 TEI-assigned 5 Awaiting-establishement 6 Awaiting-release 7 Multiple-frame-established 8 Timer-recovery Note 2: The data ...

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RELEVANT STATES (NOTE 1) CONTROL FIELD ERROR (W) Note 1: The relevant states are as follows 7 Multiple-frame-established 8 Timer-recovery Figure 41b Semiconductor Group INFO NOT INCORRECT PERMITTED LENGHT (X) (X) PCE / MDL-ERROR INDICATION (L,M,N,O) ESTABLISH DATA LINK CLEAR ...

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RELEVANT STATES (NOTE 1) CONTROL FIELD ERROR (W) Note 1: The relevant states are as follows: 4 TEI-assigned 5 Awaiting-establishment 6 Awaiting-release Note 2: The data link layer returns to the state it was in prior to the events shown ...

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N(R) ESTABLISH ERROR DATA LINK RECOVERY MDL-ERROR EXCEPTION INDICATION(J) CONDITION PCE CMDR:RHR,XRES MODE: NAM ESTABLISH DATA LINK CLEAR TX SABME LAYER 3 XFIFO INITIATED CMDR:XTF RESTART T200 STOP T203 Figure 41d Semiconductor Group CLEAR EXCEPTION CONDITIONS CMDR:RHR,XRES CLEAR CLEAR PEER ...

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ENQUIRY RESPONSE OWN YES RECEIVER BUSY RESPONSE STAR2:SDET CLEAR ACKNOWLEDGE PENDING Note: The generation of the correct number of signals in order to cause the required retransmission of I frames does not alter their ...

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Operational Description The ISAC-S TE, designed for the connection of subscribers to an ISDN using a standard S/T interface, has the following application, corresponding to the operating mode explained in chapter 2: Terminal Equipment TE1, TA e.g. ISDN-feature telephone, ...

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The microprocessor interface signals are summarized in table 9. Table 9 ® P Interface of the ISAC -S TE Pin No. Pin No. Pin No. P-DIP-40 P-LCC-44 P-MQFP- ...

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Interrupt Structure and Logic Since the ISAC-S TE provides only one interrupt request output (INT), the cause of an interrupt is determined by the microprocessor by reading the Interrupt Status Register ISTA. In this register, seven interrupt sources can ...

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A read of the ISTA register clears all bits except EXI and CISQ. CISQ is cleared by reading CIR0. A read of EXIR clears the EXI bit in ISTA as well as the EXIR register. When all bits in ISTA ...

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MOS-Interrupt Logic The MONITOR Data Receive (MDR) and the MONITOR End of Reception (MER) interrupt status bits have two enable bits, MONITOR Receive interrupt Enable (MRE) and MR bit Control (MRC). The MONITOR channel Data Acknowledged (MDA) and MONITOR channel ...

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INT A status bit is set. This causes an interrupt. The microprocessor starts its service routine and reads the status registers. A new status bit is set before the first status bit has been read. The first status bit is ...

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DCL INT RD Figure 45 Timing of INT Pin The INT line is switched with the rising edge of DCL pending interrupts are internally stored, a reading of ISTA respectively EXIR or CIR0 switches the INT line to ...

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FSC DIU DIU IDP1 (DU IDP0 (DD) DCL Figure 46 ® Deactivation of the IOM Interface The clock pulses will be enabled again when the IDP1 line is pulled low (bit SPU, SPCR register) i.e. the C/I command ...

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SPU = 1 FSC IDP1 (DU) IDP0 (DD) FSC IDP1 (DU) 0 IDP0 (DD) DCL Note : IDP0 is input and IDP1 is low during IDP0 is low and IDP1 is input during Figure 47 ® Activation ...

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The ISAC-S TE supplies IOM timing signals as long as there is no DIU command in the C/I (C/ I0) channel. If timing signals are no longer required and activation is not yet requested, this is indicated by programming DIU ...

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Layer-1 Command/Indication Codes and State Diagrams Table 10 Commands Command (upstream) Timing Reset Send continuous zeros Send single zeros Activate request, set priority 8 Activate request, set priority 10 Activate request loop Deactivate indication upstream (x) unconditional commands Important ...

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Table 11 Indications Indication (downstream) Power-up Deactivate request Error indication Level detected Activate request downstream Test indication Awake test indication Activate indication with priority class 8 Activate indication with priority class 10 Deactivate indication downstream Semiconductor Group Abbr. Code Remarks ...

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F3 Power-Down This is the deactivated state of the physical protocol. The receive line awake unit is active except during an RST pulse. Clocks are disabled if SQXR:CFS=1. The power consumption in this state is approximately 80 mW when the ...

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F8 Lost Framing This is the condition where the ISAC-S TE has lost frame synchronization and is awaiting re- synchronization by INFO2 or INFO4 or deactivation by INFO0. Unconditional States Loop 3 Closed On Activate Request Loop command, INFO3 is ...

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F5 Unsynchroniz Synchronized i2 RSYD X F8 Lost Framing Figure 49a State Diagram Semiconductor Group DID DIU RST F3 Power Down DIU PU ARU TIM F4 Pend. Act ...

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ARL Loop i3 Loop OUT R IOM S : Only Internally Forcing Commands can be : ARL, RES, TM, SSP : is Single Pulses Test Pulses, Figure 49b State Diagram: Unconditional Transitions Semiconductor Group PU ...

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Example of Activation/Deactivation An example of an activation/deactivation of the S interface, with the time relationships mentioned in the previous chapters, is shown in figure 50, in the case of an ISAC and an ISAC-S in LT-S Mode. ISAC ...

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Control of Layer-2 Data Transfer The control of the data transfer phase is mainly done by commands from the P to ISAC-S TE via the Command Register (CMDR). Table 12 gives a summary of possible interrupts from the HDLC ...

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Table 12 (cont’d) Mnemonic Register Meaning (addr. hex) XPR ISTA (20) Transmit Pool Ready. Further octets of an HDLC frame can be written to XFIFO. If XIFC was issued (auto mode), indicates that the message was successfully acknowledged with S ...

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Table 13 List of Commands (CMDR (21) Register) Command HEX Bit 7…0 Mnemonic RMC 80 1000 RRES 40 0100 RNR 20 0010 STI 10 0001 XTFC 0A 0000 (XTF+XME) XIFC 06 0000 (XIF+XME) XTF 08 0000 XIF 04 0000 XRES ...

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HDLC-Frame Reception Assuming a normally running communication link (layer-1 activated, layer-2 link established, TEI assigned), figure 51 illustrates the transfer frame via the D channel. The transmitter is shown on the left and the receiver on ...

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Address Flag High Auto-Mode SAP1,SAP2 FE,FC (U-and - -Frames) (Note 1) SAP1,SAP2 Non-Auto FE,FC Mode (Note Transparent SAPR Mode 1 Transparent Mode 2 SAP1,SAP2 Transparent FE,FC Mode 3 Description of Symbols: Figure 52 Receive Data Flow Note 1 Only if ...

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RME has been indicated, bits 0-4 of the RBCL register represent the number of bytes stored in the RFIFO. Bits 7-5 of RBCL and bits RBCH indicate the total number of 32-byte blocks which where stored ...

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The HDLC controller will request another data block by an XPR interrupt if there are no more than 32 bytes in XFIFO and the frame close command bit (Transmit Message End XME) has not been set. To this the microcontroller ...

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Table 14 (cont’d) Register (address (hex)) MODE (22) RBCL (25) RBCH (2A) SPCR (30) CIR0 (31) CIX0 (31) STCR (37) ADF1 (38) ADF2 (39) SQXR (3B) Semiconductor Group Value after Meaning Reset (hex) 00 – auto-mode – 1-octet address field ...

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Initialization During initialization a subset of registers have to be programmed to set the configuration parameters according to the application and desired features. They are listed in table 15. After reset, the ISAC IOM-1 mode. As ...

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Table 15 (cont’d) Register (address) Bit STCR (37 ) TSF H TBA2-0 MODE (22 ) MDS2-0 H TMD DIM2-0 TIMR (23 ) CNT H VALUE XAD1 ( XAD2 ( SAP1/2 (26 / TEI1/2 ...

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Detailed Register Description The parameterization of the ISAC-S TE and the transfer of data and control information between the P and ISAC performed through two register sets. The register set in the address range 00-2B controller. It ...

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Table 17 ® ISAC -S TE Address Map 30-3B Address Read (hex) Name Description 30 SPCR Serial Port Control Register 31 CIR0 Command/Indication Receive 0 32 MOR0 MONITOR Receive 0 33 CIR1 Command/Indication Receive 1 34 MOR1 MONITOR Receive 1 ...

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Table 18 Register Summary: HDLC Operation and Status Registers 7 20 RME RPF RSC H 20 RME RPF RSC H 21 XDOV XFW XRNR H 21 RMC RRES RNR H 22 MDS2 MDS1 MDS0 H 23 CNT H 24 XMR ...

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Table 19 Register Summary: Special Purpose Register IOM ® IOM - SPU SQC BAS H 31 RSS BAC ...

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HDLC Operation and Status Registers 4.1.1 Receive FIFO A read access to any address within the range 00-1F location selected by an internal pointer which is automatically incremented after each read access. This allows for the use of efficient ...

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XPR Transmit Pool Ready A data block bytes can be written to the XFIFO. An XPR interrupt will be generated in the following cases: – after an XTF or XIF command, when one transmit pool is ...

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Status Register Value after reset XDOV XFW XRNR XDOV Transmit Data Overflow More than 32 bytes have been written in one pool of the XFIFO, i.e. data has been overwritten. XFW Transmit FIFO Write ...

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Command Register Value after reset RMC RRES Note: The maximum time between writing to the CMDR register and the execution of the command is 2.5 DCL-clock cycles. During this time no further commands should be written ...

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XME Transmit Message End By setting this bit to "1" the processor indicates that the data block written last in the XFIFO completes the corresponding frame. The ISAC-S TE terminates the transmission by appending the CRC and the closing flag ...

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MDS2 Mode Number MDS1 of MDS0 Address Bytes Auto-mode Auto-mode Non-auto 1 mode Non-auto mode Reserved Transparent >1 mode ...

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IOM -2 Modes (ADF2:IMS = 1) Characteristics IOM-2 terminal mode SPCR:SPM = 0 Last octet of IOM channel 2 used for TIC-bus access Stop/go bit evaluated for D-channel access handling Reserved Applications TE mode 4.1.8 Timer Register Value after ...

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The internal timer procedure will be started in auto-mode: – after start of an I-frame transmission or – after an "RNR" S frame has been received. After the last retry, a timer interrupt (TIN bit in ISTA) is generated. The ...

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Extended Interrupt Register Value after reset XMR XDU XMR Transmit Message Repeat The transmission of the last frame has to be repeated because: – the ISAC-S TE has received a negative acknowledgement frame ...

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SAW Subscriber Awake Used only if terminal specific functions are enabled (STCR:TSF = 1). Indicates that a falling edge on the EAW line has been detected, in case the terminal specific functions are enabled (TSF bit in STCR). WOV Watchdog ...

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Receive Frame Byte Count Low Value after reset RBC7 RBC6 RBC5 RBC7-0 Receive Byte Count Eight least significant bits of the total number of bytes in a received message. Bits RBC4-0 indicate the length of the ...

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SAPI1 Register 7 SAPI1 SAPI1 Value Value of the first programmable Service Access Point Identifier (SAPI) according to the ISDN LAPD protocol. CRI Command/Response Interpretation CRI defines the end of the ISDN user-network interface the ISAC used ...

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CRC CRC Check The CRC is correct (1) or incorrect (0). RAB Receive Message Aborted The receive message was aborted by the remote station (1), i.e. a sequence of 7 1’s was detected. SA1-0 SAPI Address Identification TA TEI Address ...

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C/R Command/Response The C/R bit identifies a receive frame as either a command or a response, according to the LAPD rules: Command 0 1 4.1.16 SAPI2 Register 7 SAPI2 SAPI2 Value Value of the second programmable Service Access Point Identifier ...

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Note: If the value FF is programmed in TEI1, received numbered frames with address H SAPI1-TEI1 (SAPI1-TEIG) are not handled autonomously by the ISAC-S TE. In auto and non-auto-modes with one-byte address field, TEI1 is a command address, according to ...

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Note 1: S frames are handled automatically and are not transferred to the microprocessor. Note 2: For U frames (bit 0 of RHCR = 1) the control field the modulo 8 case. Note 3: For I frames ...

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OV Overflow A "1" in this bit position indicates a message longer than 4095 bytes. RBC8-11Receive Byte Count Four most significant bits of the total number of bytes in a received message. Note: Normally RBCH and RBCL should be read ...

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Special Purpose Registers: IOM The following register description is only valid if IOM-2 is selected (ADF2:IMS-1). 4.2.1 Serial Port Control Register Value after reset SPU 0 Important Note After a hardware reset the pin SDS1 is ...

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C2C1, C2C0 Channel 2 Connect Determines which of the two channels B2 or IC2 is connected to register C2R and/or B2CR, for monitoring, test-looping and switching data to/from the processor. C2R C2C1 C2C0 Read 0 0 IC2 0 1 IC2 ...

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CIC1 C/I Code 1 Change A change in the received Command/Indication code in IOM channel 1 has been rec- ognized. This bit is set when a new code is detected in one IOM frame reset by a read ...

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Note: Access is always granted by default to the ISAC-S TE/ICC with TIC-bus address (TBA2-0, STCR register) "7", which has the lowest priority in a bus configuration. CODX0 C/I Code 0 Transmit Code to be transmitted in the C/I channel ...

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Value after reset CODX1 C/I Code 1 Transmit Bits 7-2 of C/I channel 1 4.2.8 MONITOR Receive Channel 1 7 Contains the MONITOR data received in IOM channel 1 according to the MONITOR channel protocol. 4.2.9 MONITOR ...

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B1-Channel Register 7 Contains the value received in IOM channel B1, if programmed (see C1C1, C1C0, SPCR register). 4.2.13 Synchronous Transfer Control RegisterSTCR Value after reset TSF TBA2 TSF Terminal Specific Functions 0: No terminal specific ...

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ST1 Synchronous Transfer 1 When set, causes the ISAC generate an SIN-interrupt status (ISTA register) at the beginning of an IOM frame. ST0 Synchronous Transfer 0 When set, causes the ISAC generate an SIN-interrupt status (ISTA ...

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Additional Feature Register 1 Value after reset WTC1 WTC2 WTC1, 2 Watchdog Timer Control 1, 2 After the watchdog timer mode has been selected (STCR:TSF = CIX0:RSS = 1) the watchdog timer is started. During every ...

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ITF Inter-Frame Time Fill Selects the inter-frame time fill signal which is transmitted between HDLC frames. 0: idle (continuous 1 s), 1: flags (sequence of patterns: "0111 1110") Note applications with D-channel access handling (collision resolution), the only ...

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MONITOR Status Register Value after reset MDR1 MER1 MDA1 MDR1 MONITOR Channel 1 Data Received MER1 MONITOR Channel 1 End of Reception MDA1 MONITOR Channel 1 Data Acknowledged The remote end has acknowledged the MONITOR byte ...

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MXE1,0 MONITOR Transmit Interrupt Enable (IOM channel 1,0) MONITOR interrupt status MDA1/0, MAB1/0 generation is enabled (1) or masked (0). MXC1,0 MX Bit Control (IOM channel 1,0) Determines the value of the MX bit always "1" ...

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S, Q Channel Transmit Register Value after reset IDC CFS IDC IOM Direction Control 0: Master (normal) mode Layer 2 transmits IOM channel 0 and 2 on IDP1, channel 1 on IDP0. 1: Slave (test) mode ...

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CI1E C/I Channel 1 Interrupt Enable Interrupt generation of CIR0:CIC1 is enabled (1) or masked (0). SQIE S-, Q-Interrupt Enable Generation of CIR0:SQC status (and the accompanying CISQ interrupt is enabled (1) or masked (0). SQX1-4 Transmitted Q Bits transmitted ...

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Electrical Characteristics Absolute Maximum Ratings Parameter Voltage on any pin with respect to ground Ambient temperature under bias Storage temperature Maximum voltage Note: Stresses above those listed here may cause permanent damage to the device. Exposure ...

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Transmitter Input Current The destruction limits for negative input signals are given in figure 55 100 0.5 0.05 - Figure 55 The destruction limits for positive input signals are given in figure ...

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Receiver Input Current The destruction limits are given in figure . 0.1 0.01 0.005 -10 10 Semiconductor Group Electrical Characteristics 300 . ITD02338 178 t w1 ...

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DC Characteristics = ° Parameter Symbol L-input voltage V IL H-input voltage V IH L-output voltage V OL L-output voltage V OL1 (IDP0) H-output voltage V OH ...

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DC Characteristics = ° Parameter Symbol Input leakage I LIPD current internal pull-down Absolute value output pulse amplitude (VSX2 – VSX1) Transmitter out- I ...

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Capacitances = 25 ° Parameter Input capacitance I/O capacitance Output capacitance against V SSA Input capacitance Load capacitance Recommended Oscillator Circuits Crystal ...

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XTAL1 Clock Characteristics (external oscillator input) Parameter Duty cycle AC Characteristics = ° Inputs are driven to 2.4 V for a logical "1" and to 0.4 V for a ...

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Microprocessor Interface Timing Siemens/Intel Bus Mode AD0 - AD7 Figure 59 Microprocessor Read Cycle AD0 -AD7 Figure 60 Microprocessor Write Cycle ALE AD0 - AD7 Figure 61 ...

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Figure 62 Non-Multiplexed Address Timing Motorola Bus Mode R Figure 63 Microprocessor Read Timing Figure 64 Microprocessor Write Cycle Semiconductor Group t AS Address ...

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AD0 - AD5 Figure 65 Non-Multiplexed Address Timing Microprocessor Interface Timing Parameter ALE pulse width Address setup time to ALE Address hold time from ALE Address latch setup time to WR, RD Address setup time Address hold ...

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Serial Interface Timing FSC1 (O) DCL (O) IDP0 IDP0/1 (O) SDS1 (O) BCL (O) Figure 66 ® IOM Timing (TE mode) ® IOM Timing Parameter IOM output data delay IOM input data setup IOM input data hold FSC1 ...

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HDLC Mode (ADF2: IMS = 0, ADF1: TEM = 1, MODE: DIM2 – 101 – 111) Figure 67 FSC1 (strobe) Characteristics HDLC Mode Timing Parameter FSC1 set-up time FSC1 hold time Output data from high impedance to active ...

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Clock Timing The clocks are summarized in table 20, with the respective duty ratios. Table 20 ® ISAC -S TE Clock Signals (IOM Application DCL TE o:1536 kHz* 3:2 The 1536-kHz clock is phase-locked to the receive S signal, and ...

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R DCL (IOM -2) t BCD BCL t FSD FSC1 t SSD t SBD SDS1 Figure 69 Timing Relationships between ISAC Table 21 Parameter Bit clock delay SDS1 delay from DCL SDS1 delay from BCL Semiconductor Group t BCD ® ...

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V 0.8 V Figure 70 Definition of Clock Period and Width Table 22 DCL-Clock Characteristics (IOM Parameter Symbol t (TE) 1536 kHz PO t WHO t WLO Semiconductor Group ® -2) Limit Values min. ...

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Jitter In TE mode, the timing extraction jitter of the ISAC-S conforms to CCITT Recommendation I.430 (– the S-interface bit period). Description of the Receive PLL (RPLL) of the ISAC-S TE The receive ...

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ISAC -S TE Low Level Controller The following paragraphs outline the functionality and structure of a software driver example for the ISAC-S TE. This example is based on the Siemens Low Level Controllers (LLC’s) for Basic Access IC ...

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OPERATING SYSTEM and Higher Level Protocol Software FUNCTION CALLS ... Driver Functions SBC Part Layer-1 Functions Figure 73 LLC Architecture The ISAC-S TE LLC supports following standard functions: – Initialization of the SBC (layer 1) part. – Activation of layer ...

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HDLC-frame transmission. – Programming of TEI and SAPI values. – HDLC-transceiver control. – Local test loop switching. The LLC assumes that the ISAC operating in an IOM-2 TE configuration. In addition to the ISAC-S TE standard functions ...

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External Functions The LLC-program listing shows some references to external functions (indicated by an ’IMPORT’ declaration). These functions are used by the LLC but are not part of it. These external functions must be provided by the operating system ...

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Decode_U_Frame_BASIC () Decode_U_Frame_BASIC is called by the LLC-interrupt server to transfer a received HDLC U frame to a higher layer protocol software. Following information is passed to Decode_U_Frame_BASIC: ’pei’: (refer to Decode_S_Frame). ’sapi’: (refer to Decode_S_Frame). ’tei’: (refer to Decode_S_Frame). ...

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LLC-Code Elements 6.3.1 Structures The Structure ’ISAC’ As the various routines in the LLC require facilities to store information about the device they control, the global variabel ’pt’ of the type ’ISAC’ has been introduced. The type ’ISAC’ is ...

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The Structure ’FRAME_PASS’ The variable ’fp’ of the type FRAME_PASS is used when the LLC-interrupt server has received a valid HDLC frame. A pointer to ’fp’ is passed to PassLongFrame_BASIC. FRAME_PASS contains all information about the received ...

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Macro Definitions Error conditions and other states of the ISAC-S TE must be reported to higher layers. This reporting is realized by a few macros which are executed when such conditions are detected. These macros can be mapped to ...

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Interrupts Int_ICC called in the case of ISAC-S TE interrupts. The following interrupts are handled directly in Int_ICC: ’Transmit pool ready’ interrupt (ISTA:XPR) ’Timer’ interrupt (ISTA:TIN). ’Receive Status Change’ interrupt (ISTA:RSC). ’Extended’ interrupt (ISTA:EXI). The ’Receive ...

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