RTL8316 REALTEK, RTL8316 Datasheet

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RTL8316

Manufacturer Part Number
RTL8316
Description
Single Chip 16-Port 10/100 Ethernet Switch Controller with Embedded Memory
Manufacturer
REALTEK
Datasheet

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1. Features........................................................................ 2
2. General Description .................................................... 2
3. Pin Assignments .......................................................... 4
4. Pin Description ............................................................ 5
5. Block Diagram........................................................... 10
6. Functional Description ..............................................11
2001/11/09
4.1 RMII Interface (Port #0 ~ Port #15)....................... 5
4.2 Serial Management Interface.................................. 6
4.3 System Pins ............................................................ 6
4.4 Mode Control Pins ................................................. 6
4.5 LED Pins ................................................................ 9
4.6 Power / Ground Pins .............................................. 9
4.7 Test Pins ................................................................. 9
6.1 Reset..................................................................... 11
6.2 RMII interface...................................................... 11
6.3 Serial Management Interface MDC/MDIO.......... 11
6.4 Address Search and Learning............................... 12
6.5 Address Aging...................................................... 12
6.6 Illegal Frames....................................................... 12
6.7 802.1D Reserved Group Addresses Filtering ....... 12
6.8 Back off Algorithm .............................................. 12
6.9 Inter-Frame Gap ................................................... 12
WITH EMBEDDED MEMORY
16-PORT 10/100 ETHERNET
REALTEK SINGLE CHIP
SWITCH CONTROLLER
RTL8316
1
7. Electrical Characteristics ......................................... 17
8. Mechanical Information ........................................... 20
9. Revision History ........................................................ 21
6.10 Buffer Management ........................................... 13
6.11 Buffer Manager .................................................. 13
6.12 Data Reception................................................... 13
6.13 Data Forwarding ................................................ 13
6.14 Flow Control ...................................................... 14
6.15 Broadcast Storm Filtering Control ..................... 14
6.16 Head-Of-Line Blocking Prevention ................... 14
6.17 Port Trunking and Load Balance........................ 14
6.18 Force Mode Setting of Port ability..................... 15
6.19 Port Based HOME VLAN Function .................. 15
6.20 QoS Function ..................................................... 16
7.1 Temperature Limit Ratings: ................................. 17
7.2 DC Characteristics ............................................... 17
7.3 AC Characteristics ............................................... 17
7.3.1 Reset and Clock Timing ............................... 17
7.3.2 RMII Timing................................................. 18
7.3.3 PHY Management (SMI) Timing ................. 19
RTL8316
Rev.1.72

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RTL8316 Summary of contents

Page 1

... Force Mode Setting of Port ability..................... 15 6.19 Port Based HOME VLAN Function .................. 15 6.20 QoS Function ..................................................... 16 7. Electrical Characteristics ......................................... 17 7.1 Temperature Limit Ratings: ................................. 17 7.2 DC Characteristics ............................................... 17 7.3 AC Characteristics ............................................... 17 7.3.1 Reset and Clock Timing ............................... 17 7.3.2 RMII Timing................................................. 18 7.3.3 PHY Management (SMI) Timing ................. 19 8. Mechanical Information ........................................... 20 9. Revision History ........................................................ 21 1 RTL8316 Rev.1.72 ...

Page 2

... Two ports can support Speed, Duplex and Flow-control abilities through force setting mode for fiber applications. The address look-up table consists of 8K entries of hash table and a 128 entries of CAM. The RTL8316 uses 13 bit MAC address direct mapping method to search the destination MAC address and record source MAC address from and to the hash table. ...

Page 3

... The RTL8316 provides a Broadcast storm filtering function which is provided to compensate for unusual broadcast storm interference. The RTL8316 port trunking function supports the ability to aggregate four 10/100 ports into a single logical link to increase the bandwidth between the RTL8316 and another device (switch or server) with trunking function enabled. Four Trunk Groups are supported ...

Page 4

... P12RXD1 120 P13TXE/ P14ForceSPD 121 P13TXD0/ P14ForceDUPX 122 P13TXD1 123 P13CRSDV 124 P13RXD0 125 P13RXD1 126 P14TXE/ EnP15ForceMode 127 P14TXD0/ P15ForceFCTL 128 2001/11/09 RTL8316 4 RTL8316 64 P6TXD1 63 P6TXD0/ EnPortPri[1] 62 P6TXE/ EnPortPri[0] 61 GND 60 VCC 59 P5RXD1 58 P5RXD0 57 P5CRSDV 56 P5TXD1 55 P5TXD0/ En8021pPri 54 P5TXE/ EnDSPri ...

Page 5

... P6CRSDV, P7CRSDV, P8CRSDV, P9CRSDV, P10CRSDV, P11CRSDV, P12CRSDV, P13CRSDV, P14CRSDV, P15CRSDV, 2001/11/09 Type Pin No O 17, RMII Transmit Enable: The RTL8316 asserts high to indicate that 26, valid data for transmission is presented on the TXD[1:0 34, synchronous with REFCLK. 40, 48, 54, 62, 77, 68, 86, 95, 107, 115, 121, ...

Page 6

... System Reset: Active low to reset the system to a known state. After (P-up) power-on reset (low to high), the configuration modes from Mode Pins are sampled and determined, then RTL8316 will start to access the management register of PHY devices and restart the Auto-negation. Type Pin No ...

Page 7

... Enable 802.1D specified reserved group MAC addresses frame filtering: When network control frames are received with the destination MAC address as a group MAC address: (01-80-C2-00-00-03 ~ 01-80-C2-00-00-0F), the RTL8316 will drop the frames if the EnCtrlFrameFilter is set. Otherswise , it will be flooded. The value of EnCtrlFrameFilter is trapped on the power on reset. ...

Page 8

... Enable Flow Control Ability Auto Turn Off: Latched during hardware reset. Enable Auto turn off low priority queue's flow control ability 1~2 seconds whenever the port received a high priority frame. The flow control ability will be re-enabled when no high priority frames are received for the 1~2 second period. 1: Enabled 0: Disabled 8 RTL8316 Rev.1.72 ...

Page 9

... Embedded DRAM Ground (3 pins) Type Pin No I P4TXE Enable Accept Error Packets: Enables the RTL8316 to accept error packets and forward them to the destination port. But the acceptable error packet is only limited 1536 bytes. Note: Used for testing only. Do Not pull-up this pin. I ...

Page 10

... Queue RX/TX F.P.P. FIFOs Flow control 128-entry Address CAM 2001/11/09 RMII PHY Management 10/100 I/F MAC EDORAM I/F FIFOs, QUEUE, DMA Flow Engine Control, RX/TX F.P.P. FIFO Switching Logic Address-Lookup Engine F.P.P FIFO 10 RTL8316 LED I/F Packet Buffer Space (4 Mbits) Page Pointer Space 8K-entry Address Table Buffer Manager Rev.1.72 ...

Page 11

... PHY management registers via MDC/MDIO most important that the RTL8316 and connected PHYs use the same reset signal source. Otherwise, if the reset action of PHY is finished after the RTL8316, there is no guarantee of proper operation on the expected port speed, duplex and flow control ability. ...

Page 12

... Address Search and Learning The address look-up table consists of 8K entries of hash table and 128 entries of CAM. The RTL8316 uses the last 13 bits of MAC address Direct Mapping method to index the 8K-entry look-up table for address searching and learning. If the mapped location in the 8K entries is occupied, then the RTL8316 will compare the destination MAC address with the contents of the CAM for address searching and store source MAC address to CAM for address learning ...

Page 13

... Data FIFO first and then is moved into the Packet Buffer by the Receive DMA Engine, using the free page pointers in the Receive Free Page Pointer FIFO via the Get Free Page command. The RTL8316 always attempts to fill the Receive Free Page Pointer FIFO with free page pointers. ...

Page 14

... The RTL8316 incorporates a simple mechanism to prevent Head-Of-Line blocking problems when flow control is disabled. When the flow control function is disabled, the RTL8316 will first check the destination address of the incoming packet. If the destined port is congested, then the RTL8316 will discard this packet to avoid blocking the next packet which is going to a non-congested port. ...

Page 15

... EnForceMode = 1 indicates the force mode has been enabled on the corresponding port. The corresponding port of the RTL8316 will use the duplex, speed and flow control ability as these pins are set. Furthermore, the RTL8316 will write the DUPLEX and SPEED to bit 13 and bit 8 of PHY’s register 0, and bit 12 of register 0 will be written to be '0' to enable the corresponding PHY port to act at force mode ...

Page 16

... EnProtPri[1:0], En8021pPri and EnDSPri respectively and can be used together. There are 2 priority queues, high and low, supported by the RTL8316 to buffer high and low priority frames. The queue service rate is based on the Weighted Round Robin algorithm. The packet based service weight ratio of high-priority and low-priority queuing can be set as 2:1, 4:1, 8:1 or " ...

Page 17

... V IN GND V OUT GND I OUT= 0mA, Description Minimum t1 t2 Reset and Clock Timing 17 Maximum +125 70 Minimum Typical 0.9 * Vcc 0.5 * Vcc -0.5 -1.0 -10 Typical Maximum -- 1000 - - RTL8316 Units ℃ ℃ Maximum Units Vcc V 0.1 * Vcc V Vcc+0.5 V 0.3 * Vcc V 1.0 μA 10 μA 370 mA Units MHZ ns ns Rev.1.72 ...

Page 18

... CSRDV,RXD to REFCLK rising setup time t7 CRSDV,RXD to REFCLK rising hold time REFCLK TXE TXD[1:0] REFCLK CRSDV RXD[1:0] 2001/11/09 Minimum Typical - DATA RMII Transmit Timing DATA RMII Receive Timing 18 RTL8316 Maximum Units - Rev.1.72 ...

Page 19

... MDC/MDIO actives from RST# deasserted 2001/11/09 Minimum - - - MDC t4 MDIO data MDIO Write Timing MDC MDIO MDIO Read Timing RST# MDC MDIO MDC/MDIO Reset Timing 19 Typical Maximum SYSCK * 32 - SYSCK * 16 - SYSCK * 500 - t5 t6 data t7 high high RTL8316 Units Rev.1.72 ...

Page 20

... Dimension Dimensions D & not include interlead flash. Min Typical Max 2. Dimension b does not include dambar - - 3.40 protrusion/intrusion. 0.10 0.91 3. Controlling dimension: Millimeter 0.25 2.60 2.85 3.10 4. General appearance spec. should be based on final visual 0.12 0.22 0.32 inspection spec. 0.05 0.15 0.25 13.75 14.00 14.25 19.75 20.25 20.00 0.25 0.5 0.75 16.90 17.20 17.50 22.90 23.50 23.20 0.68 0.88 1.08 1.35 1.60 1. 0.10 - 0° 12° 20 RTL8316 Rev.1.72 ...

Page 21

... CtrlFrameFilter. 2. modift the Pin assignment diagram 08/15/2001 1. English grammatical check and general polish. 11/09/2001 1. SD review and check 2. add an test pin "IpgCompTest" 3. update some test pin definition. 4. Change 6.16 H-O-L Blocking to H-O-L Blocking Prevention 12/12/2001 1. update mistakes of the Pin description 21 Description of Change RTL8316 Rev.1.72 ...

Page 22

... Realtek Semiconductor Corp. Headquarters 1F, No. 2, Industry East Road IX, Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Tel : 886-3-5780211 Fax : 886-3-5776047 WWW: www.realtek.com.tw 2001/11/09 22 RTL8316 Rev.1.72 ...

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