LPC47B377QFP Standard Microsystems, LPC47B377QFP Datasheet
LPC47B377QFP
Related parts for LPC47B377QFP
LPC47B377QFP Summary of contents
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Pin Enhanced Super I/O for LPC Bus with SMBus Controller for Commercial Applications 3.3 Volt Operation (5V Tolerant) Floppy Disk Controller (Supports 2 FDCs) Multi-Mode Parallel Port Two UARTs 8042 Keyboard Controller SMBus Controller Programmable Wakeup Event Interface (nIO_PME ...
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... Channel and Hardware IRQ of each logical device in the LPC47B37x may be reprogrammed through the internal configuration registers. There are 480 I/O address location options, a Serialized IRQ channels. Standard Microsystems is a registered trademark and SMSC is a trademark Corporation. Other product and company names are trademarks or registered trademarks of their respective holders ...
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FEATURES ....................................................................................................................................... 1 GENERAL DESCRIPTION ................................................................................................................ 2 PIN CONFIGURATION ...................................................................................................................... 5 DESCRIPTION OF PIN FUNCTIONS................................................................................................. 6 Buffer Type Descriptions............................................................................................................... 10 Pins That Require External Pullup Resistors.................................................................................. 11 3.3 VOLT OPERATION / 5 VOLT TOLERANCE .............................................................................. 12 POWER FUNCTIONALITY .............................................................................................................. 12 ...
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LED Functionality ........................................................................................................................140 WATCH DOG TIMER .....................................................................................................................141 SYSTEM MANAGEMENT INTERRUPT (SMI).................................................................................141 SMI Registers..............................................................................................................................142 ACPI Support Register for SMI Generation...................................................................................143 PME SUPPORT..............................................................................................................................143 WAKE ON SPECIFIC KEY OPTION ...............................................................................................145 FAN SPEED CONTROL AND MONITORING..................................................................................146 Fan Speed Control ......................................................................................................................146 Fan Tachometer Input .................................................................................................................147 ...
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GP40/DRVDEN0 1 GP41/DRVDEN1 2 nMTR0 3 nDSKCHG 4 nDS0 5 CLKI32 6 VSS 7 nDIR 8 nSTEP 9 nWDATA 10 nWGATE 11 nHDSEL 12 nINDEX 13 LPC47B37x nTRK0 14 nWRTPRT 15 nRDATA 16 100 PIN QFP GP42/nIO_PME 17 VTR 18 ...
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Note: There are no internal pullups on any of the pins in the LPC47B37x. PIN # NAME 1 GP40/DRVDEN0 2 GP41/DRVDEN1 3 nMTR0 5 nDS0 8 nDIR 9 nSTEP 10 nWDATA 11 nWGATE 12 nHDSEL 13 nINDEX 14 nTRK0 15 ...
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PIN # NAME 41 GP20 /P17 /nDS1 General Purpose I/O / P17 /Drive Select 1 42 GP21 /P16 /IRQ6 General Purpose I/O / P16 /IRQ6 43 GP22 /P12/ nMTR1 General Purpose I/O / P12 / Motor GP23 ...
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PIN # NAME 64 GP37 /A20M General Purpose I/O /Gate A20 (Note 8) 66 nINIT /nDIR Initiate Output/FDC Direction Control 67 nSLCTIN/nSTEP Printer Select Input/FDC Step Pulse 68 PD0 /nINDEX Port Data 0/FDC Index 69 PD1 /nTRK0 Port Data 1/FDC ...
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PIN # NAME 95 GP52 /RXD2/IRRX 96 GP53 /TXD2/IRTX 97 GP54 /nDSR2 98 GP55/nRTS2 99 GP56/nCTS2 100 GP57/nDTR2 53, 65, VCC 93 18 VTR 7, 31, VSS 60 CLKI32 19 CLOCKI Note: The "n" as the first letter ...
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Note 8: External pullups must be placed on the nKBDRST and A20M pins. These pins are General Purpose I/Os that are inputs after an initial power-up (VTR POR). If the nKBDRST and A20M functions are to be used, the system ...
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Pins That Require External Pullup Resistors The following pins require external pullup resistors: KDAT KCLK MDAT MCLK GP36/KBDRST if KBDRST function is used GP37/A20M if A20M function is used GP20/P17/nDS1 If P17 function is used GP21/P16/IRQ6 if P16 or IRQ6 ...
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VOLT OPERATION / TOLERANCE The LPC47B37x is a 3.3 Volt part intended solely for 3.3V applications. Non-LPC bus pins are 5V tolerant; that is, the input voltage is 5.5V max, and the I/O buffer output pads are ...
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Indication of 32kHz Clock There is a bit to indicate whether or not the 32kHz clock input is connected LPC47B37x. This bit is located at bit 0 of the CLOCKI32 register at 0xF0 in Logical Device A. This register is ...
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The other GPIOs function as follows: GP40, GP62: Buffers powered by VCC, but in the absence of VCC they are backdrive protected. These pins do not have input buffers into the wakeup logic that are powered by VTR. These pins ...
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The following list summarizes the blocks, registers and pins that are powered by VTR. PME interface block Runtime register block (includes all PME, SMI, GPIO and other miscellaneous registers) Wake on Specific Key logic LED control logic Pins for PME ...
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Super I/O Registers The address map, shown below in Table 1, shows the addresses of the different blocks of the Super I/O immediately after power up. addresses of the FDC, serial and parallel ports, PME register block, Game port and ...
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LPC Interface The following sub-sections specify the implementation of the LPC bus. LPC Interface Signal Definition The signals required for the LPC bus interface are described in the table below. LPC bus signals use PCI 33MHz electrical signal characteristics. SIGNAL ...
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Field Definitions The data transfers are based on specific fields that are used in various combinations, depending on the cycle type. These fields are driven onto the LAD[3:0] signal lines to communicate address, control and data information over the LPC ...
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Power Management CLOCKRUN Protocol The nCLKRUN pin is not implemented in the LPC47B37x. See the Low Pin Count (LPC) Interface Specification Reference, Section 8.1. LPCPD Protocol See the Low Pin Count (LPC) Interface Specification Reference, Section 8.2. SYNC Protocol See ...
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I/O and DMA START Fields I/O and DMA cycles use a START field of 0000. Reset Policy The following rules govern the reset policy: 1) When nPCI_RESET goes inactive (high), the clock is assumed to have been running for 100usec ...
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The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an IBM XT/AT compatible ...
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BIT 1 nWRITE PROTECT Active low status of the WRITE PROTECT disk interface input. A logic "0" indicates that the disk is write protected. BIT 2 nINDEX Active low status of the INDEX disk interface input. BIT 3 HEAD SELECT ...
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BIT 3 nHEAD SELECT Active low status of the HDSEL disk interface input. A logic "0" selects side 1 and a logic "1" selects side 0. BIT 4 TRACK 0 Active high status of the TRK0 disk interface input. BIT ...
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BIT 5 DRIVE SELECT 0 Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset and it is unaffected by a software reset. BIT 6 RESERVED ...
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Address 3F2 READ/WRITE The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the enable for the DMA logic and a software reset bit. The contents of the DOR are unaffected by a ...
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Tape Drive Register (TDR) Address 3F3 READ/WRITE The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during initialization. Any future references to that drive automatically invokes ...
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Normal Floppy Mode Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits are ‘0’. DB7 DB6 REG 3F3 0 0 Enhanced Floppy Mode 2 (OS2) Register 3F3 for Enhanced Floppy ...
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BIT 2 through 4 PRECOMPENSATION SELECT These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 7 shows the precompensation values for the combination of these bits settings. Track 0 is ...
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DRIVE RATE DATA RATE DRT1 DRT0 SEL1 ...
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Main Status Register Address 3F4 READ ONLY The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register can be read at any time. The MSR indicates when the disk controller ...
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The data is based upon the following formula: Threshold # 1 DELAY x DATA RATE At the start of a command, the FIFO action is always disabled and command parameters are sent based upon ...
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PC-AT Mode 7 6 DSK 0 CHG RESET N/A N/A COND. BIT UNDEFINED The data bus outputs are read as ‘0’. BIT 7 DSKCHG This bit monitors the pin of the same name and ...
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BITS DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 8 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, ...
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BIT 2 NO PRECOMPENSATION This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in Model 30 register mode. Unaffected by software reset. BIT ...
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Table 13 - Status Register 1 BIT NO. SYMBOL NAME 7 EN End of Cylinder Data Error 4 OR Overrun/ Underrun Data 1 NW Not Writeable 0 MA Missing Address Mark DESCRIPTION The ...
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BIT NO. SYMBOL Control Mark 5 DD Data Error in Data Field 4 WC Wrong Cylinder Bad Cylinder 0 MD Missing Data Address Mark BIT NO. SYMBOL Write Protected 5 ...
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Pin (Hardware Reset) The nPCI_RESET pin is a global reset and clears all registers except those programmed by the Specify command. The DOR reset bit is enabled and must be cleared by the host to exit the reset state. ...
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The FIFO is disabled during the command phase to provide for the proper handling of the "Invalid Command" condition. Execution Phase All data transfers to or from the FDC occur during the execution phase, which can proceed in DMA or ...
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The FDC generates a DMA request cycle when entering the execution phase of the data transfer commands. The DMA controller responds by placing data in the FIFO. The DMA request remains active until the FIFO becomes full. The DMA request ...
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Table 16 - Description of Command Symbols SYMBOL NAME C Cylinder Address D Data Pattern D0, D1 Drive Select 0-1 DIR Direction Control DS0, DS1 Disk Drive Select DTL Special Sector Size EC Enable Count EFIFO Enable FIFO EIS Enable ...
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Table 16 - Description of Command Symbols SYMBOL NAME MT Multi-Track When set, this flag selects the multi-track operating mode. In this Selector mode, the FDC treats a complete cylinder under head 0 and single track. The ...
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Table 16 - Description of Command Symbols SYMBOL NAME SK Skip Flag When set to 1, sectors containing a deleted data address mark will automatically be skipped during the execution of Read Data. If Read Deleted is executed, only sectors ...
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Instruction Set PHASE R Command W MT MFM Execution Result Table 17 ...
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PHASE R Command W MT MFM Execution Result READ DELETED DATA DATA BUS ...
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PHASE R Command W MT MFM Execution Result WRITE DATA DATA BUS ...
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PHASE R Command W MT MFM Execution Result WRITE DELETED DATA DATA BUS ...
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PHASE R Command W 0 MFM Execution Result READ A TRACK DATA BUS ...
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PHASE R Command W MT MFM Execution Result PHASE R Command Result VERIFY ...
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PHASE R Command W 0 MFM Execution for W Each Sector Repeat Result FORMAT A TRACK DATA BUS ...
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PHASE R Command Execution PHASE R Command Result R ST0 R PCN PHASE R Command SRT W HLT RECALIBRATE DATA BUS ...
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PHASE R Command Result R PHASE R Command Execution PHASE R Command EIS ...
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PHASE R Command W 1 DIR PHASE R/W D7 Command W 0 Execution Result SRT LOCK RELATIVE SEEK DATA BUS ...
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PHASE R Command W 0 MFM Execution Result READ ID DATA BUS HDS DS1 ST0 ...
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PHASE R/W D7 Command PHASE R Command W Invalid Codes Result R PHASE R/W D7 Command W LOCK Result returned if the last command that was issued was the Format command. ...
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Data Transfer Commands All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte. An implied ...
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If the host terminates a read or write operation in the FDC, the ID information in the result phase is dependent upon the state of the MT bit and EOT byte. Refer to Table 19. At the completion of the ...
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Read Deleted Data This command is the same as the Read Data command, only it operates on sectors that contain a Deleted Data Address Mark at the beginning of a Data Field. Table 21 describes the effect of the SK ...
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FINAL SECTOR MT HEAD TRANSFERRED TO HOST 0 0 Less than EOT Equal to EOT 1 Less than EOT Equal to EOT 1 0 Less than EOT Equal to EOT 1 Less than EOT Equal to EOT NC: No Change, ...
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Verify The Verify command is used to verify the data stored on a disk. This command acts exactly like a Read Data command except that no data is transferred to the host. Data is read from the disk and CRC ...
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Table 23 - Verify Command Result Phase DTL EOT # Sectors Per Side DTL EOT > # Sectors Per Side Sectors Remaining AND EOT # Sectors ...
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SYSTEM 34 (DOUBLE DENSITY) FORMAT GAP4a SYNC IAM GAP1 SYNC 80x 12x 50x 12x SYSTEM 3740 (SINGLE DENSITY) FORMAT GAP4a SYNC IAM GAP1 SYNC 40x 6x 26x ...
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Table 24 - Typical Values for Formatting FORMAT SECTOR SIZE 128 128 512 FM 1024 2048 5.25" 4096 Drives ... 256 256 512* MFM 1024 2048 4096 ... 128 3.5" FM 256 Drives 512 256 MFM 512** 1024 GPL1 = ...
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Control Commands Control commands differ from the other commands in that no data transfer takes place. Three commands generate an interrupt when complete: Read ID, Recalibrate, and Seek. The other control commands do not generate an interrupt. Read ID The ...
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The rate at which step pulses are issued is controlled by SRT (Stepping Rate Time) in the Specify command. After each step pulse is issued, NCN is compared against PCN, and when NCN = PCN the SE bit in Status ...
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The Seek, Relative Seek, and Recalibrate commands have no result phase. The Sense Interrupt Status command must be issued immediately after these commands to terminate them and to provide verification of the head position (PCN). The H (Head Address) bit ...
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Configure Default Values: EIS - No Implied Seeks EFIFO - FIFO Disabled POLL - Polling Enabled FIFOTHR - FIFO Threshold Set to 1 Byte PRETRK - Pre-Compensation Set to Track 0 EIS - Enable Implied Seek. When set to "1", ...
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The Relative Seek command differs from the Seek command in that it steps the head the absolute number of tracks specified in the command instead of making a comparison against an internal register. The Seek command is good for drives ...
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Selection of the 500 Kbps and 1 Mbps perpendicular modes is independent of the actual data rate selected in the Data Rate Select Register. The user must ensure that these two data rates remain consistent. The Gap2 and VCO timing ...
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Software and hardware resets have the following effect on the PERPENDICULAR MODE COMMAND: 1. "Software" resets (via the DOR or DSR registers) will only clear GAP and WGATE bits to "0". D0-D3 are unaffected and retain their previous value. 2. ...
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Compatibility The LPC47B37x was designed with software compatibility in mind fully backwards- compatible solution with the older generation 765A/B disk controllers. The FDC also implements on-board registers for compatibility with the PS/2, as well as PC/AT and ...
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The LPC47B37x incorporates two full function UARTs. They are compatible with the NS16450, the 16450 ACE registers and the NS16C550A. characters and parallel-to-serial conversion on transmit characters. The data rates are independently programmable from 460.8K baud down to 50 baud. ...
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Transmit Buffer Register (TB) Address Offset = 0H, DLAB = 0, WRITE ONLY This register contains the data byte to be transmitted. The transmit buffer is double buffered, utilizing an additional shift register (not accessible) to convert the 8 bit ...
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Bit 1 Setting this bit to a logic "1" clears all bytes in the RCVR FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self-clearing. Bit 2 Setting this bit to a ...
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Bit 0 This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending. When bit logic "0", an interrupt is pending and the contents of the IIR may ...
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FIFO INTERRUPT MODE IDENTIFICATION ONLY REGISTER BIT 3 BIT 2 BIT 1 BIT Line Control Register (LCR) Address Offset = 3H, DLAB = 0, READ/WRITE Start LSB Data 5-8 bits MSB This register contains the ...
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Bit 2 This bit specifies the number of stop bits in each transmitted or received serial character. The following table summarizes the information. BIT 2 Note: The receiver will ignore all stop bits beyond the first, regardless of the number ...
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This 8 bit register controls the interface with the MODEM or data set (or device emulating a MODEM). The contents of the MODEM control register are described below. Bit 0 This bit controls the Data Terminal Ready (nDTR) output. When ...
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Bit 0 Data Ready (DR set to a logic "1" whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the FIFO. Bit 0 is reset to a logic "0" by reading ...
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Bit 6 Transmitter Empty (TEMT). Bit 6 is set to a logic "1" whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty reset to logic "0" whenever either the THR or TSR contains ...
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Bit 4 This bit is the complement of the Clear To Send (nCTS) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to nRTS in the MCR. Bit 5 This bit is the ...
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C. The receiver line status interrupt (IIR=06H), has higher priority than the received data available (IIR=04H) interrupt. D. The data ready bit (LSR bit 0) is set as soon as a character is transferred from the shift register to the ...
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There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode, however, the RCVR and XMIT FIFOs are still fully capable of holding characters. DESIRED DIVISOR USED TO BAUD RATE GENERATE 16X CLOCK 50 2304 75 ...
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REGISTER/SIGNAL Interrupt Enable Register RESET Interrupt Identification Reg. RESET FIFO Control RESET Line Control Reg. RESET MODEM Control Reg. RESET Line Status Reg. RESET MODEM Status Reg. RESET TXD1, TXD2 RESET INTRPT (RCVR errs) RESET/Read LSR INTRPT (RCVR Data Ready) ...
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Table 32 - Register Summary for an Individual UART Channel REGISTER ADDRESS* REGISTER NAME ADDR = 0 Receive Buffer DLAB = 0 Register (Read Only) ADDR = 0 Transmitter Holding DLAB = 0 Register (Write Only) ADDR = 1 Interrupt ...
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Table 32 - Register Summary for an Individual UART Channel (continued) BIT 2 BIT 3 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 2 Data Bit 3 Data Bit 4 Enable Enable 0 Receiver Line MODEM Status ...
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Notes On Serial Port Operation TXD2 Pin The inactive state of the TXD2 pin can be selected through the TXD2_MODE bit, bit 7 of the Serial Port 2 Mode configuration register (at 0xF0 in LD5). FIFO Mode Operation GENERAL The ...
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The infrared interface provides a two-way wireless communications port using infrared as a transmission medium. Several IR implementations have been provided for the second UART in this chip (logical device 5), IrDA, and Amplitude Shift Keyed IR. The IR transmission ...
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IR Transmit Pin The following description pertains to the TXD2/IRTX pin of the LPC47B37x. The LPC47B37x implements a configuration bit to control state of the TXD2/IRTX pin. The TXD2_MODE bit, bit 7 of the Serial Port 2 Mode configuration register ...
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The LPC47B37x incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the Configuration Registers for information ...
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The bit map of these registers is DATA PORT PD0 PD1 STATUS TMOUT 0 PORT CONTROL STROBE AUTOFD PORT EPP ADDR PD0 PD1 PORT EPP DATA PD0 PD1 PORT 0 EPP DATA PD0 PD1 PORT 1 EPP DATA ...
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Data Port ADDRESS OFFSET = 00H The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the Data Register latches the contents of ...
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BIT PAPER END The level on the PE input is read by the CPU as bit 5 of the Printer Status Register. A logic 1 indicates a paper end; a logic 0 indicates the presence of paper. ...
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EPP Address Port ADDRESS OFFSET = 03H The EPP Address Port is located at an offset of '03H' from the base address. The address register is cleared at initialization by RESET. During a WRITE operation, the contents of the internal ...
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In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of the EPP ...
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EPP 1.9 Read The timing for a read operation (data) is shown in timing diagram EPP Read Data cycle. The chip inserts wait states into the LPC I/O read cycle until it has been determined that the read cycle can ...
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Write Sequence of Operation 1. The host sets PDIR bit in the control register to a logic "0". This asserts nWRITE. 2. The host initiates an I/O write cycle to the selected EPP register. 3. The chip places address or ...
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EPP 1.7 Read The timing for a read operation (data) is shown in timing diagram EPP 1.7 Read Data cycle. The chip inserts wait states into the I/O read cycle when nWAIT is active low during the EPP cycle. This ...
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Extended Capabilities Parallel Port ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater detail in the remainder of this section. High performance half-duplex forward and reverse channel Interlocked handshake, for ...
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Note 2: All FIFOs use one common 16 byte FIFO. Note 3: The ECP Parallel Port Config Reg B reflects the IRQ and DMA channel selected by the Configuration Registers. ECP Implementation Standard This specification describes the standard interface to ...
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NAME TYPE nStrobe O During write operations nStrobe registers data or address into the slave on the asserting edge (handshakes with Busy). PData 7:0 I/O Contains address or data or RLE data. nAck I Indicates valid data driven by the ...
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Table 36 - ECP Register Definitions NAME ADDRESS (Note 1) data +000h R/W ecpAFifo +000h R/W dsr +001h R/W dcr +002h R/W cFifo +400h R/W ecpDFifo +400h R/W tFifo +400h R/W cnfgA +400h R cnfgB +401h R/W ecr +402h R/W ...
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Device Status Register (DSR) ADDRESS OFFSET = 01H The Status Port is located at an offset of '01H' from the base address. Bits are not implemented as register bits, during a read of the Printer Status Register ...
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BIT 5 DIRECTION If mode=000 or mode=010, this bit has no effect and the direction is always out regardless of the state of this bit. In all other modes, Direction is valid and a logic 0 means that the printer ...
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The readIntrThreshold can be determined by setting the direction bit to 1 and filling the empty tFIFO a byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has been ...
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BIT 2 serviceIntr Read/Write 1: Disables DMA and all of the service interrupts. 0: Enables one of the following 3 cases of interrupts. Once one of the 3 service interrupts has occurred serviceIntr bit shall be set ...
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Table 38A - Extended Control Register R/W 000: Standard Parallel Port Mode . In this mode the FIFO is reset and common collector drivers are used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will ...
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Operation Mode Switching/Software Control Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ...
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Termination from ECP Mode Termination from ECP Mode is similar to the termination from Nibble/Byte Modes. The host is permitted to terminate from ECP Mode only in specific well-defined states. The termination can only be executed while the bus is ...
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LPC Connections The interface can never stall causing the host to hang. The width of data transfers is strictly controlled on an I/O address basis per this specification. All FIFO-DMA transfers are byte wide, byte aligned and end on a ...
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DMA Transfers DMA transfers are always to or from the ecpDFifo, tFifo or CFifo. DMA utilizes the standard PC DMA services. To use the DMA transfers, the host first sets up the direction and state as in the programmed I/O ...
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Programmed I/O - Transfers from the FIFO to the Host In the reverse direction an interrupt occurs when serviceIntr is 0 and readIntrThreshold bytes are available in the FIFO this time the FIFO is full it can be ...
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For ACPI compliance the FDD pins that are multiplexed onto the Parallel Port function independently of the state of the Parallel Port controller. For example, if the FDC is enabled onto the Parallel Port the multiplexed FDD interface functions normally ...
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FDC on Parallel Port Pin The “floppy on the parallel port” pin function, FDC_PP, is muxed onto GP43. This pin function can be used to switch the parallel port pins between the FDC and the parallel port. The FDC_PP pin ...
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Power management capabilities are provided for the following logical devices: floppy disk, UART 1, UART 2 and the parallel port. For each logical device, two types of power management are provided: direct powerdown and auto powerdown. FDC Power Management Direct ...
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Register Behavior Table 40 illustrates the AT and PS/2 (including Model 30) configuration registers available and the type of access permitted. In order to maintain software transparency, access to all the registers must be maintained. As Table 40 shows, two ...
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System Interface Pins Table 43 gives the state of the interface pins in the powerdown state. Pins unaffected by the powerdown are labeled "Unchanged". Table 43 – State of System Pins in Auto Powerdown SYSTEM PINS LAD[3:0] nLDRQ nLPCPD nLFRAME ...
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Note: While in powerdown the Ring Indicator interrupt is still valid and transitions when the RI input changes. Exit Auto Powerdown The transmitter exits powerdown on a write to the XMIT buffer. The receiver exits auto powerdown when RXDx changes ...
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The LPC47B37x supports the serial interrupt to transmit interrupt information to the host system. The serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0. Timing Diagrams for SER_IRQ Cycle A) Start Frame timing with source ...
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SER_IRQ Cycle Control There are two modes of operation for the SER_IRQ Start Frame. 1) Quiet (Active) Mode: Any device may initiate a Start Frame by driving the SER_IRQ low for one clock, while the SER_IRQ is Idle. After driving ...
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SER_IRQ PERIOD The SER_IRQ data frame supports IRQ2 from a logical device on Period 3, which can also be used for SMI via the ...
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EOI/ISR Read Latency Any serialized IRQ scheme has a potential implementation issue related to IRQ latency. IRQ latency could cause an EOI or ISR Read to precede an IRQ transition that it should have followed. This could cause a system ...
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ISA IRQ To Serial IRQ Conversion Capability these pins via the GPIO registers, then the associated IRQ input will appear in the serial IRQ stream if the IRQ is not used by an internal device. The ISA IRQs that are ...
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The LPC47B37x is a Super I/O and Universal Keyboard Controller that is designed for intelligent keyboard management in desktop computer applications. The Universal Keyboard Controller uses an 8042 microcontroller CPU core. This section concentrates on the LPC47B37x enhancements to the ...
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ADDRESS Write Read 0x64 Write Read Note 1: These registers consist of three separate 8 bit registers. Status, Data/Command Write and Data Read. Keyboard Data Write This bit write only register. When written, the C/D status bit ...
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If "EN FLAGS” has not been executed: KIRQ can be controlled by writing to P24. Writing a zero to P24 forces KIRQ low; a high forces KIRQ high. If "EN FLAGS" has been executed and P25 is set to a ...
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Soft Power Down Mode This mode is entered by executing a HALT instruction. The execution of program code is halted until either RESET is driven active or a data byte is written to the DBBIN register by a master CPU. ...
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OBF register (DBB). When the host system reads the output data register, this bit is automatically reset. The LPC47B37x Keyboard Controller clock source MHz clock generated from a 14.318 MHz clock. The reset pulse must last for ...
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BIT Reserved. Returns 00 when read 5 4 Reserved. Returns a 0 when read 3 Reserved. Returns a 0 when read 2 Reserved. Returns a 1 when read 1 ALT_A20 Signal control. Writing this bit causes the ...
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P20 P92 Bit 0 Pulse Gen Note: When Port 92 is disabled, writes are ignored and reads return undefined values. Bit 1 of Port 92, the ALT_A20 signal, is used to force nA20M to the CPU low for support ...
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Latches On Keyboard and Mouse IRQs The implementation of the latches on the keyboard and mouse interrupts is shown below. KLATCH Bit KINT 8042 FIGURE 3 - KEYBOARD LATCH VCC D Q CLR RD 60 130 KINT new ...
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MLATCH Bit MINT 8042 The KLATCH and MLATCH bits are located in the KRST_GA20 register, in Logical Device 7 at 0xF0. These bits are defined as follows: Bit[4]: MLATCH – Mouse Interrupt latch control bit. 0=MINT is the 8042 MINT ...
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Keyboard and Mouse PME Generation The LPC47B37x sets the associated PME Status bits when the following conditions occur: Keyboard Interrupt Mouse Interrupt These events can cause a PME to be generated if the associated PME Wake Enable register bit and ...
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GENERAL PURPOSE I/O The LPC47B37x provides a set of flexible Input/Output control functions to the system designer through the 39 dedicated independently programmable General Purpose I/O pins (GPIO). The GPIO pins can perform basic I/O and many of them can ...
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Description Each GPIO port has a 1-bit data register and an 8-bit configuration control register. The data register for each GPIO port is represented as a bit in one of the 8-bit GPIO DATA Registers, GP1 to GP8. The bits ...
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PIN NO. DEFAULT ALT. /QFP FUNCTION FUNC GPIO Device Disable Reg. Control N/A Reserved N/A Reserved N/A Reserved N/A Reserved 92 GPIO Ring Indicator 2 94 GPIO Data Carrier Detect 2 95 GPIO Receive Serial Data 2 96 ...
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GPIO Control Each GPIO port has an 8-bit control register that controls the behavior of the pin. These registers are defined in the “Runtime Registers” section of this specification. Each GPIO port may be configured as either an input or ...
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GPIO Operation The operation of the GPIO ports is illustrated in Figure 5. Note: Figure 5 is for illustration purposes only and in not intended to suggest specific implementation details. D-TYPE SD-bit D Q GPx_nIOW Transparent Q D GPx_nIOR GPIO ...
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TABLE 52 - GPIO Read/Write Behavior HOST OPERATION READ WRITE The LPC47B37x provides 36 GPIOs that can directly generate a PME. See the table in the next section. The polarity bit in the GPIO control registers select the edge on ...
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The following GPIOs have “either edge triggered interrupt” (EETI) input capability. These GPIOs can generate a PME and an SMI on both a high-to-low and a low-to-high edge on the GPIO pin. These GPIOs have a status bit in the ...
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Either Edge Triggered Interrupts Six GPIO pins are implemented such that they allow an interrupt (PME or SMI generated on both a high-to-low and a low-to-high edge transition, instead of one or the other as selected by the ...
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The LPC47B37x contains a Watch Dog Timer (WDT). The Watch Dog Time-out status bit may be mapped to an interrupt through the WDT_CFG Register (Runtime register at offset 54h). The LPC47B37x's WDT has a programmable time-out ranging from 1 to ...
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An example logic equation for the nSMI output for SMI registers 1 and follows: nSMI = (EN_PINT and IRQ_PINT) or (EN_U2INT and IRQ_U2INT) or (EN_U1INT and IRQ_U1INT) or (EN_FINT and IRQ_FINT) or (EN_WDT and IRQ_WDT) or (EN_MINT ...
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ACPI Support Register for SMI Generation The ACPI PM1 Control register is implemented in the LPC47B37x to allow the generation of an SMI when the SLP_EN bit (PM1_CNTRL2 bit 5) is written to ‘1’. The SLP_TYPx field (bits[4:2]) is also ...
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For the GPIO events, the polarity of the edge used to set the status bit and generate a PME is controlled by the polarity bit of the GPIO control register. For non-inverted polarity (default) the status bit is set on ...
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The LPC47B37x has logic to detect a single keyboard scan code for wakeup (PME generation). The scan code is programmed onto the Keyboard Scan Code Register, a runtime register at offset 0x5F from the base address located in the primary ...
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The LPC47B37x implements fan speed control outputs and fan tachometer inputs. The implementation of these features are described in the sections below. Fan Speed Control The fan speed control for the LPC47B37x is implemented as pulse width modulators with fan ...
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Fan Register The Fan Register is located at 0x56 from base I/O in Logical Device A. See register description in the Runtime Registers section. Fan Clock Select, D7 The Fan Clock Select bit in the Fan registers is used with ...
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The clock source for the tachometer count is the 32.768kHz oscillator. The Fan Tachometer Input gate a divided down version of the 32.768kHz oscillator for one period of the Fan signal into an 8-bit counter (maximum count is 255). The ...
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Term 1 in the equation above is determined by multiplying the clock source of 32.768kHz by 60sec/min and dividing by the product of the revolutions per minute times the divisor. The default divisor, located in the Fan Control Register, is ...
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The following tables show examples of the desired functionality. Counts are based on 2 pulses per revolution tachometer outputs with a default divisor of 2. Time per Term 1 for “Divide by 2” RPM Revolution (Default) in Decimal 4400 13.64 ...
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The following register describes the functionality to support security in the LPC47B37x. GPIO Device Disable Register Control The GPIO pin GP43 is used for the Device Disable Register Control (DDRC) function. Setting bits[3:2] of the GP43 configuration register to ‘01’, ...
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Configuration Registers See the configuration registers section for the SMBus Configuration Registers (Logical Device 0x0B). Runtime Registers Overview The SMBus contains five registers: 1) Control, 2) Status, 3) Own Address, 4) Data, 5) Clock. The five SMBus registers occupy four ...
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Control Register Overview The Control/Status register manages the SMBus operation and provides operational status (Table 55). The Control/Status register is located at the SMBus Base Address. The Control register is write-only and is located at the SMBus Base Address. The ...
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Bit 3 ENI This bit enables the internal SMBus interrupt, nINT, which is generated when the PIN bit is asserted (‘0’). Bit 2 and Bit 1 STA and STO These bits control the generation of the SMBus Start condition and ...
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After transmission or reception of one byte on the SMBus (nine clock pulses, including acknowledge) the PIN bit will be automatically reset to logic “0” (active) indicating a complete byte transmission/reception. When the PIN bit is subsequently set to logic ...
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PIN Bit Summary 1. The PIN bit can be used in polled applications to test when a serial transmission has been completed. When the ENI bit is also set, the PIN flag sets the internal interrupt via the nINT output. ...
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Bit 1 LAB Lost Arbitration Bit. This bit is set when, in multi-master operation, arbitration is lost to another master on the SMBus. Bit 0 nBB Bus Busy bit. This is a read-only flag indicating when the SMBus is in ...
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Table 58 - SMBus Data Register (SMBus Base Address +2) Default DATA 0x00 on VTR POR, R/W VCC POR, Hard Reset or Soft Reset Clock Register Overview The Clock Register controls the internal SMBus clock generator, the SMBus reset, and ...
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The SMBus output clock SCLK frequency is determined by the CLK_SEL and CLK_DIV bits (Table 60). Table 60 – SMBus Clock Select Encoding SMBUS CLOCK FREQUENCY CONTROLS CLK_SEL CLK_DIV Pin Multiplexing SDAT is multiplexed with pin GP32. ...
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SMB Clk SMB Data Start 0 1 FIGURE 6 - SAMPLE SMBUS SINGLE BYTE TRANSACTION RUNTIME REGISTERS Runtime Registers Block Summary The following registers are runtime registers in the LPC47B37x. They are located at the address programmed in the Base ...
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OFFSET HARD (hex) TYPE RESET R/W 0x03 R/W ...
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OFFSET HARD (hex) TYPE RESET 41 R R/W 0x00 R/W ...
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OFFSET HARD (hex) TYPE RESET 6C R/W - 6D- Note. Reserved bits return 0 on read. Note 1: This register contains some bits that are read or write only. Note 2: Bit 0 is not cleared by HARD ...
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Runtime Registers Block Description Table 62 - Runtime Registers Block Description Note: Reserved bits return 0 on read. REG OFFSET NAME (hex) PME_STS 00 Default = 0x00 (R/W) on VTR POR PME_EN 02 Default = 0x00 (R/W) on VTR POR ...
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REG OFFSET NAME (hex) PME_STS2 05 Default = 0x00 (R/W) on VTR POR PME_STS3 06 Default = 0x00 (R/W) on VTR POR DESCRIPTION PME Wake Status Register 2 This register indicates the state of the individual PME wake sources, independent ...
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REG OFFSET NAME (hex) PME_STS4 07 Default = 0x00 (R/W) on VTR POR PME_STS5 08 Default = 0x00 (R/W) on VTR POR DESCRIPTION PME Wake Status Register 4 This register indicates the state of the individual PME wake sources, independent ...
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REG OFFSET NAME (hex) PME_STS6 09 Default = 0x01 on (R/W) VTR POR Bit 0 is set to ‘1’ on VCC POR, VTR POR, HARD RESET and SOFT RESET PME_EN1 0A Default = 0x00 on (R/W) VTR POR DESCRIPTION This ...
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REG OFFSET NAME (hex) PME_EN2 0B Default = 0x00 on (R/W) VTR POR PME_EN3 0C Default = 0x00 on (R/W) VTR POR DESCRIPTION PME Wake Enable Register 2 This register is used to enable individual PME wake sources onto the ...
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REG OFFSET NAME (hex) PME_EN4 0D Default = 0x00 on (R/W) VTR POR PME_EN5 0E Default = 0x00 on (R/W) VTR POR DESCRIPTION PME Wake Enable Register 4 This register is used to enable individual PME wake sources onto the ...
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REG OFFSET NAME (hex) PME_EN6 0F Default = 0x00 on (R/W) VTR POR SMI_STS1 10 Default = 0x02 (R/W) on VTR POR Bit 1 is set to ‘1’ on VCC POR, VTR POR, hard reset and soft reset SMI_STS2 11 ...
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REG OFFSET NAME (hex) SMI_STS3 12 Default = 0x00 (R/W) on VTR POR SMI_STS4 13 Default = 0x00 (R/W) on VTR POR SMI_STS5 14 Default = 0x00 (R/W) on VTR POR DESCRIPTION SMI Status Register 3 This register is used ...
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REG OFFSET NAME (hex) SMI_STS6 15 Default = 0x00 (R/W) on VTR POR SMI_EN1 16 Default = 0x00 (R/W) on VTR POR SMI_EN2 17 Default = 0x00 (R/W) on VTR POR DESCRIPTION SMI Status Register 6 This register is used ...
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REG OFFSET NAME (hex) SMI_EN3 18 Default = 0x00 (R/W) on VTR POR SMI_EN4 19 Default = 0x00 (R/W) on VTR POR SMI_EN5 1A Default = 0x00 (R/W) on VTR POR DESCRIPTION SMI Enable Register 3 This register is used ...
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REG OFFSET NAME (hex) SMI_EN6 1B Default = 0x00 (R/W) on VTR POR MSC_STS 1C Default = 0x00 on (R/W) VTR POR UART2 FIFO Control 1D Shadow (R) DESCRIPTION SMI Enable Register 6 This register enables the individual SMI sources ...
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REG OFFSET NAME (hex) Force Disk Change 1E Default = 0x03 on (R/W) VCC POR and hard reset Floppy Data Rate 1F Select Shadow (R) UART1 FIFO Control 20 Shadow (R) DESCRIPTION Force Change 1 and Force Change 0 can ...
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REG OFFSET NAME (hex) Edge Select Register 21 Default = 0x00 (R/W) on VTR POR DESCRIPTION Bit[0] EDGE_P12_SMI 0= P12 SMI status bit is set on the high-to-low edge of P1.2 1= P12 SMI status bit is set on both ...
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REG OFFSET NAME (hex) Device Disable 22 Register Read/Write when Default = 0x00 GP43 register VTR POR bits[3: AND GP43 pin = 0 OR GP43 register bits[3:2] READ-ONLY When GP43 register bits[3:2] =01 AND GP43 pin = 1 ...
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REG OFFSET NAME (hex) GP10 23 Default = 0x01 (R/W) on VTR POR GP11 24 Default = 0x01 on VTR POR (R/W) GP12 25 Default = 0x01 (R/W) on VTR POR GP13 26 Default = 0x01 (R/W) on VTR POR ...
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REG OFFSET NAME (hex) GP14 27 Default = 0x01 (R/W) on VTR POR GP15 28 Default = 0x01 (R/W) on VTR POR GP16 29 Default = 0x01 (R/W) on VTR POR GP17 2A Default = 0x01 (R/W) on VTR POR ...
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REG OFFSET NAME (hex) GP20 2B Default = 0x01 (R/W) on VTR POR GP21 2C Default =0x01 (R/W) on VTR POR GP22 2D Default =0x01 (R/W) on VTR POR GP23 2E Default=0x01 (R/W) on VTR POR DESCRIPTION General Purpose I/0 ...
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REG OFFSET NAME (hex) GP24 2F Default = 0x01 (R/W) on VTR POR GP25 30 Default = 0x01 (R/W) on VTR POR GP26 31 Default = 0x01 (R/W) on VTR POR GP27 32 Default = 0x01 (R/W) on VTR POR ...
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REG OFFSET NAME (hex) GP31 34 Default = 0x01 (R/W) on VTR POR GP32 35 Default = 0x01 (R/W) on VTR POR GP33 36 Default = 0x01 (R/W) on VTR POR Default = 0x00 on VCC POR and Hard Reset ...
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REG OFFSET NAME (hex) GP35 38 Default = 0x01 (R/W) on VTR POR GP36 39 Default = 0x01 (R/W) on VTR POR GP37 3A Default = 0x01 (R/W) on VTR POR GP40 3B Default =0x01 (R/W) on VTR POR DESCRIPTION ...
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REG OFFSET NAME (hex) GP41 3C Default =0x01 (R/W) on VTR POR GP42 3D Default =0x01 (R/W) on VTR POR DESCRIPTION General Purpose I/0 bit 4.1 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert ...
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REG OFFSET NAME (hex) GP43 3E Default = 0x01 (R/W) on VTR POR Bits[3:2] are reset (cleared) on VCC POR, VTR POR and Hard Reset GP50 3F Default = 0x01 (R/W) on VTR POR DESCRIPTION General Purpose I/0 bit 4.3 ...
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REG OFFSET NAME (hex) GP51 40 Default = 0x01 (R/W) on VTR POR GP52 41 Default = 0x01 (R/W) on VTR POR GP53 42 Default = 0x00 (R/W) on VTR POR, VCC POR and HARD RESET (Note 2) GP54 43 ...
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REG OFFSET NAME (hex) GP55 44 Default = 0x01 (R/W) on VTR POR GP56 45 Default = 0x01 (R/W) on VTR POR GP57 46 Default = 0x01 (R/W) on VTR POR GP60 47 Default = 0x01 (R/W) on VTR POR ...
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REG OFFSET NAME (hex) GP61 48 Default = 0x01 (R/W) on VTR POR GP62 49 Default = 0x01 (R/W) on VTR POR GP1 4B Default = 0x00 (R/W) on VTR POR GP2 4C Default = 0x00 (R/W) on VTR POR ...
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REG OFFSET NAME (hex) GP3 4D Default = 0x00 (R/W) on VTR POR Bits 3 is reset on VCC POR, Hard Reset and VTR POR GP4 4E Default = 0x00 (R/W) on VTR POR GP5 4F Default = 0x00 (R/W) ...
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REG OFFSET NAME (hex) WDT_CFG 54 Default = 0x00 (R/W) on VCC POR, VTR POR, VTR POR and Hard Reset WDT_CTRL 55 Default = 0x00 (R/W) on VCC POR, VTR POR, VTR POR and Hard Reset DESCRIPTION Watch-dog timer Configuration ...
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REG OFFSET NAME (hex) FAN 56 Default = 0x00 (R/W) on VTR POR Fan Control 58 Default = 0x10 (R/W) on VTR POR DESCRIPTION FAN Register Bit[0] Fan Control 1=FAN pin is high 0=bits[6:1] control the duty cycle of the ...
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REG OFFSET NAME (hex) Fan Tachometer 59 Register (R) Default = 0x00 on VTR POR Fan Preload Register 5B Default = 0x00 (R/W) on VTR POR LED1 5D Default = 0x00 (R/W) on VTR POR LED2 5E Default = 0x00 ...
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REG OFFSET NAME (hex) PM1_CNTRL2 61 Default = 0x00 R/W – Bits[4:2] on VTR POR Read Only – Bits[7,6,1,0] Write Only – Bit[5] SMI_STS7 64 Default = 0x00 (R/W) on VTR POR SMI_EN7 66 Default = 0x00 (R/W) on VTR ...
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REG OFFSET NAME (hex) PME_STS7 68 Default = 0x00 on (R/W) VTR POR PME_EN7 6C Default = 0x00 on (R/W) VTR POR User Note: When selecting an alternate function for a GPIO pin, all bits in the GPIO register must ...
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GPIO Control Register. Bit 7 of the FDD Mode Register will also affect the pin if the FDC function is selected. Note 4: The nIO_SMI pin is inactive when the internal group SMI signal is inactive and when the ...
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The Configuration of the LPC47B37x is very flexible and is based on the configuration architecture implemented in typical Plug-and-Play components. The LPC47B37x is designed for motherboard applications in which the resources required by their components are known. With its flexible ...
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Exiting the Configuration State The device exits the Configuration State when the following Config Key is successfully written to the CONFIG PORT. CONFIGURATION SEQUENCE To program the configuration registers, the following sequence must be followed: 1. Enter Configuration Mode 2. ...
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Programming Example The following is an example of a configuration program in Intel 8086 assembly language. ;----------------------------. ; ENTER CONFIGURATION MODE ;----------------------------' MOV DX,02EH MOV AX,055H OUT DX,AL ;----------------------------. ; CONFIGURE REGISTER CRE0, ; LOGICAL DEVICE 8 ;----------------------------' MOV DX,02EH ...
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Notes: HARD RESET: nPCI_RESET pin asserted SOFT RESET: Bit 0 of Configuration Control register set to one All host accesses are blocked for 500µs after VCC POR (see Power-up Timing Diagram) Table 63 – LPC47B37x Configuration Registers Summary INDEX TYPE ...
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INDEX TYPE HARD RESET VCC POR 0xF5 R/W 0x00 LOGICAL DEVICE 1 CONFIGURATION REGISTERS (Reserved) LOGICAL DEVICE 2 CONFIGURATION REGISTERS (Reserved) LOGICAL DEVICE 3 CONFIGURATION REGISTERS (Parallel Port) 0x30 R/W 0x00 0x60, R/W 0x00, 0x61 0x00 0x70 R/W 0x00 0x74 ...