VSC7302VF Vitesse Semiconductor Corp., VSC7302VF Datasheet

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Heathrow-III™ – 16-Port Gigabit Ethernet Switch-on-a-Chip F EATURES 16 Gigabit Ethernet ports with nonblocking wire- speed performance Tri-speed (10/100/1000 Mb/s) operation via RGMII or RTBI interface Support for both wire-speed automatic learning, and CPU-based learning 272 kB on-chip frame buffer ...

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VSC7302 Data Sheet Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Advance Product Information Subject to Change Contents Direct MAC Table Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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VSC7302 Data Sheet Contents Categorizer Block Registers (Block 1/ ...

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Advance Product Information Subject to Change Contents 2.5 V Output Supply (VDD_OUT25 ...

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VSC7302 Data Sheet Figures 1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Advance Product Information Subject to Change Tables 1. Flow Control Data Receivable After Pause Frame . . . . . . . . . . . . . . . . . . . . . . . . . ...

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VSC7302 Data Sheet Tables 40. Time Compare Value - TIMECMP (Address 24h) Block 7 Subblock ...

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Advance Product Information Subject to Change Tables 65. Categorizer Map Tag - CATTAG (Address 64h) Block 1/6 Subblock 4-15/0 ...

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VSC7302 Data Sheet Tables 90. Rx Fragments - C_RXFRAG (Address A7h) Block 1/6 Subblock 4-15/0 ...

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Advance Product Information Subject to Change Tables 115. MII-M Command - MIIMCMD (Address 01h) Block 3 Subblock 0 ...

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VSC7302 Data Sheet Tables 140. Aggregation Masks - AGGRMSKS (Address 30h - 3Fh) Block 2 Subblock ...

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Advance Product Information Subject to Change Tables 176. PI Interface AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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VSC7302 Data Sheet F O UNCTIONAL VERVIEW Heathrow-III can operate as either a VLAN aware switch or a VLAN unaware switch. It forwards frames at Layer 2 based on information up to and including Layer 4. Policer Shaper ...one for ...

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Advance Product Information Subject to Change Register Access The control block receives commands via the CPU interfaces from an off-chip controller/processor and interprets these commands. The commands can be divided into four categories: MII Management reads and writes for PHY ...

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VSC7302 Data Sheet Quality Of Service Heathrow-III has two priority queues on each port, and the enhanced classifier/categorizer can assign priorities based on information taken from Layer 2 to Layer 4. The Categorizer analyzes all received frames. It can determine ...

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Advance Product Information Subject to Change MAC Address Learning When a packet is received, the source MAC address is looked up in the destination address table (see the ”Packet Forwarding” on page 16 not presently registered and ...

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VSC7302 Data Sheet General Purpose I/Os Heathrow-III features four general purpose I/Os (GPIO). These pins are freely configurable as either inputs or outputs and are accessed via either CPU interface UNCTIONAL ESCRIPTION In this section, the different aspects ...

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Advance Product Information Subject to Change PHY Rx Data MAC Categorizer Policer Input Queues (Shared FIFO) Frame +Header The PHY Rx Data is received by the MAC, which sends the realigned data further through the Categorizer and the Policer to ...

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VSC7302 Data Sheet MAC Features Each of the 16 ports of Heathrow-III are equipped with a MAC, which can operate in various modes. The modes are mainly set up in the MACCONF register, where selections of speed, duplex mode, and ...

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Advance Product Information Subject to Change Each port in Heathrow-III has two registers for configuring congestion control. In the POOLCFG register, the flow control mechanism is programmed, and in the DROPCFG register the conditions for dropping frames are set. Each ...

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VSC7302 Data Sheet Flow Control Mode When running a port in flow control mode, no packet drop is allowed on the port, and memory depletion must be handled by flow controlling the source of additional data. In this mode, the ...

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Advance Product Information Subject to Change Flow Control Thresholds Thresholds must be set with care to avoid packet loss in all cases (provided that no pause frames are lost). The amount of data that can possibly be received from the ...

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VSC7302 Data Sheet Frame Categorization Each port has a Frame Categorizer, whose main purpose is to determine the priority of ingress frames. This priority can be either high or low, and is based on information in Layer 2–4 within the ...

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Advance Product Information Subject to Change SOF n Tag only? Tagged CFI FS2 Tagged FS1 Map Tag Prio b7 CATTAG CATPRIO FS8 1 1 ...

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VSC7302 Data Sheet Table 4. Frame Classes Frame Type Reserved Addresses DMAC = 0180C200000x (IEEE802.1D 7.12.6) (STP, BPDU) IP/ARP MAC broadcast DMAC = BC, Type = IP/ARP IGMP DMAC = 01005Exxxxxx, Type = IP, IP type IGMP IP Multicast Data ...

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Advance Product Information Subject to Change If the bucket level reaches the Policer threshold, flow control frames are generated. Packets are not discarded. Over time, the bucket level will drop below the threshold. At this time, the flow control condition ...

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VSC7302 Data Sheet Table 5. Basic Frame Analysis Data (cont’d) Table/Register VLAN Table 4096 masks with allowed egress ports for each VID, and a flag – SourceChk - for checking the ingress port as being a member of the VLAN ...

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Advance Product Information Subject to Change Packet Information: DMAC, SMAC, VID, Ingress Port Within VLAN VID, DMAC VID: Find DMAC Egress Port(s) Ingress Port Find allowed Egress Ports for current Ingress Port VID, Ingress Port SMAC, DMAC Find Eggress Ports ...

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VSC7302 Data Sheet Table 6. MAC Address Table (cont’d) MAC Record Field Aged Flag Flag: ageing has run since last learn of this address Locked Flag Flag: entry is locked. It will not be aged out nor overwritten Valid Flag: ...

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Advance Product Information Subject to Change A MAC entry MUST be written into the correct hash chain, in order to be found by the search engines. Therefore, when accessing the table for specific addresses, the table index must comply with ...

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VSC7302 Data Sheet the locked flag must be set. In addition used for CPU Based Learning (see the ”CPU Based Learning” on page 42). When setting up a permanent station on a port, the CPU can write an ...

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Advance Product Information Subject to Change Aggregation Processing Link aggregation is a method of logically grouping a set of ports, so that two network stations can be interconnected using multiple links. All stations learned in a group of ports must ...

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VSC7302 Data Sheet The Port Masks must be set as shown in Table 8, (leftmost (rightmost). Table 8. Source Port Masks Port 2,6 ...

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Advance Product Information Subject to Change Table 10. Aggregation Port Mask (cont’d) Aggregation Key Exception Flags In the ...

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VSC7302 Data Sheet Basically, all the masks are ANDed. As previously mentioned, the flags reported by the DMAC process, the VLAN process, or the received Categorizer Classification can change this. Table 11. Categorizer Classes Categorizer Class MUSTBEKNOWN If the DMAC ...

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Advance Product Information Subject to Change Flow Control And Jumbo Frames The use of flow control while simultaneously allowing jumbo frames has limitations. This is because the amount of excess data that can arrive between the time a pause frame ...

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VSC7302 Data Sheet Egress high threshold = 3.5 kB When an egress frame is MAC initiated and n kB have already been received from the ingress port, the maximum amount of data to be stored during the MAC transmission is ...

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Advance Product Information Subject to Change odd number of writes occurred, write an extra word to CPUTXDAT 5. Set the CPU Tx bit of the MISCFIFO register A write operation to the CPUTXDAT queue can internally take ...

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VSC7302 Data Sheet 16 kB CPU Capture RAM Bytes 4087- Bytes 2040-4087 Payload bytes 1016-2039 Payload upto byte 1023-8 Type/Len/TAG SMAC, bits 31-0 DMAC 15-0 DMAC, bits 47-32 Header word 1 Header word 0 Header word 0 63 61-48 Pri ...

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Advance Product Information Subject to Change Table 12. Packet Header Format Header Field Pri The priority decided by the Categorizer (1 = high) Length The frame length excluding this header, including CRC Source Port The source port of the frame ...

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VSC7302 Data Sheet CPU Based Learning As default operation, Heathrow-III will auto learn all SMAC addresses into the MAC table. When more advanced learning policies are required, the CPU capture function can instead be used to allow CPU based learning ...

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Advance Product Information Subject to Change Example: How to continuously update the Link Status for PHY numbers 10-17. Set MIIMSCAN to PhyAddrLow = 10, PhyAddrHigh = 17, PhyRegMask = 0x0004. Set MIIMCMD to SCAN, READ, PhyAddr = 10, PhyReg = ...

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VSC7302 Data Sheet C ONFIGURATION Command Interfaces Through a CPU attached to Heathrow-III possible to configure, monitor, and collect statistics from different parts of the switching engine. In Heathrow-III, there are two buses attached to the internal register ...

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Advance Product Information Subject to Change The Serial Interface The Serial Interface (SI simple interface that operates as described in the “Serial Peripheral Interface” or “SPI” specification by Motorola (not to be confused with “SPI4” which is a ...

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VSC7302 Data Sheet SI Clock Select The internal timing of Heathrow-III means that the SI user must ensure at least a 600 ns delay from when the last bit of a read address is transmitted to when SI_CLK goes low ...

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Advance Product Information Subject to Change SI_nEN SI_CLK Block No. SI_DI CMD Byte SI_DO Figure 11. Figure 11: SI Read Operation With Clock Pause SI_nEN 50 ns (20 MHz) SI_CLK Block No. SI_DI 7 6 ...

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VSC7302 Data Sheet SI Configuration By the use of certain system registers possible to configure the SI protocol sequence. These possibilities exist: To select the byte order for the interface when sending 32 bit data words (endian selection) ...

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Advance Product Information Subject to Change Input/ Output I PI_Addr I/O PI_Data I PI_nWR I PI_nCS I PI_nOE O PI_nDone All inputs are latched a configurable amount of time after nCS falling. The delay is set in the CPUCTRL register, ...

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VSC7302 Data Sheet Example: 1. Read one of the half words of the register 2. Poll the SlowDone bit of CPUCTRL, or wait for SlowDone interrupt 3. Read one of the half words of the SLOWDATA register 4. Read the ...

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Advance Product Information Subject to Change As an example, system register 0 is read (Big endian mode) as shown in Table 21. PI Bus 8-Bit Data Width Example Heathrow-III Access No. Address 0 0xe000 1 0xe000 2 0xe001 3 0xe001 ...

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VSC7302 Data Sheet The mandatory operation for the software is split into an initialization sequence and a PHY polling operation. If the PHYs are running with fixed speed and duplex mode, the poll operation could be ignored, and the Heathrow-III ...

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Advance Product Information Subject to Change Port Mode Procedure Execute this procedure on a regular basis, for updating the port mode according to the PHY state. This example is made for illustrating the basic requirements only, but must be expanded ...

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VSC7302 Data Sheet Table 24. MAC Block Registers (Block 1/6) Address Register Name 00h MAC Config 02h Half Duplex Gaps 04h Flow Control Setup 08h Flow Control SMAC High 0Ch Flow Control SMAC Low 10h Max Length 11h Shaper Setup ...

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Advance Product Information Subject to Change Table 26. Categorizer Block Registers (Block 1/6) (cont’d) Address Register Name 78h DS Mapping Register High 79h DS Mapping Register Low 7Ch PVID Register 80h TCP/UDP Port Register 1 84h TCP/UDP Port Register 2 ...

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VSC7302 Data Sheet Table 28. Detailed Counters Block Registers (Block 1/6) (cont’d) Address Register Name ADh Rx 512-1023 Bytes AEh Rx 1024-long Bytes AFh Tx Drops B0h Tx Packets B1h Tx Broadcasts B2h Tx Multicasts B3h Tx Collisions B4h Tx ...

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Advance Product Information Subject to Change Table 31. Frame Arbiter Block Registers (Block 5) Address Register Name 0Ch Arbiter Empty 0Eh Arbiter Discard Table 32. CPU Capture Block Registers (Block 4) Address Register Name 00h Read Pointer 03h Write Pointer ...

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VSC7302 Data Sheet Table 33. Frame Analyzer Block Registers (Block 2) (cont’d) Address Register Name D0h VLAN Table Command E0h VLAN Table Index F0h Analyzer Config Register Register Description Unspecified fields in the registers must be written zero, and can ...

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Advance Product Information Subject to Change Table 35. SI Padding - SIPAD (Address 01h) Block 7 Subblock 0 Bit Name 2:0 SI Padding Note: Number of byte cycles (0–7) during SI read between command and the first byte read. Used ...

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VSC7302 Data Sheet Table 39. Chip Identification - CHIPID (Address 18h) Block 7 Subblock 0 Bit Name 31:28 REVISION_NUMBER 27:12 PART_NUMBER 11:1 MANUFACTURER_ID 0 RESERVED Note: This register returns the same value as the JTAG Identifier Table 40. Time Compare ...

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Advance Product Information Subject to Change Table 42. CPU Control - CPUCTRL (Address 30h) Block 7 Subblock 0 (cont’d) Bit Name 5 ExtCpu Use Slow 4 SlowDone 3 CPU Rx Frame Ready 2 Inverse INTR Polarity 1 Int Enable Packet ...

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VSC7302 Data Sheet MAC Block Registers (Block 1/6) Table 44. MAC Config - MACCONF (Address 00h) Block 1/6 Subblock 4-15/0-3 Bit Name 29 Port Reset 28 Tx_en 27 Seed Load 26:19 Back Off Seed 18 Full Duplex 17 Giga Mode ...

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Advance Product Information Subject to Change Table 45. Half Duplex Gaps - MACHDXGAP (Address 02h) Block 1/6 Subblock 4-15/0-3 Bit Name 11:8 LCOLPOS 7:4 IFG2 3:0 IFG1 Table 46. Flow Control Setup - FCCONF (Address 04h) Block 1/6 Subblock 4-15/0-3 ...

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VSC7302 Data Sheet Table 48. Flow Control SMAC Low - FCMACLO (Address 0Ch) Block 1/6 Subblock 4-15/0-3 Bit Name 23:0 Flow Control SMAC Low Table 49. Max Length - MAXLEN (Address 10h) Block 1/6 Subblock 4-15/0-3 Bit Name 16 Type/Len ...

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Advance Product Information Subject to Change Table 51. Policer Setup - POLICECONF (Address 12h) Block 1/6 Subblock 4-15/0-3 Bit Name 31 Drop Mode 30 Flow Control Mode 29 Reset 24:16 Bucket Threshold 11:0 Data Rate Note: The flow control frames ...

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VSC7302 Data Sheet Table 53. TBI Status Register - TBISTAT (Address 14h) Block 1/6 Subblock 4-15/0-3 (cont’d) Bit Name 20 Link Status 19:18 PCS State 17 ANEG Priority Resolution 16 ANEG Complete 15:0 Ability Note: This register must be polled ...

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Advance Product Information Subject to Change Table 55. Advanced Port Mode Setup - ADVPORTM (Address 19h) Block 1/6 Subblock 4-15/0-3 Bit Name 6 Loopback 5 Skip ERR XOR 4 Invert GTX 3 Halt GTX 0 TBI Enable Table 56. Transmit ...

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VSC7302 Data Sheet Shared FIFO Block Registers (Block 1/6) Table 58. CPU Transmit DATA - CPUTXDAT (Address C0h) Block 1/6 Subblock 4-15/0-3 Bit Name 31:0 CPU Transmit DATA Note: This register is used by the CPU to transmit frames. The ...

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Advance Product Information Subject to Change Table 60. Pool Control Register - POOLCFG (Address CCh) Block 1/6 Subblock 4-15/0-3 (cont’d) Bit Name 5:0 Ingress High Note: All the values are in 256-byte slices. Table 61. Drop Control Register - DROPCFG ...

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VSC7302 Data Sheet Table 63. Free RAM Counter - FREEPOOL (Address D8h) Block 1/6 Subblock 4-15/0-3 (cont’d) Bit Name 5:0 Egress Used Note: The default values for the use counters are above zero, due to a minimum allocation for each ...

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Advance Product Information Subject to Change Table 64. Categorizer Config - CATCONF (Address 60h) Block 1/6 Subblock 4-15/0-3 (cont’d) Bit Name 17 IPMC Ctrl snoop Capture Table 65. Categorizer Map Tag - CATTAG (Address 64h) Block 1/6 ...

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VSC7302 Data Sheet Table 68. IP Protocol Register - CATIPPRT (Address 70h) Block 1/6 Subblock 4-15/0-3 Bit Name 7:0 IP Protocol Register Note: Refer to the Frame Priority Determination in the Functional Description section. Table 69. Categorizer Priorities - CATPRIO ...

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Advance Product Information Subject to Change Table 72. PVID Register - CATPVID (Address 7Ch) Block 1/6 Subblock 4-15/0-3 Bit Name 31:20 Port vID 19 Port CFI Field 18:16 Port VLAN Priority 15:4 Port vID 3 Port CFI Field 2:0 Port ...

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VSC7302 Data Sheet Table 75. TCP/UDP Port Register 3 - CATPORT3 (Address 88h) Block 1/6 Subblock 4-15/0-3 Bit Name 31:16 Port 5 15:0 Port 6 Table 76. TCP/UDP Port Register 4 - CATPORT4 (Address 8Ch) Block 1/6 Subblock 4-15/0-3 Bit ...

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Advance Product Information Subject to Change Table 79. Rx Control Packets - RXCTRL (Address 39h) Block 1/6 Subblock 4-15/0-3 Bit Name 23:0 Rx Control Packets Table 80. Tx Total Error Packets - TXERR (Address 44h) Block 1/6 Subblock 4-15/0-3 Bit ...

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VSC7302 Data Sheet Table 84. Rx Packets - C_RXPKT (Address A1h) Block 1/6 Subblock 4-15/0-3 Bit Name 23:0 Rx Packets Note: For counting only good RX packets, the sum of high and low priority packets must be used (C_RXHP+C_RXLP). Table ...

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Advance Product Information Subject to Change Table 90. Rx Fragments - C_RXFRAG (Address A7h) Block 1/6 Subblock 4-15/0-3 Bit Name 23:0 Rx Fragments Table 91. Rx Jabbers - C_RXJAB (Address A8h) Block 1/6 Subblock 4-15/0-3 Bit Name 23:0 Rx Jabbers ...

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VSC7302 Data Sheet Table 96. Rx 512-1023 Bytes - C_RX512 (Address ADh) Block 1/6 Subblock 4-15/0-3 Bit Name 23:0 Rx 512-1023 Bytes Table 97. Rx 1024-long Bytes - C_RX1024 (Address AEh) Block 1/6 Subblock 4-15/0-3 Bit Name 23:0 Rx 1024-long ...

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Advance Product Information Subject to Change Table 102. Tx Collisions - C_TXCOL (Address B3h) Block 1/6 Subblock 4-15/0-3 Bit Name 23:0 Tx Collisions Table 103 Bytes - C_TX64 (Address B4h) Block 1/6 Subblock 4-15/0-3 Bit Name 23:0 Tx ...

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VSC7302 Data Sheet Table 108. Tx 1024-long Bytes - C_TX1024 (Address B9h) Block 1/6 Subblock 4-15/0-3 Bit Name 23:0 Tx 1024-long Bytes Note: The maximum frame length is set in the MAXLEN register. Table 109. Tx FIFO Drops - C_TXOVFL ...

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Advance Product Information Subject to Change MII Management Bus Block Registers (Block 3) Table 114. MII-M Status - MIIMSTAT (Address 00h) Block 3 Subblock 0-1 Bit Name 3 Busy 1 Reading 0 Writing Note: This register provides the status of ...

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VSC7302 Data Sheet Table 118. MII-M Scan setup - MIIMSCAN (Address 04h) Block 3 Subblock 0-1 Bit Name 25:21 PhyAddress HIGH 20:16 PhyAddress LOW 15:0 PhyRegMask Note: When the SCAN bit is set in the command register, the operation set ...

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Advance Product Information Subject to Change Frame Arbiter Block Registers (Block 5) Table 122. Arbiter Empty - ARBEMPTY (Address 0Ch) Block 5 Subblock 0 Bit Name 19:4 Arbiter Empty This register used when reseting a port to ...

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VSC7302 Data Sheet Table 124. Read Pointer - CAPREADP (Address 00h) Block 4 Subblock 4 Bit Name Note: Write anything to this register and the read pointer will be advanced to the next frame for readout. This register is only ...

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Advance Product Information Subject to Change Table 127. Advanced Learning Setup - ADVLEARN (Address 03h) Block 2 Subblock 0 Bit Name 19:4 LearnMirror Table 128. IP Multicast Flood Mask - IFLODMSK (Address 04h) Block 2 Subblock 0 Bit Name 19:4 ...

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VSC7302 Data Sheet Table 131. Ageing Filter - ANAGEFIL (Address 09h) Block 2 Subblock 0 Bit Name 15 vID Enab 11:0 vID Value Note: This register sets up which entries should be touched by an ageing operation. This way it ...

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Advance Product Information Subject to Change Table 132. Event Sticky Bits - ANEVENTS (Address 0Ah) Block 2 Subblock 0 (cont’d) Bit Name 2 CPU Operation 1 DMAC Lookup 0 SMAC Lookup Note: This register contains various debug event logs. A ...

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VSC7302 Data Sheet Table 137. Multicast Flood Mask - MFLODMSK (Address 0Fh) Block 2 Subblock 0 Bit Name 19:4 Multicast Flood Mask Table 138. Receive Mask - RECVMASK (Address 10h) Block 2 Subblock 0 Bit Name 19:4 Receive Mask Table ...

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Advance Product Information Subject to Change Table 141. Destination Port Masks - DSTMASKS (Address 40h - 7Fh) Block 2 Subblock 0 Bit Name Note: By default, Destination Port Masks 4-19 have the bit corresponding to their number set only. The ...

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VSC7302 Data Sheet Table 143. Mac Table Command - MACACCES (Address B0h) Block 2 Subblock 0 (cont’d) Bit Name 2:0 Mac Table Command Note: This register is used for updating or reading the MAC table from the CPU. The command ...

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Advance Product Information Subject to Change Table 146. Mac Address Low - MACLDATA (Address 07h) Block 2 Subblock 0 Bit Name 31:0 Mac Address Low Table 147. VLAN Table Command - VLANACES (Address D0h) Block 2 Subblock 0 Bit Name ...

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VSC7302 Data Sheet Table 149. Analyzer Config Register - AGENCNTL (Address F0h) Block 2 Subblock 0 (cont’d) Bit Name 8 Mirror CPU 7 Learn CPUCopy 6 Learn FwdKill 5 Learn Ignore VLAN 4:0 Mirror Port S D IGNAL ESCRIPTION To ...

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Advance Product Information Subject to Change Clock Circuits Table 151. Clk Interface Signal Name Type PLL_Cap0 A PLL Loop filter capacitor, connect 100 nF capacitor between the pins PLL_Cap1 Clk I, 3V System reference clock, LVTTL input. It can be ...

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VSC7302 Data Sheet Table 152. RGMII Ports (cont’d) Signal Name Type RGMII[0:15]_Tx_Ctrl O RGMII mode: Transmit control. On the rising edge of Tx_Clk it serves as transmit enable indicating valid data on TD[3:0]. On the falling edge it contains a ...

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Advance Product Information Subject to Change Parallel CPU Interface (PI) Table 155. PI Interface Signal Name Type PI_Addr0 I, 3V LSB PI_Addr1 PI_Addr2 PI_Addr3 PI_Addr4 PI_Addr5 PI_Addr6 Parallel CPU interface address bus PI_Addr7 Selects the block, subblock and address PI_Addr8 ...

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VSC7302 Data Sheet Serial Interface Table 156. SI Interface Signal Name Type SI_Clk clock from the master. SI_DI I, 3V Serial input from the master. SI_DO OZ, 3V Serial output to the master. SI_nEn ...

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Advance Product Information Subject to Change Miscellaneous Table 159. Miscellaneous Signals Signal Name Type nReset I, 3V Global chip reset, active low Test_Mode I, 3V Internal test, pull low to VSS VDD_Probe A Internal test, leave floating Reserved_0 NC Leave ...

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VSC7302 Data Sheet Table 160. Signal List by Ball Number Ball # Signal Name A1 VSS_77 A2 VSS_75 A3 VSS_74 A4 Reserved_94 A5 VSS_70 A6 Reserved_88 A7 VSS_68 A8 VDD_OUT25_6 A9 Reserved_78 A10 Reserved_75 A11 VSS_66 A12 Reserved_69 A13 Reserved_67 ...

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Advance Product Information Subject to Change Table 160. Signal List by Ball Number (cont’d) Ball # Signal Name C25 nReset C26 PI_Addr14 C27 VSS_52 C28 PI_Addr8 C29 PI_Addr5 C30 VSS_49 C31 PI_nCS C32 PI_nDone C33 VSS_47 C34 VDD_OUT33_2 C35 VSS_36 ...

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VSC7302 Data Sheet Table 160. Signal List by Ball Number (cont’d) Ball # Signal Name F39 PI_Data1 G1 Reserved_105 G2 Reserved_104 G3 VSS_84 G4 Reserved_103 G5 VDD_34 G35 VDD_13 G36 Reserved_50 G37 VSS_30 G38 VDD_IN_0 G39 Reserved_51 H1 VSS_86 H2 ...

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Advance Product Information Subject to Change Table 160. Signal List by Ball Number (cont’d) Ball # Signal Name U2 RGMII1_Rx_Ctrl U3 RGMII1_Rx_Clk U4 RGMII2_TD0 U5 VDD_42 U35 VDD_7 U36 Reserved_20 U37 Reserved_21 U38 Reserved_22 U39 VSS_22 V1 RGMII2_TD1 V2 VDD_OUT25_13 ...

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VSC7302 Data Sheet Table 160. Signal List by Ball Number (cont’d) Ball # Signal Name AG4 RGMII4_Tx_Ctrl AG5 VDD_47 AG35 VDD_2 AG36 RGMII15_RD0 AG37 VSS_14 AG38 RGMII15_RD1 AG39 RGMII15_RD2 AH1 VDD_OUT25_18 AH2 RGMII4_Tx_Clk AH3 RTBI4_SigDet AH4 RGMII4_RD0 AH5 VSS_102 AH35 ...

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Advance Product Information Subject to Change Table 160. Signal List by Ball Number (cont’d) Ball # Signal Name AR26 RGMII11_Tx_Clk AR27 VDD_61 AR28 VSS_141 AR29 VDD_62 AR30 RGMII12_Tx_Ctrl AR31 VDD_63 AR32 RGMII12_RD3 AR33 VDD_64 AR34 VDD_65 AR35 RGMII13_RD0 AR36 RGMII13_RD3 ...

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VSC7302 Data Sheet Table 160. Signal List by Ball Number (cont’d) Ball # Signal Name AV11 RGMII7_Rx_Clk AV12 VDD_OUT25_25 AV13 RGMII8_Tx_Ctrl AV14 RGMII8_RD1 AV15 RGMII8_RD3 AV16 RGMII9_TD1 AV17 RGMII9_Tx_Ctrl AV18 RGMII9_RD0 AV19 VDD_IN_17 AV20 RGMII10_TD1 AV21 RGMII10_TD2 AV22 RTBI10_SigDet AV23 ...

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Advance Product Information Subject to Change Table 161. Signal List by Signal Name Signal Name Ball # Clk Y37 Clk125_En A25 GPIO1 D21 GPIO2 A21 GPIO3 E20 GPIO4 D20 JTAG_nTRST D23 JTAG_TCK B24 JTAG_TDI A24 JTAG_TDO B23 JTAG_TMS C23 MDC_0 ...

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VSC7302 Data Sheet Table 161. Signal List by Signal Name (cont’d) Signal Name Ball # Reserved_46 J39 Reserved_47 H36 Reserved_48 H37 Reserved_49 H38 Reserved_50 G36 Reserved_51 G39 Reserved_52 F36 Reserved_53 F37 Reserved_54 B18 Reserved_55 C18 Reserved_56 B17 Reserved_57 C17 Reserved_58 ...

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Advance Product Information Subject to Change Table 161. Signal List by Signal Name (cont’d) Signal Name Ball # RGMII11_TD0 AU25 RGMII11_TD1 AT25 RGMII11_TD2 AW25 RGMII11_TD3 AV26 RGMII11_Tx_Clk AR26 RGMII11_Tx_Ctrl AU26 RGMII12_RD0 AT31 RGMII12_RD1 AV32 RGMII12_RD2 AU32 RGMII12_RD3 AR32 RGMII12_Rx_Clk AV33 ...

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VSC7302 Data Sheet Table 161. Signal List by Signal Name (cont’d) Signal Name Ball # RGMII6_RD0 AW5 RGMII6_RD1 AT6 RGMII6_RD2 AU6 RGMII6_RD3 AW6 RGMII6_Rx_Clk AT7 RGMII6_Rx_Ctrl AR8 RGMII6_TD0 AP5 RGMII6_TD1 AR4 RGMII6_TD2 AT3 RGMII6_TD3 AV2 RGMII6_Tx_Clk AW4 RGMII6_Tx_Ctrl AT5 RGMII7_RD0 ...

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Advance Product Information Subject to Change Table 161. Signal List by Signal Name (cont’d) Signal Name Ball # VDD_33 E5 VDD_34 G5 VDD_35 J5 VDD_36 K5 VDD_37 L4 VDD_38 L5 VDD_39 N5 VDD_40 R4 VDD_41 R5 VDD_42 U5 VDD_43 W5 ...

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VSC7302 Data Sheet Table 161. Signal List by Signal Name (cont’d) Signal Name Ball # VDD_OUT25_39 AJ37 VDD_OUT25_40 AH37 VDD_OUT25_41 AE38 VDD_OUT25_42 AD38 VDD_OUT25_43 V35 VDD_OUT25_44 V39 VDD_OUT25_45 P35 VDD_OUT25_46 N36 VDD_OUT25_47 K38 VDD_OUT25_48 J38 VDD_OUT33_0 B38 VDD_OUT33_1 E36 VDD_OUT33_2 ...

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Advance Product Information Subject to Change Table 161. Signal List by Signal Name (cont’d) Signal Name Ball # VSS_85 H5 VSS_86 H1 VSS_87 K3 VSS_88 L1 VSS_89 M5 VSS_90 N3 VSS_91 P1 VSS_92 T3 VSS_93 U1 VSS_94 W3 VSS_95 Y5 ...

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VSC7302 Data Sheet E S LECTRICAL PECIFICATIONS Unless otherwise noted, the DC and AC electrical specifications in this section are guaranteed over process, recommended supply voltage. General Electrical Specifications The recommended operating conditions are listed in Table 163. Table 162. ...

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Advance Product Information Subject to Change Table 163. Absolute Maximum Ratings (cont’d) Parameter ESD (Human Body Model) Note: Stresses listed under Absolute Maximum Ratings may be applied to devices one at a time without causing permanent damage. Functionality at or ...

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VSC7302 Data Sheet Table 165. DC Specifications for RGMII and RTBI Symbol Parameter V Output high voltage OH V Output low voltage OL V Input high voltage IH V Input low voltage IL I Input current IH I Input low ...

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Advance Product Information Subject to Change Table 167. DC Specifications for PI, SI, JTAG, and Other Control Signals Symbol Parameter V Output high voltage OH V Output low voltage Input high voltage IH V Input low voltage ...

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VSC7302 Data Sheet Table 168. Maximum Operating Current (cont’d) Symbol Parameter I Average active operating DD_PLL current for PLL Note: All power consumption figures assume 100% TX activity. Typical Current Consumption Table 169 shows typical figures for current consumption for ...

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Advance Product Information Subject to Change Table 170. System Clock AC Specifications (cont’d) Symbol Parameter Clk rise/fall time r f Notes: 1. Typical values are at 25°C. 2. The frequency tolerance of the output clocks of the ...

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VSC7302 Data Sheet Table 171. nReset AC Specifications (cont’d) Symbol Parameter Rise and fall time of nReset r f Note 1. Guaranteed by design. RGMII (10/100/1000 Mb/s) And RTBI (1000 Mb/s) All AC specifications for the RGMII ...

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Advance Product Information Subject to Change All RGMII and RTBI transmit signals comply with the specifications in using the test circuit in Figure 18. All RGMII and RTBI receive signal requirements are requested at the chip pins. Table 172. RGMII ...

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VSC7302 Data Sheet RGMII driver Figure 18. RGMII and RTBI Test Circuit MII Management All ac specifications for the MII Management interface has been designed to meet or exceed the requirements of IEEE Std 802.3-2002 (clause 22.2-4). Figure 19 shows ...

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Advance Product Information Subject to Change Table 174. MII Management AC Specifications Symbol Parameter f MDC frequency clk t MDC cycle time c t MDC time high w(CH) t MDC time low w(CL) t MDIO setup to MDC on write ...

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VSC7302 Data Sheet SI_nEn (Input) SI_Clk (Input) SI_DO (Output) SI_DI (Input) Note: Not defined, but normally content from next address All SI signals complies with the specifications in the chip pins. Table 175. SI Interface AC Specifications Symbol Parameter f ...

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Advance Product Information Subject to Change Table 175. SI Interface AC Specifications (cont’d) Symbol Parameter disable time dis Notes: 1. The SI clock frequency may MHz, but if it exceeds 0.5 MHz, dummy ...

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VSC7302 Data Sheet PI_Addr[15:0] PI_Data[15:0] PI_nOE PI_nWR PI_nCS PI_nDone Figure 23. PI Write Cycle (Input to Chip) PI_Addr[15:0] PI_Data[15:0] PI_nOE PI_nWR PI_nCS PI_nDone All PI signals complies with the specification in chip pins. 140 d(SLNH) ...

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Advance Product Information Subject to Change Table 176. PI Interface AC Specifications Symbol Parameter t PI_Addr, PI_Data, PI_nWR setup su to PI_nCS falling t PI_Addr, PI_Data, PI_nWR hold h from PI_nCS falling t Delay from low PI_nCS to rising d(SLNH) ...

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VSC7302 Data Sheet PI_Addr[15:0] PI_Data[15:0] PI_Addr[15:0] PI_Data[15:0] JTAG All AC specifications for the JTAG interface have been designed to meet or exceed the requirements of IEEE Std 1149.1-2001. Figure 28 shows the JTAG transmit and receive waveforms and required measurement ...

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Advance Product Information Subject to Change TCK TDI TMS TDO nTRST Figure 28. JTAG Interface Timing Definitions All JTAG signals comply with the specifications in requested at the chip pin. Table 177. JTAG AC Specifications Symbol Parameter f TCK frequency ...

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VSC7302 Data Sheet Figure 29. Test Circuit for Signal Disable Test D G ESIGN UIDE Power Supplies Power Supply Decoupling It is important to have the power supplies very well decoupled, because Heathrow-III's signals have short fall/rise times. To make ...

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Advance Product Information Subject to Change 3.3 V Output Supply (VDD_OUT33) All VDD_OUT33 pins must be connected to the same power supply. 2.5 V Output Supply (VDD_OUT25) All VDD_OUT25 pins must be connected to the same power supply. Input Power ...

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VSC7302 Data Sheet PLL Inputs The reference clock to Heathrow-III can be either a 25 MHz or a 125 MHz clock. The function is: CLK125_EN selects 125 MHz clock if high or 25 MHz clock if low. CLK must be ...

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Advance Product Information Subject to Change Interfaces MII Management Heathrow-III includes two identical management busses recommended that they are equally loaded and the layout is done very carefully recommend that the clock signal (MDCx) is routed ...

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VSC7302 Data Sheet This interface can be configured either as an 8-bit or a 16-bit interface. If configured as an 8-bit interface, PI_Data[7..0] carries data information and PI_Data[15..8] needs to be pulled (high is preferred). For address mapping using an ...

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Advance Product Information Subject to Change Termination Considerations MAC Interfaces All signals in the MAC interface and the reference Clk input (both on VSC7302 and the PHYs), require termination considerations. All RGMII/RTBI outputs were designed to drive one load and ...

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VSC7302 Data Sheet P P RELIMINARY ACKAGE Package Outline All Measurements are in mm Body Size: 40.00 x 40.00 TSBGA Package No. of Balls: 680 Ball Pitch: 1.00 Ball Footprint Ball Corner Location Indication on Top ...

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... PCB). For more information, see the JEDEC standard. Table 178. Thermal Resistances Part Number JC VSC7302VF 0.1 Moisture Sensitivity Level This device is rated moisture sensitivity level 3 or better as specified in the JEDEC standard IPC/JEDEC J-STD- 020B. For more information, see the JEDEC standard. ...

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VSC7302 Data Sheet Workaround To make room for pause frames necessary to limit the egress data stream by use of the built-in shaper to ensure loss-free operation. By the use of the shaper, a port can be configured ...

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... As a consequence, some frames will be lost due to aging and FIFO drop, but the link will begin to carry traffic again RDERING NFORMATION Part Number VSC7302VF Heathrow-III Gb/s Ethernet Switch Package type VF: 680-pin Tape Super BGA with grounded heat spreader VMDS-10082 Revision 2.0 140 November 14, 2003 ...

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VSC7302 Data Sheet S R TANDARD EFERENCES Ports The Ethernet ports have been designed to meet or exceed the requirements found in the following standards: IEEE Std 802.3-2002 Edition for Ethernet, Fast Ethernet and Gigabit Ethernet Hewlett Packard RGMII specification ...

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Advance Product Information Subject to Change Table 179. Abbreviations (cont’d) Abbreviation Mpackets/s million packets per second MSB most significant bit/byte PCS physical coding sublayer PHY physical layer device QoS quality of service Rbc receive bit clock RFC request for comments ...

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VSC7302 Data Sheet For application support, latest technical literature, and locations of sales offices, Copyright © 2003 by Vitesse Semiconductor Corporation PRINTED IN THE U.S.A Vitesse Semiconductor Corporation (“Vitesse”) retains the right to make changes to its products or specifications ...