MT4LC16M4G3DJ-6 Micron Semiconductor Products, MT4LC16M4G3DJ-6 Datasheet

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MT4LC16M4G3DJ-6

Manufacturer Part Number
MT4LC16M4G3DJ-6
Description
Manufacturer
Micron Semiconductor Products
Datasheet
DRAM
FEATURES
• Single +3.3V ±0.3V power supply
• Industry-standard x4 pinout, timing, functions,
• 12 row, 12 column addresses (H9) or
• High-performance CMOS silicon-gate process
• All inputs, outputs and clocks are LVTTL-compat-
• Extended Data-Out (EDO) PAGE MODE access
• Optional self refresh (S) for low-power data
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH
OPTIONS
• Refresh Addressing
• Plastic Packages
• Timing
• Refresh Rates
NOTE: 1. The 16 Meg x 4 EDO DRAM base number
*Contact factory for availability
KEY TIMING PARAMETERS
16 Meg x 4 EDO DRAM
D22_2.p65 – Rev. 5/00
SPEED
and packages
13 row, 11 column addresses (G3)
ible
retention
distributed across 64ms
4,096 (4K) rows
8,192 (8K) rows
32-pin SOJ (400 mil)
32-pin TSOP (400 mil)
50ns access
60ns access
Standard Refresh
Self Refresh (128ms period)
-5
-6
2. The “#” symbol indicates signal is active LOW.
104ns
differentiates the offerings in one place—
MT4LC16M4H9. The fifth field distinguishes the
address offerings: H9 designates 4K addresses and
G3 designates 8K addresses.
84ns
t
RC
MT4LC16M4H9DJ-6
t
50ns
60ns
RAC
Part Number Example:
20ns
25ns
t
PC
25ns
30ns
t
AA
MARKING
t
13ns
15ns
CAC
None
H9
G3
TG
DJ
-5
-6
S*
t
10ns
CAS
8ns
1
MT4LC16M4G3, MT4LC16M4H9
For the latest data sheet, please refer to the Micron Web
site:
16 MEG x 4 EDO DRAM PART NUMBERS
x = speed
GENERAL DESCRIPTION
dynamic random-access memory device containing
67,108,864 bits and designed to operate from 3V to
3.6V. The MT4LC16M4H9 and MT4LC16M4G3 are
functionally organized as 16,777,216 locations con-
taining 4 bits each. The 16,777,216 memory locations
are arranged in 4,096 rows by 4,096 columns on the H9
version and 8,192 rows by 2,048 columns on the G3
version. During READ or WRITE cycles, each location is
RAS#
MT4LC16M4H9DJ-x
MT4LC16M4H9DJ-x S
MT4LC16M4H9TG-x
MT4LC16M4H9TG-x S
MT4LC16M4G3DJ-x
MT4LC16M4G3DJ-x S
MT4LC16M4G3TG-x
MT4LC16M4G3TG-x S
WE#
DQ0
DQ1
PART NUMBER
V
V
NC
NC
NC
NC
A0
A1
A2
A3
A4
A5
CC
CC
**NC on H9 version, A12 on G3 version
The 16 Meg x 4 DRAM is a high-speed CMOS,
www.micronsemi.com/mti/msp/html/datasheet.html
Micron Technology, Inc., reserves the right to change products or specifications without notice.
32-Pin SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN ASSIGNMENT (Top View)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vss
DQ3
DQ2
NC
NC
NC
CAS#
OE#
NC /A12**
A11
A10
A9
A8
A7
A6
Vss
ADDRESSING
REFRESH
4K
4K
4K
4K
8K
8K
8K
8K
RAS#
WE#
DQ0
DQ1
V
V
NC
NC
NC
NC
A0
A1
A2
A3
A4
A5
CC
CC
32-Pin TSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PACKAGE
16 MEG x 4
EDO DRAM
TSOP
TSOP
TSOP
TSOP
SOJ
SOJ
SOJ
SOJ
©2000, Micron Technology, Inc.
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Standard
Standard
Standard
Standard
REFRESH
Self
Self
Self
Self
Vss
DQ3
DQ2
NC
NC
NC
CAS#
OE#
NC/A12**
A11
A10
A9
A8
A7
A6
Vss

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MT4LC16M4G3DJ-6 Summary of contents

Page 1

... PART NUMBER -6 MT4LC16M4H9DJ-x MT4LC16M4H9DJ-x S MT4LC16M4H9TG-x None MT4LC16M4H9TG MT4LC16M4G3DJ-x MT4LC16M4G3DJ-x S MT4LC16M4G3TG-x MT4LC16M4G3TG speed GENERAL DESCRIPTION The 16 Meg x 4 DRAM is a high-speed CMOS, dynamic random-access memory device containing 67,108,864 bits and designed to operate from 3V to 3.6V. The MT4LC16M4H9 and MT4LC16M4G3 are functionally organized as 16,777,216 locations con- taining 4 bits each ...

Page 2

WE# CAS# NO. 2 CLOCK GENERATOR COLUMN- ADDRESS A0 11 BUFFER(11 REFRESH CONTROLLER REFRESH A7 COUNTER A10 ROW- A11 ADDRESS 13 A12 BUFFERS (13) NO. 1 CLOCK RAS# GENERATOR WE# CAS# ...

Page 3

GENERAL DESCRIPTION (Continued) uniquely addressed via the address bits. First, the row address is latched by the RAS# signal, then the column address is latched by CAS#. The device provides EDO- PAGE-MODE operation, allowing for fast successive data operations (READ, ...

Page 4

DRAM REFRESH (Continued) The self refresh mode is terminated by driving RAS# t HIGH for a minimum time of RPS. This delay allows for the completion of any internal refresh cycles that may be in process at the time of ...

Page 5

ABSOLUTE MAXIMUM RATINGS* Voltage on V Relative to V ................ -1V to +4. Voltage on NC, Inputs or I/O Pins Relative to V ....................................... -1V to +4.6V SS Operating Temperature, T (ambient) ... 0°C to +70°C A Storage ...

Page 6

ICC OPERATING CONDITIONS AND MAXIMUM LIMITS (Notes +3.3V ±0.3V) CC PARAMETER/CONDITION STANDBY CURRENT: TTL (RAS# = CAS STANDBY CURRENT: CMOS (RAS# = CAS 0.2V; DQs may be ...

Page 7

CAPACITANCE (Note: 2) PARAMETER Input Capacitance: Address pins Input Capacitance: RAS#, CAS#, WE#, OE# Input/Output Capacitance ELECTRICAL CHARACTERISTICS (Notes 10, 11, 12 CHARACTERISTICS PARAMETER Access time from column address Column-address setup ...

Page 8

AC ELECTRICAL CHARACTERISTICS (Notes 10, 11, 12 CHARACTERISTICS PARAMETER OE# setup prior to RAS# during HIDDEN REFRESH cycle EDO-PAGE-MODE READ or WRITE cycle time EDO-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# ...

Page 9

NOTES 1. All voltages referenced This parameter is sampled. V MHz 25° dependent on output loading and cycle CC rates. Specified values are obtained with mini- mum cycle time and ...

Page 10

V IH RAS CRP V CAS ASR V IH ROW ADDR WE OE TIMING PARAMETERS -5 SYMBOL MIN ...

Page 11

V IH RAS CRP CAS ASR V IH ADDR ROW IOH DQ V IOL TIMING PARAMETERS -5 SYMBOL MIN ...

Page 12

WRITE and READ-MODIFY-WRITE cycles RAS CRP V IH CAS ASR V IH ADDR V ROW WE IOH DQ V IOL ...

Page 13

V IH RAS CSH t CRP V CAS RAD t ASR t RAH V IH ADDR V ROW OPEN OE# ...

Page 14

EDO-PAGE-MODE EARLY WRITE CYCLE V IH RAS CSH t CRP V IH CAS RAD t ASR t RAH V IH ADDR ROW WCS ...

Page 15

WRITE and READ-MODIFY-WRITE cycles RAS CRP V IH CAS ASR V IH ADDR V ROW WE IOH DQ V IOL ...

Page 16

EDO-PAGE-MODE READ EARLY WRITE CYCLE V IH RAS CRP t RCD V IH CAS RAD t ASR t RAH V IH ADDR ROW WE IOH DQ OPEN ...

Page 17

V IH RAS CRP V CAS ASR V IH ADDR WE OE TIMING PARAMETERS -5 SYMBOL MIN MAX ...

Page 18

V IH RAS CRP V IH CAS ASR V IH ADDR RAS RPC CSR V IH CAS# ...

Page 19

V IH RAS CRP CAS ASR t RAH V IH ADDR ROW OE TIMING PARAMETERS -5 SYMBOL MIN MAX t AA ...

Page 20

RAS RPC CSR V IH CAS WRP TIMING PARAMETERS -5 SYMBOL MIN MAX t CHD 15 t ...

Page 21

PIN #1 ID .050 (1.27) TYP .024 (0.61) .032 (0.82) .026 (0.67) SEATING PLANE NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. 2. Package width and length do ...

Page 22

TYP 32 1 .020 (0.50) .012 (0.30) NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" ...

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