MT4LC8M8B6DJ-5 Micron Semiconductor Products, MT4LC8M8B6DJ-5 Datasheet

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MT4LC8M8B6DJ-5

Manufacturer Part Number
MT4LC8M8B6DJ-5
Description
Manufacturer
Micron Semiconductor Products
Datasheet
DRAM
FEATURES
• Single +3.3V ±0.3V power supply
• Industry-standard x8 pinout, timing, functions,
• 13 row, 10 column addresses (E1) or
• High-performance CMOS silicon-gate process
• All inputs, outputs and clocks are LVTTL-
• FAST PAGE MODE (FPM) access
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH
• Optional self refresh (S) for low-power data
OPTIONS
• Refresh Addressing
• Plastic Packages
• Timing
• Refresh Rates
NOTE: 1. The 8 Meg x 8 FPM DRAM base number
*Contact factory for availability
KEY TIMING PARAMETERS
8 Meg x 8 FPM DRAM
D19_2.p65 – Rev. 5/00
SPEED
and packages
12 row, 11 column addresses (B6)
compatible
distributed across 64ms
retention
4,096 (4K) rows
8,192 (8K) rows
32-pin SOJ (400 mil)
32-pin TSOP (400 mil)
50ns access
60ns access
Standard Refresh (64ms period)
Self Refresh (128ms period)
-5
-6
2. The # symbol indicates signal is active LOW.
differentiates the offerings in one place—
MT4LC8M8E1. The fifth field distinguishes
various options: E1 designates an 8K refresh and
B6 designates a 4K refresh for FPM DRAMs.
110ns
90ns
t
RC
MT4LC8M8E1DJ-5
Part Number Example:
t
50ns
60ns
RAC
30ns
35ns
t
PC
25ns
30ns
t
MARKING
AA
None
TG
B6
E1
DJ
-5
-6
S*
t
13ns
15ns
CAC
1
MT4LC8M8E1, MT4LC8M8B6
For the latest data sheet, please refer to the Micron Web
site:
8 MEG x 8 FPM DRAM PART NUMBERS
x = speed
GENERAL DESCRIPTION
namic random-access memory devices containing
67,108,864 bits organized in a x8 configuration. The
8 Meg x 8 DRAMs are functionally organized as 8,388,608
locations containing eight bits each. The 8,388,608
memory locations are arranged in 8,192 rows by 1,024
columns for the MT4LC8M8E1 or 4,096 rows by 2,048
columns for the MT4LC8M8B6. During READ or WRITE
cycles, each location is uniquely addressed via the
address bits. First, the row address is latched by the
RAS#
PART NUMBER
MT4LC8M8E1DJ-x
MT4LC8M8E1DJ-x S
MT4LC8M8E1TG-x
MT4LC8M8E1TG-x S
MT4LC8M8B6DJ-x
MT4LC8M8B6DJ-x S
MT4LC8M8B6TG-x
MT4LC8M8B6TG-x S
WE#
DQ0
DQ1
DQ2
DQ3
V
V
V
**A12 on E1 version, NC on B6 version
NC
A0
A1
A2
A3
A4
A5
CC
CC
CC
The 8 Meg x 8 DRAMs are high-speed CMOS, dy-
www.micron.com/products/datasheets/dramds.html
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-Pin SOJ
PIN ASSIGNMENT (Top View)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
ADDRESSING PACKAGE REFRESH
V
DQ7
DQ6
DQ5
DQ4
Vss
CAS#
OE#
NC /A12**
A11
A10
A9
A8
A7
A6
V
SS
SS
REFRESH
8K
8K
8K
8K
4K
4K
4K
4K
RAS#
DQ0
DQ1
DQ2
DQ3
WE#
V
V
V
NC
A0
A1
A2
A3
A4
A5
CC
CC
CC
32-Pin TSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FPM DRAM
8 MEG x 8
TSOP
TSOP
TSOP
TSOP
SOJ
SOJ
SOJ
SOJ
©2000, Micron Technology, Inc.
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Standard
Standard
Standard
Standard
V
DQ7
DQ6
DQ5
DQ4
V
CAS#
OE#
NC/A12**
A11
A10
A9
A8
A7
A6
V
Self
Self
Self
Self
SS
SS
SS

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MT4LC8M8B6DJ-5 Summary of contents

Page 1

... MT4LC8M8E1DJ MT4LC8M8E1DJ-x S MT4LC8M8E1TG-x MT4LC8M8E1TG-x S None MT4LC8M8B6DJ-x S* MT4LC8M8B6DJ-x S MT4LC8M8B6TG-x MT4LC8M8B6TG speed GENERAL DESCRIPTION The 8 Meg x 8 DRAMs are high-speed CMOS, dy- namic random-access memory devices containing 67,108,864 bits organized configuration. The 8 Meg x 8 DRAMs are functionally organized as 8,388,608 locations containing eight bits each. The 8,388,608 ...

Page 2

WE# CAS# NO. 2 CLOCK GENERATOR COLUMN- ADDRESS 10 BUFFER(10) REFRESH CONTROLLER A0- A12 REFRESH COUNTER 13 ROW- ADDRESS 13 BUFFERS (13) NO. 1 CLOCK RAS# GENERATOR WE# CAS# NO. 2 CLOCK GENERATOR COLUMN- ADDRESS 11 BUFFER(11) REFRESH CONTROLLER A0- ...

Page 3

GENERAL DESCRIPTION (continued) RAS# signal, then the column address by CAS#. Both devices provide FAST-PAGE-MODE operation, allow- ing for fast successive data operations (READ, WRITE, or READ-MODIFY-WRITE) within a given row. The MT4LC8M8E1 and MT4LC8M8B6 must be re- freshed periodically ...

Page 4

ABSOLUTE MAXIMUM RATINGS* Voltage on V Relative to V ................ -1V to +4. Voltage on NC, Inputs or I/O Pins Relative to V ....................................... -1V to +4.6V SS Operating Temperature, T (ambient) ... 0°C to +70°C A Storage ...

Page 5

I OPERATING CONDITIONS AND MAXIMUM LIMITS CC (Notes +3.3V ±0.3V) CC PARAMETER/CONDITION STANDBY CURRENT: TTL (RAS# = CAS STANDBY CURRENT: CMOS (RAS# = CAS# ž 0.2V; DQs ...

Page 6

CAPACITANCE (Note: 2) PARAMETER Input Capacitance: Address pins Input Capacitance: RAS#, CAS#, WE#, OE# Input/Output Capacitance ELECTRICAL CHARACTERISTICS (Notes 10, 11, 12 CHARACTERISTICS PARAMETER Access time from column address Column-address hold ...

Page 7

AC ELECTRICAL CHARACTERISTICS (Notes 10, 11, 12 CHARACTERISTICS PARAMETER RAS# to column-address delay time Row-address hold time RAS# pulse width RAS# pulse width (FAST PAGE MODE) RAS# pulse width during Self Refresh Random ...

Page 8

NOTES 1. All voltages referenced This parameter is sampled. V MHz dependent on output loading and cycle CC rates. Specified values are obtained with mini- mum cycle time and the outputs open. 4. ...

Page 9

V IH RAS CRP V IH CAS ASR V IH ROW ADDR WE IOH DQ V IOL TIMING PARAMETERS -5 SYMBOL MIN MAX ...

Page 10

V IH RAS CRP V IH CAS ASR V IH ADDR ROW WE IOH DQ V IOL TIMING PARAMETERS -5 SYMBOL MIN MAX ...

Page 11

WRITE and READ-MODIFY-WRITE cycles RAS CRP V IH CAS ASR V IH ADDR V ROW WE IOH DQ V IOL ...

Page 12

V IH RAS CSH t CRP V IH CAS RAD t ASR t RAH V IH ADDR V ROW WE IOH DQ OPEN V IOL V IH OE# ...

Page 13

FAST-PAGE-MODE EARLY WRITE CYCLE V IH RAS CSH t CRP V IH CAS RAD t ASR t RAH V IH ADDR ROW WCS ...

Page 14

FAST-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles RAS CRP V IH CAS RAD t ASR t RAH V IH ADDR ROW WE ...

Page 15

FAST-PAGE-MODE READ EARLY WRITE CYCLE V IH RAS CRP V IH CAS ASR t RAH V IH ADDR V ROW WE TIMING PARAMETERS -5 ...

Page 16

V IH RAS CRP V IH CAS ASR V IH ADDR RAS RPC CSR V IH CAS# ...

Page 17

V IH RAS CRP V IH CAS ASR t RAH V IH ADDR ROW IOH DQ V IOL TIMING PARAMETERS -5 SYMBOL MIN MAX t AA ...

Page 18

RAS RPC CSR V IH CAS WRP TIMING PARAMETERS -5 SYMBOL MIN MAX t CHD 15 t ...

Page 19

PIN #1 ID .024 (0.61) .032 (0.82) .026 (0.67) SEATING PLANE NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. 2. Package width and length do not include mold ...

Page 20

TYP PIN 1 ID +0.07 0.43 -0.13 NOTE: 1. All dimensions in millimeters MAX or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is .25mm per side. 8000 S. ...

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