T35L6464A-5Q Taiwan Semiconductor Company, Ltd. (TSC), T35L6464A-5Q Datasheet

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T35L6464A-5Q

Manufacturer Part Number
T35L6464A-5Q
Description
Manufacturer
Taiwan Semiconductor Company, Ltd. (TSC)
Datasheet
tm
SYNCHRONOUS
BURST SRAM
FEATURES
OPTIONS
Part Number Examples
Taiwan Memory Technology, Inc. reserves the right P. 1
to change products or specifications without notice.
PART NO.
T35L6464A -5Q
T35L6464A -5L
Fast Access times: 5, 6, 7, and 8ns
Fast clock speed: 100, 83, 66, and 50 MHz
Provide high performance 3-1-1-1 access rate
Fast OE access times: 5 and 6ns
Single 3.3V +10% / -5V power supply
Common data inputs and data outputs
BYTE WRITE ENABLE and GLOBAL
Five chip enables for depth expansion and
Address, control, input, and output pipelined
Internally self -timed WRITE cycle
WRITE pass-through capability
Burst control pins ( interleaved or linear burst
High density, high speed packages
Low capacitive bus loading
High 30pF output drive capability at rated access
SNOOZE MODE for reduced power standby
Single cycle disable ( Pentium
WRITE control
address pipelining
registers
sequence)
time
compatible )
TIMING
Package
5ns access/10ns cycle
6ns access/12ns cycle
7ns access/15ns cycle
8ns access/20ns cycle
128-pin QFP
128-pin LQFP
CH
TE
Pkg.
Q
L
BURST SEQUENCE
Interleaved
(MODE=NC or VCC)
Linear (MODE=GND)
T M
BSRAM
MARKING
-5
-6
-7
-8
Q
L
VSSQ
VCCQ
VSSQ
VCCQ
VSSQ
VCCQ
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ64
PIN ASSIGNMENT (Top View)
GENERAL DESCRIPTION
Burst RAM family employs: high-speed, low power
CMOS
polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two
high valued resistors.
SRAM cells with advanced synchronous peripheral
circuitry and a 2-bit counter for internal burst
operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered
clock input (CLK). The synchronous inputs include
all addresses, all data inputs, three active LOW
chip enable ( CE , CE2 and CE3 ), two additional
chip enables (CE2 and CE3) , burst control inputs
3.3V SUPPLY, FULLY REGISTERED AND OUTPUTS,
32
33
34
35
36
37
38
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1
2
3
4
5
6
7
8
9
The Taiwan Memory Technology Synchronous
The T35L6464A SRAM integrates 65536 x 64
128127126125
39
40
41
42
design
124
43
123
44
122
45
121
46
64K x 64 SRAM
120
47
119
128-pin LQFP
48
128-pin QFP
Publication Date: AUG. 1998
using
118
49
117
50
116115114113112111110109
51
or
52
53
advanced
54
55
56
T35L6464A
57
BURST COUNTER
58
108107106105104103
59
60
Revision: E
61
triple-layer
62
63
102
101
100
64
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VCCQ
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
VSSQ
VCCQ
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
VSSQ
VCCQ
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
VSSQ

Related parts for T35L6464A-5Q

T35L6464A-5Q Summary of contents

Page 1

... Each -8 memory cell consists of four transistors and two high valued resistors. The T35L6464A SRAM integrates 65536 SRAM cells with advanced synchronous peripheral L circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK) ...

Page 2

... AMPS ARRAY 8 8 BYTE 4 WRITE DRIVER 8 8 BYTE 3 64 WRITE DRIVER 8 8 BYTE 2 WRITE DRIVER 8 8 BYTE 1 WRITE DRIVER PIPELINED ENABLE 8 T35L6464A controls DQ1-DQ8. BW2 controls DQ17-DQ24. BW3 DQ25-DQ32. BW5 controls BW6 controls DQ41-DQ48. BW8 DQ49-DQ56. controls , , , , BW1 BW2 BW3 BW4 ...

Page 3

... This input can be used for memory depth expansion. Synchronous Chip Enable: This active HIGH input is used to enable is loaded. This input can be used for memory depth expansion. Output enable: This active LOW asynchronous input enables the data output drivers T35L6464A controls DQ9- BW2 controls DQ25-DQ32. BW4 controls DQ41-DQ48. ...

Page 4

... Fifth Byte is DQ33- DQ40. Sixth Byte is DQ41- DQ48. Seventh Byte is DQ49- DQ56. Eighth Byte is DQ57- DQ64. Input data must meet setup and hold times around the rising edge of CLK. Power Supply: 3.3V +10%/-5%. Ground: GND No Connect: These signals are not internally conntected T35L6464A CE Publication Date: AUG. 1998 Revision: E ...

Page 5

... T35L6464A Fourth Address (internal) A...A11 A...A10 A...A01 A...A00 Fourth Address (internal) A...A11 A...A00 A...A01 A...A10 BW4 BW5 BW6 BW7 BW8 ...

Page 6

... H means all byte write signal are HIGH. GW WRITE = enables write to DQ9-DQ16. BW2 =enables write to DQ25-DQ32. = enables write to DQ49-DQ56. BW7 must meet setup and hold times around the rising edge ( LOW to HIGH) OE and staying HIGH throughout the input data hold T35L6464A CLK L L-H X ...

Page 7

... 8.0 mA Supply Voltage Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. T35L6464A *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any ...

Page 8

... I SB3 SB4 30 81 SYM. TYP VCC = 3.3V 6 CONDITIONS SYM. QFP TYP UNITS Still air, soldered on JA 4.25x 1.125 inch 4-layer PCB T35L6464A UNITS NOTES 260 240 210 12, 13 ...

Page 9

... P. 9 T35L6464A - 8,10 0.5 ns 8,10 0.5 ns 8,10 0.5 ns 8,10 ...

Page 10

... C and = 20ns cycle time. L 14.MODE pin has an internal pull-up and exhibits an input leakage current =1.5V 3.3V DQ 351 P. 10 T35L6464A HIGH for the ADSP LOW) or LOW for ADV ADSP 317 5 pF Publication Date: AUG. 1998 Revision: E ...

Page 11

... SYMBOL MIN KC) t RZZ Vss + 0 Vcc -0.2 V T35L6464A is guaranteed after the setup time Z Z MAX UNITS NOTES KC DON'T CARE Publication Date: AUG ...

Page 12

... ( Q (NOT this diagram, when T35L6464A urs tinue d w ith new Des elec le its inita ...

Page 13

... D(A2) D(A2+1) D(A2+1) D(A2+2) (NOT this diagram, when CE CE2 CE3 is HIGH T35L6464A D(A2+3) D(A3) D(A3+1) D(A3+2) Exte WRIT E DON 'T CAR E UND CE2 is LOW, ...

Page 14

... -throu this diagram, when CE is HIGH ADSP P. 14 T35L6464A (A5) D (A6) Q(A 4 k-to WRIT ARE UN DEF INED ...

Page 15

... Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. y DIMENTION IN MM 3.400(MAX) 2.720+0.180-0.220 0.250(MIN) 0.200+0.070-0.030 14.000 20.000 0.500 17.200 23.200 0.880±0.150 1.600 ± 0.150 0.150+0.080-0.040 0.080 0 ~7 P.15 T35L6464A Publication Date: AUG. 1998 Revision: E ...

Page 16

... Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. y DIMENTION IN MM 1.600(MAX) 1.400±0.050 0.050(MIN) 0.200+0.070-0.030 14.000 20.000 0.500 16.000 22.000 0.600±0.150 1.000 0.090(MIN),0.200(MAX) 0.080 0 ~7 P.16 T35L6464A Publication Date: AUG. 1998 Revision: E ...

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