XC56303PV80 Motorola, XC56303PV80 Datasheet
XC56303PV80
Specifications of XC56303PV80
Available stocks
Related parts for XC56303PV80
XC56303PV80 Summary of contents
Page 1
... The DSP56303 is a member of the DSP56300 core family of programmable CMOS Digital Signal Processors (DSPs). This family uses a high performance, single-clock-cycle-per-instruction engine providing a two-fold performance increase over Motorola’s popular DSP56000 core, while retaining code compatibility. Significant architectural enhancements in the DSP56300 family include a barrel shifter, 24-bit addressing, instruction cache, and Direct Memory Access (DMA). The DSP56303 offers 66/80/100 MIPS using an internal 66/80/100 MHz clock at 3.0– ...
Page 2
... TABLE OF CONTENTS 1-800-521-6274 dsphelp@dsp.sps.mot.com http://www.motorola-dsp.com Logic State Signal State True Asserted False Deasserted True Asserted False Deasserted are defined by individual product specifications. OH Preliminary Data DSP56303/D, Rev Voltage MOTOROLA ...
Page 3
... End-of-block-transfer interrupts – Triggering from interrupt lines and all peripherals • Phase Lock Loop (PLL) – Allows change of low power Divide Factor (DF) without loss of lock – Output clock with skew elimination MOTOROLA Preliminary Data DSP56303/D, Rev. 1 DSP56303 Features iii ...
Page 4
... Preliminary Data DSP56303/D, Rev Data RAM Y Data RAM Size Size 2048 24-bit 2048 24-bit 2048 24-bit 2048 24-bit 3072 24-bit 3072 24-bit 3072 24-bit 3072 24-bit MOTOROLA ...
Page 5
... Optimized power management circuitry (instruction-dependent, peripheral- dependent, and mode-dependent) TARGET APPLICATIONS The DSP56303 is intended for use in telecommunication applications, such as multi- line voice/data/fax processing, videoconferencing, audio applications, control, and general digital signal processing. MOTOROLA Preliminary Data DSP56303/D, Rev. 1 DSP56303 Target Applications v ...
Page 6
... A local Motorola distributor • A Motorola semiconductor sales office • A Motorola Literature Distribution Center • The World Wide Web (WWW) See the Additional Support section of the DSP56300 Family Manual for detailed information on the multiple support options available to you ...
Page 7
... Port B signals are the HI08 port signals multiplexed with the GPIO signals. 3. Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals. 4. Port E signals are the SCI port signals multiplexed with the GPIO signals. Figure 1 diagram of DSP56303 signals by functional group. MOTOROLA SECTION 1 1 Port A 2 ...
Page 8
... PB8 HA8 PB9 HA9 PB10 HA10 PB13 Double DS HRD/HRD PB11 HWR/HWR PB12 Double HR HTRQ/HTRQ PB14 HRRQ/HRRQ PB15 Port C GPIO PC0-PC2 PC3 PC4 PC5 Port D GPIO PD0-PD2 PD3 PD4 PD5 Port E GPIO PE0 PE1 PE2 Timer GPIO TIO0 TIO1 TIO2 AA0601 MOTOROLA ...
Page 9
... Note: These designations are package-dependent. Some packages connect all V other internally. On those packages, all power input, except V connections indicated in this table are minimum values; the total V MOTOROLA Table 1-2 Power Inputs Description is V dedicated for Phase Lock Loop (PLL) use. The voltage ...
Page 10
... D connections isolated ground for the bus control I/O drivers isolated ground for the HI08 I/O drivers. This isolated ground for the ESSI, SCI, and S connections. S Preliminary Data DSP56303/D, Rev. 1 should be CCP and P and GND , are P P1 MOTOROLA ...
Page 11
... Input CLKOUT Output Chip-driven PINIT/NMI Input Input MOTOROLA Table 1-4 Clock Signals Signal Description External Clock/Crystal Input—EXTAL interfaces the internal crystal oscillator input to an external crystal or an external clock. Crystal Output—XTAL connects the internal crystal oscillator output to an external crystal external clock is used, leave XTAL unconnected ...
Page 12
... Otherwise tri-stated. Write Enable—When the DSP is the bus master active-low output that is asserted to write external memory on the data bus (D0–D23). Otherwise, the signals are tri-stated. Preliminary Data DSP56303/D, Rev. 1 Signal Description Signal Description MOTOROLA ...
Page 13
... Input Ignored Input BR Output Output (deasserted) MOTOROLA Signal/Connection Descriptions External Memory Expansion Port (Port A) Signal Description Transfer Acknowledge—If the DSP56303 is the bus master and there is no external bus activity, or the DSP56303 is not the bus master, the TA input is ignored. The TA input is a Data Transfer Acknowledge (DTACK) function that can extend an external bus cycle indefinitely ...
Page 14
... When BCLK is active and synchronized to CLKOUT by the internal PLL, BCLK precedes CLKOUT by one-fourth of a clock cycle. Bus Clock Not—When the DSP is the bus master, BCLK is an active-low output and is the inverse of the BCLK signal. Otherwise, the signal is tri-stated. Preliminary Data DSP56303/D, Rev. 1 MOTOROLA ...
Page 15
... Type RESET Input Input MODA/IRQA Input Input MOTOROLA Signal Description Reset Reset—RESET is an active-low, Schmitt-trigger input. Deassertion of RESET is internally synchronized to the clock out (CLKOUT). When asserted, the chip is placed in the Reset state and the internal phase generator is reset. The Schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably ...
Page 16
... OMR when the RESET signal is deasserted. If IRQD is asserted synchronous to CLKOUT, multiple processors can be re- synchronized using the WAIT instruction and asserting IRQD to exit the Wait state. MODD/IRQD can tolerate 5 V. Preliminary Data DSP56303/D, Rev. 1 MOTOROLA ...
Page 17
... Asynchronous write to host The host interface programmer should change the Host Vector (HV) vector register only when the Host Command bit (HC) is clear. This will guarantee that the DSP interrupt control logic will receive a stable vector. MOTOROLA Signal/Connection Descriptions Description Preliminary Data DSP56303/D, Rev. 1 ...
Page 18
... Schmitt-trigger input. The polarity of the address strobe is programmable but is configured active-low (HAS) following reset. Port B 8—When the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. This input tolerant. Preliminary Data DSP56303/D, Rev. 1 Signal Description MOTOROLA ...
Page 19
... Output HRW Input HRD/HRD Input PB11 Input or Output MOTOROLA Signal Description Reset Input Host Address Input 1—When the HI08 is programmed to interface a non-multiplexed host bus and the HI function is selected, this signal is line 1 of the Host Address (HA1) input bus. Host Address 8—When HI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 8 of the Host Address (HA8) input bus ...
Page 20
... HI function is selected, this signal is line 10 of the Host Address (HA10) input bus. Port B 13—When the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR. This input tolerant. Preliminary Data DSP56303/D, Rev. 1 MOTOROLA ...
Page 21
... HACK/HACK Input HRRQ/HRRQ Output PB15 Input or Output MOTOROLA Signal Description Reset Input Host Request—When HI08 is programmed to interface a single host request host bus and the HI function is selected, this signal is the Host Request (HREQ) output. The polarity of the host request is programmable, but is configured as active-low (HREQ) following reset ...
Page 22
... There are two synchronous serial interfaces (ESSI0 and ESSI1) that provide a full- duplex serial port for serial communication with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals which implement the Motorola Serial Peripheral Interface (SPI). Table 1-12 Enhanced Synchronous Serial Interface 0 (ESSI0) Signal Name ...
Page 23
... PC2 Input or Output SCK0 Input/Output PC3 Input or Output MOTOROLA Enhanced Synchronous Serial Interface 0 (ESSI0) State During Reset Input Serial Control Signal 2—SC02 is used for frame sync I/O. SC02 is the frame sync for both the transmitter and receiver in Synchronous mode, and for the transmitter only in Asynchronous mode ...
Page 24
... Port C 5—The default configuration following reset is GPIO input PC5. When configured as PC5, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal STD0 through PCR0. This input tolerant. Preliminary Data DSP56303/D, Rev. 1 Signal Description MOTOROLA ...
Page 25
... Input or Output PD0 SC11 Input/Output PD1 Input or Output MOTOROLA Enhanced Synchronous Serial Interface 1 (ESSI1) State During Reset Input Serial Control 0—The function of SC10 is determined by the selection of either Synchronous or Asynchronous mode. For Asynchronous mode, this signal will be used for the receive clock I/O (Schmitt- trigger input) ...
Page 26
... DSP phases inside each half of the serial clock. Port D 3—The default configuration following reset is GPIO input PD3. When configured as PD3, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SCK1 through PCR1. This input tolerant. Preliminary Data DSP56303/D, Rev. 1 Signal Description MOTOROLA ...
Page 27
... PD4 Input or Output STD1 Input/Output PD5 Input or Output MOTOROLA Enhanced Synchronous Serial Interface 1 (ESSI1) State During Reset Input Serial Receive Data—SRD1 receives serial data and transfers the data to the ESSI receive shift register. SRD1 is an input when data is being received. ...
Page 28
... Port E 2—The default configuration following reset is GPIO input PE2. When configured as PE2, signal direction is controlled through the SCI PRR. The signal can be configured as an SCI signal SCLK through the SCI PCR. This input tolerant. Preliminary Data DSP56303/D, Rev. 1 Signal Description MOTOROLA ...
Page 29
... TIO0 Input or Output TIO1 Input or Output TIO2 Input or Output MOTOROLA Table 1-15 Triple Timer Signals State During Reset Input Timer 0 Schmitt-Trigger Input/Output—When Timer 0 functions as an external event counter or in Measurement mode, TIO0 is used as input. When Timer 0 functions in Watchdog, Timer, or Pulse Modulation mode, TIO0 is used as output. ...
Page 30
... This input tolerant. Input Test Reset—TRST is an active-low Schmitt-trigger input signal used to asynchronously initialize the test controller. TRST has an internal pull-up resistor. TRST must be asserted after power up. This input tolerant. Preliminary Data DSP56303/D, Rev. 1 Signal Description MOTOROLA ...
Page 31
... Table 1-16 JTAG/OnCE Interface (Continued) Signal Name Type DE Input/Output MOTOROLA State During Reset Input Debug Event— open-drain, bidirectional, active-low signal providing input, a means of entering the Debug mode of operation from an external command controller, and output, a means of acknowledging that the chip has entered the Debug mode ...
Page 32
... Signal/Connection Descriptions JTAG/OnCE Interface 1-26 Preliminary Data DSP56303/D, Rev. 1 MOTOROLA ...
Page 33
... Therefore, a “maximum” value for a specification will never occur in the same device that has a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. MOTOROLA SECTION SPECIFICATIONS CAUTION Preliminary Data DSP56303/D, Rev ...
Page 34
... TQFP Symbol Value 6.8 JT Preliminary Data DSP56303/D, Rev Unit Value 0.3 to +4.0 V GND 0 0 GND 0 3. ° +100 C ° +150 PBGA PBGA Unit Value Value ° C/W ° 15 — C/W ° 8 — C/W MOTOROLA ...
Page 35
... TTL (I = 3.0 mA, open-drain pins OL 5 6.7 mA • CMOS ( Internal supply current : • In Normal mode 3 • In Wait mode 4 • In Stop mode PLL supply current in Stop mode 5 Input capacitance MOTOROLA Symbol Min 2.0 IHP V 0.8 V IHX –0 –0.3 ILP V – ...
Page 36
... TTL Loads L or the high V value may cause additional power consumption (DC IHX ILX should be no higher than 0.1 V ILX minimum of 2.4 V for all pins except EXTAL, IH Preliminary Data DSP56303/D, Rev (Continued) Typ Max CC should be no lower than IHX . CC and V OL MOTOROLA Unit = 3.6 OH ...
Page 37
... PLL disabled Instruction cycle time Notes Division Factor Ef = External frequency ET = External clock cycle Multiplication Factor PDF = Predivision Factor T = internal clock cycle C PLL and Clock Generation 2. See the detailed discussion of the PLL. MOTOROLA Expression Symbol Min f — f — T — PDF DF/MF 0.47 ET ...
Page 38
... Calculations were done for a 4/20 MHz crystal with the following parameters 30/20 pF 7/6 pF series resistance of 100/20 a drive level of 2 mW. Figure 2-1 Crystal Oscillator Circuits Preliminary Data DSP56303/D, Rev. 1 EXTAL XTAL R C XTAL1 C Fundamental Frequency Crystal Oscillator MHz OSC 10 680 k 10% 20 20% , and AA1071 MOTOROLA ...
Page 39
... With PLL enabled (42.5%–57.5% duty 6 cycle ) EXTAL input low • With PLL disabled (46.7%–53.3% duty 6 cycle ) • With PLL enabled (42.5%–57.5% duty 6 cycle ) MOTOROLA IHC ILC Figure 2-2 E xternal Clock Timing Table 2-5 Clock Operation 66 MHz Symbol Min Max ...
Page 40
... C 15.15 ns 273.1 s 12.50 ns 273.1 s 4.3 ns 11.0 ns 4.3 ns 0.0 ns 1.8 ns 0.0 ns 0.0 ns 1.8 ns 0.0 ns 0.0 ns 1 CYC 30.3 ns 25.0 ns 15.15 ns 8.53 s 12. Preliminary Data DSP56303/D, Rev MHz 100 MHz Max Min Max 10.00 ns 10.00 ns 273.1 s 11.0 ns 4.3 ns 11.0 ns 1.8 ns 0.0 ns 1.8 ns 1.8 ns 0.0 ns 1.8 ns 1.8 ns 0.0 ns 1.8 ns 20.0 ns 8.53 s 10.00 ns 8.53 s and maximum MF. and maximum DF. MOTOROLA ...
Page 41
... PLL capacitor (connected between the PCAP pin and V PCAP value in pF for C can be computed from one of the following equations: PCAP (500 MF) – 150, for 690 MF, for MF > 4. MOTOROLA Phase Lock Loop (PLL) Characteristics Table 2-6 PLL Characteristics 80 MHz Max Min Max ...
Page 42
... Min Max — 26.0 — 26.0 ns 625.0 — 500.0 — ns 12.5 — 10.0 — s 1.0 — 0.75 — ms 1.0 — 0.75 — ms 31.3 — 25.0 — ns 31.3 — 25.0 — ns — — — — ns 42.6 — — — ns — — 34.5 — ns — — — — ns — 263.1 — — ns — — — 211.5 ns MOTOROLA ...
Page 43
... Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external memory access address out valid • Caused by first interrupt instruction fetch • Caused by first interrupt instruction execution MOTOROLA Reset, Stop, Mode Select, and Interrupt Timing 66 MHz Expression Min Max 9.0 — T — 15 1.0 50.0 — ...
Page 44
... WS T – – — – – Preliminary Data DSP56303/D, Rev (Continued) 80 MHz 100 MHz Unit Min Max Min Max 130.0 — 105.0 — — ns — — ns — ns MOTOROLA ...
Page 45
... SRAM MHz (WS + 2.5) 80 MHz (WS + 2.5) 100 MHz ( Synchronous interrupt setup time from IRQA, IRQB, IRQC, IRQD, NMI assertion to the CLKOUT Transition 2 MOTOROLA Reset, Stop, Mode Select, and Interrupt Timing 66 MHz Expression Min Max – 14 — – 12.4 ...
Page 46
... ET PDF + 2.0 64.1 C PLC/ PDF + 352.3 62 0.5) T 117.4 132.6 C Preliminary Data DSP56303/D, Rev (Continued) 80 MHz 100 MHz Unit Min Max Min Max 116.6 — 93.5 — ns — 314.4 — 252.5 ns 7.4 — 5.9 — ns 1.6 17.0 1.3 13.6 ms 290.6 15.4 232.5 12 96.9 109.4 77.5 87.5 ns MOTOROLA ...
Page 47
... IRQ, NMI (level trigger) 28 DMA Requests Rate • Data read from HI08, ESSI, SCI • Data write to HI08, ESSI, SCI • Timer • IRQ, NMI (edge trigger) MOTOROLA Reset, Stop, Mode Select, and Interrupt Timing 66 MHz Expression Min Max ET PDF + 64.1 — C PLC/ ...
Page 48
... Periodically sampled and not 100% tested 2-16 66 MHz Expression Min Max 4. 2.0 66.0 — 4096 (maximum MF) divided by the desired internal frequency (i.e., for C Preliminary Data DSP56303/D, Rev (Continued) 80 MHz 100 MHz Unit Min Max Min Max 55.1 — 44.0 — and T will not be constant MOTOROLA ...
Page 49
... Use expression to compute maximum value. RESET 8 All Pins A0–A17 CLKOUT 11 RESET A0–A17 Figure 2-4 Synchronous Reset Timing MOTOROLA Reset, Stop, Mode Select, and Interrupt Timing 66 MHz Expression Min Max = –40°C to +100° TTL Loads L 9 Reset Value Figure 2-3 Reset Timing ...
Page 50
... Figure 2-5 External Fast Interrupt Timing IRQA, IRQB, IRQC, IRQD, NMI IRQA, IRQB, IRQC, IRQD, NMI Figure 2-6 External Interrupt Timing (Negative Edge-Triggered) 2-18 First Interrupt Instruction Execution/Fetch First Interrupt Instruction Execution 18 b) General Purpose I Preliminary Data DSP56303/D, Rev. 1 AA0462 AA0463 MOTOROLA ...
Page 51
... A0–A17 Figure 2-7 Synchronous Interrupt from Wait State Timing RESET MODA, MODB, MODC, MODD, PINIT Figure 2-8 Operating Mode Select Timing IRQA A0–A17 Figure 2-9 Recovery from Stop State Using IRQA MOTOROLA Reset, Stop, Mode Select, and Interrupt Timing Preliminary Data DSP56303/D, Rev ...
Page 52
... Figure 2-10 Recovery from Stop State Using IRQA Interrupt Service A0–A17 RD WR IRQA, IRQB, IRQC, IRQD, NMI Figure 2-11 External Memory Access (DMA Source) Timing 2- DMA Source Address 29 First Interrupt Instruction Execution Preliminary Data DSP56303/D, Rev. 1 First IRQA Interrupt Instruction Fetch AA0467 AA1104 MOTOROLA ...
Page 53
... Symbol 100 Address valid and AA assertion pulse width 101 Address and valid to WR assertion 102 WR assertion t WP pulse width MOTOROLA External Memory Expansion Port (Port A) 66 MHz 1 Expression Min Max Min Max Min Max ( 4 4.0 86 ...
Page 54
... MOTOROLA Unit ...
Page 55
... Data hold time t DH from WR deassertion 110 WR assertion to data active 111 WR deassertion to data high impedance 112 Previous RD deassertion to data active (write) MOTOROLA External Memory Expansion Port (Port A) 66 MHz 1 Expression Min Max Min Max Min Max (WS 0.25) T 3.9 7 MHz: (WS 0.25 ...
Page 56
... MOTOROLA ...
Page 57
... A0–A17 AA0–AA3 RD WR D0–D23 A0–A17 AA0–AA3 WR RD D0–D23 MOTOROLA External Memory Expansion Port (Port A) 100 113 116 115 105 104 Figure 2-12 SRAM Read Access 100 107 101 102 114 108 110 112 Figure 2-13 SRAM Write Access Preliminary Data DSP56303/D, Rev. 1 ...
Page 58
... Figure 2-14 DRAM Page Mode Wait States Selection Guide 2-26 Note: This figure should be use for primary selection. For exact and detailed timings see the following tables. 120 66 80 100 3 Wait States 4 Wait States Preliminary Data DSP56303/D, Rev. 1 Chip Frequency (MHz) AA0472 MOTOROLA ...
Page 59
... RAS deassertion 143 WR deassertion to CAS assertion 144 CAS deassertion to WR assertion 145 CAS assertion to WR deassertion h 146 WR assertion pulse widt 147 Last WR assertion to RAS deassertion MOTOROLA External Memory Expansion Port (Port A) 20 MHz Symbol Expression Min t 1. 7.5 — CAC ...
Page 60
... T 4.0 71.0 ROH 7.5 — 0.0 GZ 0.75 T 0.3 37.2 C 0.25 T — C Preliminary Data DSP56303/D, Rev MHz Unit Max Min Max — 54.0 — ns — 4.3 — ns — 21.0 — ns — 29.0 — ns — 46.0 — ns 42.5 — 25.8 ns — 0.0 — ns — 24.7 — ns 12.5 — 8.3 ns and not OFF Figure 2-14 ). MOTOROLA ...
Page 61
... CAS assertion to column address not valid 142 Last column address valid to RAS deassertion 143 WR deassertion to CAS assertion 144 CAS deassertion to WR assertion 145 CAS assertion to WR deassertion 146 WR assertion pulse width MOTOROLA External Memory Expansion Port (Port A) Symbol Expression t 2. MHz: CAC 1 ...
Page 62
... MHz 80 MHz Unit Min Max Min Max 37.4 — 30.1 — ns 33.6 — 27.0 — ns 0.1 — — — ns — — 0.1 — ns 22.5 — 17.9 — ns 10.9 — 8.2 — ns 33.9 — 27.3 — ns — 19.0 — — ns — — — 15.4 ns 0.0 — 0.0 — ns 11.1 — 9.1 — ns — 3.8 — 3.1 ns and not OFF MOTOROLA ...
Page 63
... Column address valid to CAS assertion 141 CAS assertion to column address not valid 142 Last column address valid to RAS deassertion 143 WR deassertion to CAS assertion 144 CAS deassertion to WR assertion MOTOROLA External Memory Expansion Port (Port A) 66 MHz Symbol Expression Min Max Min Max Min Max t 3.5 T 53.0 ...
Page 64
... OFF MOTOROLA ...
Page 65
... CAS assertion 141 CAS assertion to column address not valid 142 Last column address valid to RAS deassertion 143 WR deassertion to CAS assertion 144 CAS deassertion to WR assertion MOTOROLA External Memory Expansion Port (Port A) 66 MHz Symbol Expression Min Max Min Max Min Max t 4 ...
Page 66
... OFF MOTOROLA ...
Page 67
... RAS CAS Row A0–A17 Add WR RD D0–D23 Figure 2-15 DRAM Page Mode Write Accesses MOTOROLA External Memory Expansion Port (Port A) 131 137 139 140 141 Column Column Address Address 151 144 145 146 155 150 149 Data Out Data Out Preliminary Data DSP56303/D, Rev ...
Page 68
... Add WR RD D0–D23 Figure 2-16 DRAM Page Mode Read Accesses 2-36 131 137 139 140 141 Column Column Address Address 143 133 153 Data In Data In Preliminary Data DSP56303/D, Rev. 1 136 135 138 142 Last Column Address 132 152 134 154 Data In AA0474 MOTOROLA ...
Page 69
... Column address valid to data valid (read) 161 CAS deassertion to data not valid (read hold time) MOTOROLA External Memory Expansion Port (Port A) Note: This figure should be use for primary selection. For exact and detailed timings see the following tables ...
Page 70
... MHz Unit Max Min Max — 54.3 — ns — 104.3 — ns — 54.3 — ns — 87.7 — ns — 37.7 — ns 77.0 48.0 52.0 ns 64.5 39.7 43.7 ns — 71.0 — ns — 54.3 — ns — 54.3 — ns — 37.7 — ns — 4.3 — ns — 54.3 — ns — 104.3 — ns — 62.7 — ns — 46.2 — ns — 21.3 — ns — 4.6 — ns MOTOROLA ...
Page 71
... RD deassertion will always occur after CAS deassertion; therefore, the restricted timing Reduced DSP clock speed allows use of DRAM out-of-page access with four Wait states (see Figure 2-17 ). MOTOROLA External Memory Expansion Port (Port A) 20 MHz Symbol Expression Min t 1.5 T 4.2 70 ...
Page 72
... MOTOROLA ...
Page 73
... WR assertion to CAS deassertion 185 Data valid to CAS assertion (write) 186 CAS assertion to data not valid (write) 187 RAS assertion to data not valid (write) MOTOROLA External Memory Expansion Port (Port A) 66 MHz 3 Symbol Expression Min Max Min Max Min Max t 3. ...
Page 74
... OFF MOTOROLA ...
Page 75
... CAS assertion pulse width 167 RAS assertion to CAS assertion 168 RAS assertion to column address valid 169 CAS deassertion to RAS assertion 170 CAS deassertion pulse width MOTOROLA External Memory Expansion Port (Port A) 66 MHz 3 Symbol Expression Min Max Min Max Min Max 181 ...
Page 76
... MOTOROLA ...
Page 77
... The asynchronous delays specified in the expressions are valid for DSP56303 deassertion will always occur after CAS deassertion; therefore, the restricted timing Either must be satisfied for read cycles. RCH RRH MOTOROLA External Memory Expansion Port (Port A) 66 MHz 3 Symbol Expression Min Max Min Max Min Max t 6.5 T 4.3 94.2 ...
Page 78
... MOTOROLA ...
Page 79
... WR assertion pulse width 183 WR assertion to RAS deassertion 184 WR assertion to CAS deassertion 185 Data valid to CAS assertion (write) 186 CAS assertion to data not valid (write) MOTOROLA External Memory Expansion Port (Port A) 66 MHz Symbol Expression Min Max Min Max Min Max t 6.25 T 4.0 90 ...
Page 80
... OFF MOTOROLA ...
Page 81
... RAS 169 CAS A0–A17 WR RD D0–D23 Figure 2-18 DRAM Out-of-Page Read Access MOTOROLA External Memory Expansion Port (Port A) 157 163 165 167 164 168 170 166 171 173 175 Row Address Column Address 172 176 177 191 160 159 158 ...
Page 82
... Figure 2-19 DRAM Out-of-Page Write Access 2-50 157 162 163 165 167 168 166 170 171 173 172 176 Row Address Column Address 181 175 188 182 184 183 187 185 194 Data Out Preliminary Data DSP56303/D, Rev. 1 162 164 174 180 186 195 AA0477 MOTOROLA ...
Page 83
... RAS 190 170 CAS 177 WR MOTOROLA External Memory Expansion Port (Port A) 157 163 162 165 189 Figure 2-20 DRAM Refresh Access Preliminary Data DSP56303/D, Rev. 1 Specifications 162 AA0478 2-51 ...
Page 84
... MOTOROLA ...
Page 85
... T198 and T199 are valid for Address Trace mode if the ATE bit in the OMR is set. Use the status of BR (See T212) to determine whether the access referenced by A0–A23 is internal or external, when this mode is enabled MOTOROLA External Memory Expansion Port (Port A) 66 MHz ...
Page 86
... External Memory Expansion Port (Port A) CLKOUT A0–A17 AA0–AA3 TA WR D0–D23 RD D0–D23 Figure 2-21 Synchronous Bus Timings SRAM 1 WS (BCR Controlled) 2-54 198 210 203 Data Out 202 208 206 Preliminary Data DSP56303/D, Rev. 1 199 201 200 211 205 204 209 207 Data In AA0479 MOTOROLA ...
Page 87
... CLKOUT 198 A0–A17 AA0–AA3 TA WR 210 D0–D23 208 RD D0–D23 Figure 2-22 Synchronous Bus Timings SRAM 2 WS (TA Controlled) MOTOROLA External Memory Expansion Port (Port A) 201 200 203 Data Out 202 206 Preliminary Data DSP56303/D, Rev. 1 Specifications 199 201 200 211 205 ...
Page 88
... MOTOROLA ...
Page 89
... CLKOUT 212 A0–A17 RD, WR AA0–AA3 MOTOROLA External Memory Expansion Port (Port A) 213 215 Figure 2-23 Bus Acquisition Timings Preliminary Data DSP56303/D, Rev. 1 Specifications 214 216 217 220 222 AA0481 2-57 ...
Page 90
... Specifications External Memory Expansion Port (Port A) CLKOUT 212 A0–A17 RD, WR AA0–AA3 Figure 2-24 Bus Release Timings Case 1 (BRT Bit in OMR Cleared) 2-58 214 213 218 221 224 223 Preliminary Data DSP56303/D, Rev. 1 219 AA0482 MOTOROLA ...
Page 91
... CLKOUT 212 A0–A17 RD, WR AA0–AA3 Figure 2-25 Bus Release Timings Case 2 (BRT Bit in OMR Set) MOTOROLA External Memory Expansion Port (Port A) 214 213 221 224 223 Preliminary Data DSP56303/D, Rev. 1 Specifications 219 218 AA0483 2-59 ...
Page 92
... MOTOROLA ...
Page 93
... A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W hold time after data strobe 4 deassertion 338 Delay from read data strobe deassertion to host request assertion for “Last Data Register” read MOTOROLA 1, 2 (Continued) 66 MHz Expression Min Max Min Max Min Max — 15.0 5.0 — ...
Page 94
... TTL loads L Preliminary Data DSP56303/D, Rev. 1 (Continued) 80 MHz 100 MHz — — — — — — 39.4 — — — — — — 31.5 — 25.0 — 22.55 — 20.24 300.0 — 300.0 — 300.0 MOTOROLA Unit ...
Page 95
... HACK HD7–HD0 HREQ Figure 2-26 Host Interrupt Vector Register (IVR) Read Timing Diagram HA0–HA7 HCS HRD, HDS HD0–HD7 HREQ, HRRQ, HTRQ Figure 2-27 Read Timing Diagram, Non-Multiplexed Bus MOTOROLA 317 327 329 326 336 337 330 300 317 318 328 ...
Page 96
... Specifications Host Interface Timing HA0–HA7 HWR, HDS HD0–HD7 HREQ, HRRQ, HTRQ Figure 2-28 Write Timing Diagram, Non-Multiplexed Bus 2-64 336 331 HCS 300 320 324 340 341 Preliminary Data DSP56303/D, Rev. 1 337 333 321 325 339 AA0485 MOTOROLA ...
Page 97
... HA8–HA10 HAS HRD, HDS HAD0–HAD7 HREQ, HRRQ, HTRQ Figure 2-29 Read Timing Diagram, Multiplexed Bus MOTOROLA 336 322 323 300 317 334 335 327 329 Address 326 340 341 Preliminary Data DSP56303/D, Rev. 1 Specifications Host Interface Timing 337 318 319 ...
Page 98
... Specifications Host Interface Timing HA8–HA10 322 HAS HWR, HDS 334 HAD0–HAD7 HREQ, HRRQ, HTRQ Figure 2-30 Write Timing Diagram, Multiplexed Bus 2-66 336 323 300 320 324 335 Data Address 340 341 Preliminary Data DSP56303/D, Rev. 1 321 325 339 AA0487 MOTOROLA ...
Page 99
... Input data hold time after clock rising edge (external clock) 411 Asynchronous clock t ACC cycle 412 Clock low period 413 Clock high period MOTOROLA Table 2-20 SCI Timing 66 MHz Expression Min Max Min Max Min Max 121 ...
Page 100
... ACC t /2 30.0 458.8 ACC = 40°C to +100 ° TTL Loads L SCC .) C Preliminary Data DSP56303/D, Rev MHz 100 MHz — 370.0 — 290.0 — — 370.0 — 290.0 — is determined by the SCI clock control is ACC MOTOROLA Unit ns ns ...
Page 101
... SCLK (Output) 403 TXD RXD SCLK (Input) 407 TXD RXD Figure 2-31 SCI Synchronous Mode Timing 1X SCLK (Output) TXD Figure 2-32 SCI Asynchronous Mode Timing MOTOROLA 400 402 401 404 Data Valid 405 406 Data Valid a) Internal Clock 400 402 401 408 Data Valid ...
Page 102
... MOTOROLA ...
Page 103
... FST input (bl, wr) setup time before TXC falling 2 edge 458 FST input (wl) to data out enable from high impedance 459 FST input (wl) to Transmitter #0 drive enable assertion MOTOROLA 66 MHz 80 MHz Expression Min Max Min Max Min Max 6.0 — 6.0 0.0 — 0.0 — ...
Page 104
... TTL Loads L Preliminary Data DSP56303/D, Rev MHz 100 MHz Cond- Unit 5 ition 2.0 — 2.0 — 21.0 — 21.0 — 4.0 — 4.0 — 0.0 — 0.0 — — 32.0 — 32 — 18.0 — 18 MOTOROLA ...
Page 105
... Flags Out Note: In Network mode, output flag transitions can occur at the start of each time slot within the frame. In Normal mode, the output flag state is asserted for the entire frame period. Figure 2-33 ESSI Transmitter Timing MOTOROLA 430 432 446 447 450 454 ...
Page 106
... FSR (Bit) Out FSR (Word) Out Data In 441 FSR (Bit) In FSR (Word) In Flags In 2-74 430 431 432 433 434 437 439 First Bit 443 442 444 Figure 2-34 ESSI Receiver Timing Preliminary Data DSP56303/D, Rev. 1 438 440 Last Bit 443 445 AA0491 MOTOROLA ...
Page 107
... Maximum 485 CLKOUT rising edge to TIO (Output) deassertion • Minimum • Maximum Note 3 40°C to +100 ° TIO Figure 2-35 TIO Timer Event Input Restrictions MOTOROLA Table 2-22 Timer Timing 66 MHz Expression Min Max Min Max Min Max 2.0 32 2.0 32.5 C 9.0 15 ...
Page 108
... Specifications Timer Timing CLKOUT TIO (Input) Address Figure 2-36 Timer Interrupt Generation CLKOUT TIO (Output) Figure 2-37 External Pulse Generation 2-76 482 483 First Interrupt Instruction Execution 484 Preliminary Data DSP56303/D, Rev. 1 AA0493 485 AA0494 MOTOROLA ...
Page 109
... CC J CLKOUT (Output) GPIO (Output) 492 GPIO (Input) A0–A17 Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO and R0 contains the address of GPIO data register. MOTOROLA Table 2-23 GPIO Timing 66 MHz Expression Min Max Min Max Min Max — 31.0 3.0 — 12.0 — 0.0 — ...
Page 110
... MHz 40°C to +100 ° TTL Loads L 501 502 Preliminary Data DSP56303/D, Rev. 1 All frequencies Unit Min Max 0.0 22.0 MHz 45.0 — ns 20.0 — ns 0.0 3.0 ns 5.0 — ns 24.0 — ns 0.0 40.0 ns 0.0 40.0 ns 5.0 — ns 25.0 — ns 0.0 44.0 ns 0.0 44.0 ns 100.0 — ns 40.0 — ns 502 V M 503 AA0496 MOTOROLA ...
Page 111
... TCK V (Input) IL TDI TMS (Input) TDO (Output) TDO (Output) TDO (Output) Figure 2-41 Test Access Port Timing Diagram MOTOROLA 504 Input Data Valid 506 Output Data Valid 507 506 Output Data Valid 508 Input Data Valid 510 Output Data Valid 511 510 ...
Page 112
... MHz Expression Min Max Min Max Min Max 1/(T 3), 0.0 C max 22.0 MHz 1 10.0 32 30.0 — 10.0 55 TTL Loads L 515 Preliminary Data DSP56303/D, Rev. 1 AA0499 80 MHz 100 MHz Unit 22.0 0.0 22.0 0.0 22.0 MHz — 28.8 — 25.0 — ns 113.3 — 98.8 — 85.0 ns — 47.5 — 40.0 — ns 516 AA0500 MOTOROLA ...
Page 113
... Section 1 are allocated for each package. The DSP56303 is available in two package types: • 144-pin Thin Quad Flat Pack (TQFP) • 196-pin Plastic Ball Grid Array (PBGA) MOTOROLA SECTION 3 PACKAGING Preliminary Data DSP56303/D, Rev ...
Page 114
... View) Preliminary Data DSP56303/D, Rev AA0 AA1 RD WR GND C V CCC BCLK BCLK CLKOUT GND C V CCC V CCQ EXTAL GND Q XTAL CAS AA2 AA3 NC GND P1 GND P PCAP V CCP RESET HAD0 HAD1 HAD2 HAD3 GND H V CCH HAD4 37 AA0301 MOTOROLA ...
Page 115
... Because of size constraints in this figure, only one name is shown for multiplexed pins. Refer to Table 3-1 and Table 3-2 for detailed information about pin functions and signal names. Figure 3-2 DSP56303 Thin Quad Flat Pack (TQFP), Bottom View MOTOROLA Pin-out and Package Information (Bottom View) ...
Page 116
... Preliminary Data DSP56303/D, Rev. 1 Pin Signal Name No. 51 AA2/RAS2 52 CAS 53 XTAL 54 GND Q 55 EXTAL 56 V CCQ 57 V CCC 58 GND C 59 CLKOUT 60 BCLK 61 BCLK CCC 66 GND AA1/RAS1 70 AA0/RAS0 CCA 75 GND A MOTOROLA ...
Page 117
... Some pins have two or more configurable functions; names assigned to these pins indicate the function for a specific configuration. For example, Pin 34 is data line H7 in non-multiplexed bus mode, data/address line HAD7 in multiplexed bus mode, or GPIO line PB7 when the GPIO function is enabled for this pin. MOTOROLA Pin Signal Name No. ...
Page 118
... EXTAL 55 GND 75 A GND 81 A GND 87 A GND 96 A GND 58 C GND 66 C GND 104 D GND 112 D GND 120 D GND 130 D GND 39 H GND 47 P GND 48 P1 GND 19 Q GND 54 Q GND 90 Q GND 127 Q GND 9 S GND MOTOROLA ...
Page 119
... HA8 32 HA9 31 HACK/HACK 23 HAD0 43 HAD1 42 HAD2 41 HAD3 40 HAD4 37 HAD5 36 HAD6 35 HAD7 34 HAS 33 HCS/HCS 30 HDS/HDS 21 MOTOROLA Pin-out and Package Information Pin Signal Name No. HRD/HRD 22 HREQ/HREQ 24 HRRQ/HRRQ 23 HRW 22 HTRQ/HTRQ 24 HWR/HWR 21 IRQA 137 IRQB 136 IRQC 135 IRQD 134 MODA 137 MODB 136 MODC ...
Page 120
... CCA V 95 CCA Preliminary Data DSP56303/D, Rev. 1 Pin Signal Name No CCC V 65 CCC V 103 CCD V 111 CCD V 119 CCD V 129 CCD V 38 CCH V 45 CCP V 18 CCQ V 56 CCQ V 91 CCQ V 126 CCQ V 8 CCS V 25 CCS WR 67 XTAL 53 MOTOROLA ...
Page 121
... IDENT PLATING BASE D METAL 0. SECTION J1-J1 (ROTATED 90) 144 PL Figure 3-3 DSP56303 Mechanical Information, 144-pin TQFP Package MOTOROLA 0. TIPS 109 108 VIEW VIEW AB 0.1 T 144X 2 SEATING PLANE — 0. ...
Page 122
... GND GND A17 A16 D0 GND GND V A14 A15 CCA GND GND A13 V A12 CCQ GND GND V A10 A11 CCA GND GND GND GND CCA GND GND CCA BCLK BCLK BR V AA0 A0 CCC TA BB AA1 BG NC MOTOROLA ...
Page 123
... A3 V GND GND CCA BCLK A0 AA0 V BR BCLK CCC NC BG AA1 BB TA Figure 3-5 DSP56303 Plastic Ball Grid Array (PBGA), Bottom View MOTOROLA Bottom View D16 D19 V D23 CCD D15 D17 D20 D21 V D18 V D22 CCD CCQ GND ...
Page 124
... No. D9 GND D10 GND D11 GND D12 D1 D13 D2 D14 V CCD E1 STD0 or PC5 E2 V CCS E3 SRD0 or PC4 E4 GND E5 GND E6 GND E7 GND E8 GND E9 GND E10 GND E11 GND E12 A17 E13 A16 E14 D0 F1 RXD or PE0 F2 SC10 or PD0 F3 SC00 or PC0 F4 GND F5 GND MOTOROLA ...
Page 125
... GND G5 GND G6 GND G7 GND G8 GND G9 GND G10 GND G11 GND G12 A13 G13 V CCQ G14 A12 CCQ MOTOROLA Pin Signal Name No. H3 SCK0 or PC3 H4 GND H5 GND H6 GND H7 GND H8 GND H9 GND H10 GND H11 GND H12 V CCA H13 A10 H14 ...
Page 126
... AA0/RAS0 N14 A0 and GND P Preliminary Data DSP56303/D, Rev. 1 (Continued) Pin Signal Name No H5, HAD5, or PB5 P3 H3, HAD3, or PB3 P4 H1, HAD1, or PB1 P5 PCAP P6 GND P1 P7 AA2/RAS2 P8 XTAL P9 V CCC P10 TA P11 BB P12 AA1/RAS1 P13 BG P14 NC that support the PLL, other P1 MOTOROLA ...
Page 127
... A5 K13 A6 K14 A7 J13 A8 J12 A9 J14 AA0 N13 AA1 P12 AA2 P7 AA3 N7 BB P11 BCLK M10 BCLK N10 MOTOROLA Pin-out and Package Information Pin Signal Name No. BG P13 BR N11 CAS N8 CLKOUT M9 D0 E14 D1 D12 D10 B11 D11 A11 D12 C10 D13 B10 ...
Page 128
... GND N6 P GND Preliminary Data DSP56303/D, Rev. 1 Pin Signal Name No HA0 M3 HA1 M1 HA10 L1 HA2 M2 HA8 M1 HA9 M2 HACK/HACK J1 HAD0 M5 HAD1 P4 HAD2 N4 HAD3 P3 HAD4 N3 HAD5 P2 HAD6 N1 HAD7 N2 HAS/HAS M3 HCS/HCS L1 HDS/HDS J3 HRD/HRD J2 HREQ/HREQ K2 HRRQ/HRRQ J1 MOTOROLA ...
Page 129
... MODB A5 MODC C5 MODD A14 NC B14 P14 NMI D1 PB0 M5 PB1 P4 PB10 M2 PB11 J2 PB12 J3 PB13 L1 MOTOROLA Pin-out and Package Information Pin Signal Name No. PB14 K2 PB15 J1 PB2 N4 PB3 P3 PB4 N3 PB5 P2 PB6 N1 PB7 N2 PB8 M3 PB9 M1 PC0 F3 PC1 D2 PC2 C1 PC3 H3 PC4 ...
Page 130
... CCA V L12 CCA V N12 CCC V P9 CCC V A7 CCD V C9 CCD V C11 CCD V D14 CCD V M4 CCH Preliminary Data DSP56303/D, Rev. 1 Pin Signal Name No CCP V C7 CCQ V G13 CCQ V H2 CCQ V N9 CCQ V E2 CCS V K1 CCS WR M11 XTAL P8 MOTOROLA ...
Page 131
... 196X 0 0.1 C BOTTOM VIEW Figure 3-6 DSP56303 Mechanical Information, 196-pin PBGA Package MOTOROLA 0 13X SIDE VIEW CASE 1128-01 ISSUE B Preliminary Data DSP56303/D, Rev. 1 Packaging ...
Page 132
... Ordering Drawings ORDERING DRAWINGS Complete mechanical information regarding DSP56303 packaging is available by facsimile through Motorola's Mfax system. Call the following number to obtain information by facsimile: The Mfax automated system requests the following information: • The receiving facsimile telephone number including area code or country code • ...
Page 133
... For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. MOTOROLA SECTION + P R ...
Page 134
... The recommended technique is to attach a 40- gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. 4 determined by a thermocouple )/P . This value gives a better estimate of the Preliminary Data DSP56303/D, Rev. 1 MOTOROLA ...
Page 135
... The following pins must be asserted after power-up: RESET and TRST. • If multiple DSP56303 devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices. MOTOROLA CAUTION ). CC and GND pins are less than 0.5 in per capacitor lead. ...
Page 136
... Minimize the capacitive load on the pins. • Connect the unused inputs to pull-up or pull-down resistors. • Disable unused peripherals. 4-4 never exceeds 3 Example 4-1 Current Consumption – 3 5.48 mA max) value reflects the typical possible CCI Preliminary Data DSP56303/D, Rev value CCItyp MOTOROLA ...
Page 137
... As defined in Figure 2-2 on page 2-7, for input frequencies greater than 15 MHz and the MF 4, this skew is greater than or equal to 0.0 ns and less than 1.8 ns; otherwise, this skew is not guaranteed. However, for MF < 10 and input frequencies greater than 10 MHz, this skew is between 1.4 ns and +3.2 ns. MOTOROLA I MHz = I – ...
Page 138
... The phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed values. 4-6 Preliminary Data DSP56303/D, Rev. 1 MOTOROLA ...
Page 139
... Voltage Thin Quad Flat Pack (TQFP) DSP56303 3 V Plastic Ball Grid Array (PBGA) MOTOROLA SECTION Table 5-1 Ordering Information Package Type Pin Count 144 196 Preliminary Data DSP56303/D, Rev Frequency Order Number (MHz) 66 XC56303PV66 80 XC56303PV80 100 XC56303PV100 66 XC56303GC66 80 XC56303GC80 100 XC56303GC100 5-1 ...
Page 140
... Ordering Information 5-2 Preliminary Data DSP56303/D, Rev. 1 MOTOROLA ...
Page 141
... Load the program ; move move do move move nop MOTOROLA APPENDIX A 200,55,0,0,0 ; Interrupt vectors for program debug only ; MAIN (external) program starting address ; INTERNAL X-data memory starting address ; INTERNAL Y-data memory starting address P:START #$0d0000,x:M_PCTL ; PLL enable ; CLKOUT disable #INT_PROG,r0 ...
Page 142
... PROG_END nop nop A-2 #INT_XDAT,r0 #XDAT_START,r1 #(XDAT_END-XDAT_START),XLOAD_LOOP p:(r1)+,x0 x0,x:(r0)+ #INT_YDAT,r0 #YDAT_START,r1 #(YDAT_END-YDAT_START),YLOAD_LOOP p:(r1)+,x0 x0,y:(r0)+ INT_PROG #$0,r0 #$0,r4 #$3f,m0 #$3f, #$0,x0 #$0,x1 #$0,y0 #$0,y1 #4,omr ; ebd #60,_end x0,y0,a x:(r0)+,x1 x1,y1,a x:(r0)+,x0 a,b x0,y0,a x:(r0)+,x1 x1,y1,a b1,x:$ff sbr Preliminary Data DSP56303/D, Rev. 1 y:(r4)+,y1 y:(r4)+,y0 y:(r4)+,y0 MOTOROLA ...
Page 143
... MOTOROLA x:0 $262EB9 $86F2FE $E56A5F $616CAC $8FFD75 $9210A $A06D7B $CEA798 $8DFBF1 $A063D6 $6C6657 $C2A544 $A3662D $A4E762 $84F0F3 $E6F1B0 $B3829 $8BF7AE $63A94F $EF78DC $242DE5 $A3E0BA $EBAB6B $8726C8 $CA361 $2F6E86 ...
Page 144
... Preliminary Data DSP56303/D, Rev. 1 MOTOROLA ...
Page 145
... EQUATES for DSP56303 I/O registers and ports ; ; Last update: June 11 1995 ; ;*********************************************************************** *** page opt ioequ ident ;----------------------------------------------------------------------- - ; ; EQUATES for I/O Port Programming ; MOTOROLA $48AC48 $EF7AE1 $6E3006 $62F6C7 $6064F4 $87E41D $CB2692 $2C3863 $C6BC60 $43A519 $6139DE $ADF7BF $4B3E8C $6079D5 $E0F5EA $8230DB $A3B778 $2BFE51 $E0A6B6 $68FFB7 ...
Page 146
... Host Transmit Register ; Host Receive interrupts Enable ; Host Transmit Interrupt Enable ; Host Command Interrupt Enable ; Host Flag 2 ; Host Flag 3 ; Host Receive Data Full ; Host Receive Data Emptiy ; Host Command Pending ; Host Flag 0 ; Host Flag 1 ; Host Port GPIO Enable Preliminary Data DSP56303/D, Rev. 1 MOTOROLA ...
Page 147
... M_WAKE EQU 5 M_RWU EQU 6 M_WOMS EQU 7 M_SCRE EQU 8 M_SCTE EQU 9 M_ILIE EQU 10 M_SCRIE EQU 11 M_SCTIE EQU 12 MOTOROLA Power Consumption Benchmark ; Host Address 8 Enable ; Host Address 9 Enable ; Host Chip Select Enable ; Host Request Enable ; Host Acknowledge Enable ; Host Enable ; Host Request Open Drain mode ...
Page 148
... SSI0 Transmit Slot Mask Register A ; SSI0 Transmit Slot Mask Register B ; SSI0 Receive Slot Mask Register A ; SSI0 Receive Slot Mask Register B ; SSI1 Transmit Data Register 0 ; SSI1 Transmit Data Register 1 ; SSI1 Transmit Data Register 2 ; SSI1 Time Slot Register Preliminary Data DSP56303/D, Rev. 1 MOTOROLA ...
Page 149
... M_SRLIE EQU 21 M_STEIE EQU 22 M_SREIE EQU 23 ; SSI Status Register Bit Flags M_IF EQU $3 M_IF0 EQU 0 MOTOROLA Power Consumption Benchmark ; SSI1 Receive Data Register ; SSI1 Status Register ; SSI1 Control Register B ; SSI1 Control Register A ; SSI1 Transmit Slot Mask Register A ; SSI1 Transmit Slot Mask Register B ...
Page 150
... IRQA Mode Trigger Mode ; IRQB Mode Mask ; IRQB Mode Interrupt Priority Level (low) ; IRQB Mode Interrupt Priority Level (high) ; IRQB Mode Trigger Mode ; IRQC Mode Mask ; IRQC Mode Interrupt Priority Level (low) ; IRQC Mode Interrupt Priority Level (high) Preliminary Data DSP56303/D, Rev. 1 MOTOROLA ...
Page 151
... EQUATES for TIMER ; ;----------------------------------------------------------------------- - ; Register Addresses Of TIMER0 MOTOROLA Power Consumption Benchmark ; IRQC Mode Trigger Mode ; IRQD Mode Mask ; IRQD Mode Interrupt Priority Level (low) ; IRQD Mode Interrupt Priority Level (high) ; IRQD Mode Trigger Mode ; DMA0 Interrupt priority Level Mask ; DMA0 Interrupt Priority Level (low) ...
Page 152
... Timer Compare Interrupt Enable ; Timer Control Mask (TC0-TC3) ; Inverter Bit ; Timer Restart Mode ; Direction Bit ; Data Input ; Data Output ; Prescaled Clock Enable ; Timer Overflow Flag ; Timer Compare Flag ; Prescaler Source Mask ; Timer Control 0 ; Timer Control 1 ; Timer Control 2 ; Timer Control 3 Preliminary Data DSP56303/D, Rev. 1 MOTOROLA ...
Page 153
... Register Addresses Of DMA4 M_DSR4 EQU $FFFFDF ; DMA4 Source Address Register M_DDR4 EQU $FFFFDE ; DMA4 Destination Address Register M_DCO4 EQU $FFFFDD ; DMA4 Counter M_DCR4 EQU $FFFFDC ; DMA4 Control Register ; Register Addresses Of DMA5 MOTOROLA Power Consumption Benchmark ; DMA Status Register Preliminary Data DSP56303/D, Rev. 1 A-13 ...
Page 154
... DMA Channel Transfer Done Status 2 ; DMA Channel Transfer Done Status 3 ; DMA Channel Transfer Done Status 4 ; DMA Channel Transfer Done Status 5 ; DMA Active State ; DMA Active Channel Mask (DCH0-DCH2) ; DMA Active Channel 0 ; DMA Active Channel 1 ; DMA Active Channel 2 Preliminary Data DSP56303/D, Rev. 1 MOTOROLA ...
Page 155
... M_BDFW EQU $1F0000 ; Default Area Wait Control Mask (BDFW0-BDFW4) M_BBS EQU 21 M_BLH EQU 22 M_BRH EQU 23 ; DRAM Control Register MOTOROLA ; PLL Control Register : Multiplication Factor Bits Mask (MF0-MF11) ; Division Factor Bits Mask (DF0-DF2) ; XTAL Range select bit ; XTAL Disable Bit ; STOP Processing State Bit ...
Page 156
... Sixteen_Bit Compatibility ; Double Precision Multiply ; DO-Loop Flag ; DO-Forever Flag ; Sixteen-Bit Arithmetic ; Instruction Cache Enable ; Arithmetic Saturation ; Rounding Mode ; bit 0 of priority bits bit 1 of priority bits mask for CORE-DMA priority bits in OMR ; Operating Mode A Preliminary Data DSP56303/D, Rev. 1 MOTOROLA ...
Page 157
... I_VEC EQU $0 endif ;----------------------------------------------------------------------- - ; Non-Maskable interrupts ;----------------------------------------------------------------------- - I_RESET EQU I_VEC+$00 MOTOROLA ; Operating Mode B ; Operating Mode C ; Operating Mode D ; External Bus Disable bit in OMR ; Stop Delay ; Memory Switch bit in OMR ; bit 0 of priority bits in OMR ; bit 1 of priority bits in OMR ; Burst Enable ...
Page 158
... TIMER 2 compare ; TIMER 2 overflow ; ESSI0 Receive Data ; ESSI0 Receive Data w/ exception Status ; ESSI0 Receive last slot ; ESSI0 Transmit data ; ESSI0 Transmit Data w/ exception Status ; ESSI0 Transmit last slot ; ESSI1 Receive Data ; ESSI1 Receive Data w/ exception Status Preliminary Data DSP56303/D, Rev. 1 MOTOROLA ...
Page 159
... I_HTDE EQU I_VEC+$62 I_HC EQU I_VEC+$64 ;----------------------------------------------------------------------- - ; INTERRUPT ENDING ADDRESS ;----------------------------------------------------------------------- - I_INTEND EQU I_VEC+$FF MOTOROLA Power Consumption Benchmark ; ESSI1 Receive last slot ; ESSI1 Transmit data ; ESSI1 Transmit Data w/ exception Status ; ESSI1 Transmit last slot ; SCI Receive Data ; SCI Receive Data With Exception Status ...
Page 160
... BOOTSTRAP PROGRAMS ; BOOTSTRAP CODE FOR DSP56303 - (C) Copyright 1995 Motorola Inc. ; Revised June, 29 1995 Bootstrap through the Host Interface, External EPROM or SCI This is the Bootstrap program contained in the DSP56303 192-word Boot ; ROM. This program can load any program RAM segment from an external ...
Page 161
... The Host Interface bootstrap load program may be stopped by ; setting the Host Flag 0 (HF0). This will start execution of the loaded ; program from the specified starting address ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; If MC:MB:MA=110, then it loads the program RAM from the Host ; Interface programmed to operate in the 8051 multiplexed bus mode, B-2 DSP56303UM/AD, Rev. 1 MOTOROLA ...
Page 162
... M_SSR EQU $FFFF93 M_STXL EQU $FFFF95 M_SRXL EQU $FFFF98 MOTOROLA ; this is the location in P memory ; on the external memory bus ; where the external byte-wide ; EPROM would be located ; AAR1 selects the EPROM as CE~ ; mapped as P from $D00000 to ; $DFFFFF, active low ; SCI Status Register ...
Page 163
... SCI Control Register ; Port E Control register ; Address Attribute Register 1 ; bootstrap code starts at $ff0000 ; clear a and load X0 with constant 0a0000 ; If MC:MB:MA=0xx, go load from EPROM/SCI ; If MC:MB:MA=111, go load from MC68302 Host ; If MC:MB:MA=101, go load from HC11 Host ; If MC:MB:MA=100, go load from ISA HOST DSP56303UM/AD, Rev. 1 MOTOROLA ...
Page 164
... This bit should be set to 0 for future ; compatibility ; HEN = 0 When the HPCR register is modified HEN should be ; cleared ; HAEN= 0 Host acknowledge is disabled ; HREN= 1 Host requests are enabled ; HCSEN = 1 Host chip select input enabled MOTOROLA meaning in non-multiplexed bus) non-multiplexed bus) non-multiplexed bus) DSP56303UM/AD, Rev. 1 Bootstrap Programs B-5 ...
Page 165
... HROD= 0 Host request is active when enabled ; spare = 0 This bit should be set to 0 for future ; compatibility ; HEN = 0 When the HPCR register is modified HEN should be ; cleared ; HAEN= 1 Host acknowledge is enabled ; HREN= 1 Host requests are enabled ; HCSEN = 1 Host chip select input enabled B-6 DSP56303UM/AD, Rev. 1 MOTOROLA ...
Page 166
... SCILD movep #$0302,X:M_SCR movep #$C000,X:M_SCCR movep #7,X:M_PCRE do #6,_LOOP6 jclr #2,X:M_SSR,* movep X:M_SRXL,A2 MOTOROLA ; Enable the HI08 to operate as host ; interface (set HEN=1) ; wait for the program length written ; wait for the program starting address ; to be written ; set a loop with the downloaded length ...
Page 167
... Each instruction has 3 bytes ; Get the 8 LSB from ext. P mem. ; Shift 8 bit data into get another byte. ; Store 24-bit result in P mem. ; and go get another 24-bit word. ; Boot from EPROM done DSP56303UM/AD, Rev. 1 MOTOROLA ...
Page 168
... This is the exit handler that returns execution to normal ; expanded mode and jumps to the RESET vector. andi #$0,ccr jmp (r1) ; End of bootstrap code. Number of program words: 91 MOTOROLA ; Clear CCR as if RESET Then go to starting Prog addr. DSP56303UM/AD, Rev. 1 Bootstrap Programs B-9 ...
Page 169
... Bootstrap Programs B-10 DSP56303UM/AD, Rev. 1 MOTOROLA ...
Page 170
... D iii Data Arithmetic Logic Unit 1-1 data bus iv data memory expansion MOTOROLA INDEX dc electrical characteristics iii Debug support description, general design considerations 4-3 electrical 4-5, 4-6 PLL power consumption 4-1, 4-2 thermal Direct Memory Access iii DMA document conventions ...
Page 171
... N non-multiplexed bus non-multiplexed bus timings 2-63 read 2-64 write O ii off-chip memory OnCE module timing OnCE module Debug request OnCE/JTAG on-chip DRAM controller On-Chip Emulation module Preliminary Data DSP56303/D, Rev. 1 1-2 vi iii 2-5 ii 1-1, 1-9, 1-10 1-9, 1-10 2-10 2-18 2-18 2-19 2-80 1-1 2-1, 2-2 iii 1-9, 1-10 2-10 1-2 1-2 iii 2-80 iii, 1-24 2-80 1-2 iv iii MOTOROLA ...
Page 172
... Reset timing 2-17 synchronous iii ROM, bootstrap S v, 1-2, 1-22 SCI Asynchronous mode timing 2-69 Synchronous mode timing 2-67 timing MOTOROLA Serial Communications Interface Serial Communications Interface (SCI) signal groupings 1-1 signals functional grouping Single Data Strobe 2-54 SRAM Access read access read and write accesses support write access ...
Page 173
... Index 3-3 pin-out drawing (bottom) 3-2 pin-out drawing (top Wait mode vi World Wide Web X iii X data RAM Y iii Y data RAM Index-4 Preliminary Data DSP56303/D, Rev. 1 MOTOROLA ...
Page 174
... Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “ ...