AT7601F AME, AT7601F Datasheet
AT7601F
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AT7601F Summary of contents
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... AME, Inc. AT7601F 1. General Description The AT7601F is a Printer Port Controller. It supports the existing Centronics printer and IEEE 1284 compat- ible parallel ports 2. Features l 5V parallel port I/O l IBM PC compatible printer port l PS/2 compatible bi-directional parallel port l IEEE 1284 compatible Enhanced Parallel Port (EPP) ...
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... AME, Inc. AT7601F 4. Pin Description I - TTL level input O12 - Out buffer with 12mA drive/sink current OD12 - Open-drain with 12mA sink current ICLK - Clock Input OCLK - Clock Output Pin No. Pin name 2 AEN 3 IOCHRDY [ DACK# 14 DRQ XTAL1/CLKIN 17 XTAL2 18 RESET ...
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... AME, Inc. AT7601F Pin No. Pin name 20 SLCT BUSY 23 ACK# 24, 26-32 PD [0:7] 33 SLIN# 34 INIT# 37 ERR# 38 AFD# 39 STB# Pin No. Pin name 19, 47 VCC 12, 36 GND Rev. B.02 I/O Type I Printer Selected input. I Printer Paper End input. I Printer Busy input. I Printer Acknowledge input: active low I/O12 Printer port data bus ...
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... AME, Inc. AT7601F 5. Function Description 5-1 Printer Interface The AT7601F fully supports an IBM XT/AT compatible parallel port, bi-directional parallel port (SPP), Enhanced Parallel Port (EPP), Extended Capabilities Parallel Port (ECP). Pin Host NO. Connector Table 4 ...
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... AME, Inc. AT7601F 5-2 Enhanced Parallel Port(EPP) SPP Name EPP Name STB# Write# PD[0:7] PD [0: 7] ACK# INTR BUSY Wait SLCT Select AFD DataSTB# ERR# Error# INIT# INIT# SLIN# AddrSTB Note 1: These registers are in all mode ...
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... AME, Inc. AT7601F Printer Status Port Address Offset = 01H The Status Port is located at an offset of '01H' from the base address. The contents of this register are latched for the duration of an IOR# read cycle. The bits of the Status Port are defined as follows: ...
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... AME, Inc. AT7601F Bit 0 TMout: TIME OUT The bit is valid in EPP mode only and indicates that a 10 uSec time out has occurred on the EPP bus. A logic 0 means that no time out error has occurred; a logic 1 means that a time out error has been detected. This bit is cleared by a RESET. Writing a one to this bit clears the time out status bit ...
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... AME, Inc. AT7601F Bit 3 SLIN (PRINTER SELECT INPUT) This bit is inverted and output onto the SLIN# output. A logic 1 on this bit selects the printer; a logic 0 means the printer is not selected. Bit 2 INIT# (INITIATE OUTPUT starts the printer (50 microsecond pulse, minimum). ...
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... AME, Inc. AT7601F 5-2-4 EPP Data Port These four registers are available only in EPP mode. Bit definitions of each port are as follows: 7 When accesses are made to any EPP data port, the contents of DB0-DB7 are buffered (non-inverting) and output to the ports PD0-PD7 during a write operation. The leading edge of LOW latches the data for the duration of the EPP write cycle ...
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... AME, Inc. AT7601F 5-2-5 EPP 1.9 Operation When the EPP mode is selected in the configuration register, the standard and bi-directional modes are also available EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bi-directional mode, and all output signals (STB, AFDD, INIT) are as set by the SPP Control Port and direction is controlled by PCD of the Control port ...
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... AME, Inc. AT7601F Pin Name ECP Mode Name STB# HostClk PD [7:0] D0-D7 ACK# PeriphClk Busy PeriphAck PError AckReverse# SLCT Xflag AFD# HostAck Fault# PeriphReq# INIT# ReverseReq# SLIN# ECPMode Rev. B.02 I/O Type During write operations STB# registers data or address O into the slave on the asserting edge. These signal handshakes with Busy ...
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... AME, Inc. AT7601F Name Address Data Base+000h ECP-AFIFO Base+000h DSR Base+001h DCR Base+002h C-FIFO Base+400h ECP-DFIFO Base+400h T-FIFO Base+400h Cnfg-A Base+400h Cnfg-B Base+401h ECR Base+402h Note 1: These address are added to the parallel port base address as selected by configuration register or jump- ers. Note 2: All address are qualified with AEN. Refer to the AEN pin definition. ...
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... AME, Inc. AT7601F D7 Data PD7 ECP-AFIFO Addr/RLE DSR BUSY# DCR 1 C-FIFO ECP-DFIFO T-FIFO Cnfg-A 0 Cnfg-B Compress IntrValue MODE ECR * Registers are in all modes. ** All FIFOs use one common 16-byte FIFO. 5-3-1.1 Data and ECP- AFIFO Port Modes 000 and 001 (Data Port) The Data Port is located at an offset of '00H'from the base address ...
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... AME, Inc. AT7601F 5-3-1.2 Device Status Register (DSR) The Status Port is located at an offset of '01H'from the base address. Bits 0-2 are not implemented as register bits; during a read of the Printer Status Register these bits are a low level. The bits of the Status Port are defined as follows: Bit 0-2: the Status Port is located at an offset of '01H'from the base address. Bits 0-2 are not imple- mented as register bits ...
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... AME, Inc. AT7601F 5-3-1.4 C-FIFO (Parallel Port Data FIFO) Mode = 010 Bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral using the standard parallel port protocol. Transfers to the FIFO are byte aligned. This mode is only defined for the forward direction. ...
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... AME, Inc. AT7601F 5-3-1.8 Cnfg-B (Configuration Register B) Mode = 111 The bit definitions are as follows: Bit 7 Compress: This bit is read only. During a read low level. This means that this chip does not support hardware RLE compression. It does support hardware de-compression! Bit 6 IntrValue: Returns the value on the ISA IRQ line to determine possible conflicts. ...
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... AME, Inc. AT7601F Mode [7:5] Standard Parallel Port Mode. In this mode the FIFO is reset and common collector drivers 000 are used on the control lines (STB#, AFD#, lNIT# and SLIN#). Setting the direction bit will not tri-state the output drivers in this mode. PS/2 Parallel Port Mode. Same as above except that direction may be used to ...
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... AME, Inc. AT7601F Bit 4 ErrIntrEn# : Read/Write (Valid only in ECP Mode) 1 Disables the interrupt generated on the asserting edge of Fault#. 0 Enables an interrupt pulse on the high to low edge of Fault#. Note that an interrupt will be generated if Fault# is asserted (interrupting) and this bit is written from This prevents interrupts from being lost in the time between the read of the ECR and the write of the ECR ...
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... AME, Inc. AT7601F 5-3-2 Operation Mode Switching / Software Control Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ECP port only in the data transfer phase (modes 011 or 010). ...
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... AME, Inc. AT7601F 5-3-2.3 Command/Data ECP Mode supports two advanced features to improve the effectiveness of the protocol for some applica- tions. The features are implemented by allowing the transfer of normal 8-bit commands. When in the forward direction, normal data is transferred when HostAck is high and an 8-bit command is transferred when HostAck is low ...
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... AME, Inc. AT7601F 5-3-2.7 Interrupts The interrupts are enabled by Servicelntr in the ECR register. Servicelntr = 1 Disables the DMA and all of the service interrupts. Servicelntr = 0 Enables the selected interrupt condition. If the interrupting condition is valid, then the interrupt is generated immediately when this bit is changed from This can occur during Programmed I/O if the number of bytes removed or added from/to the FIFO does not cross the threshold ...
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... AME, Inc. AT7601F 5-3-2.9 DMA Transfers DMA transfers are always to or from the ECP-DFIFO, T-FIFO or C-FIFO. DMA utilizes the standard PC DMA services. To use the DMA transfers, the host first sets up the direction and state as in the pro- grammed I/O case. Then it programs the DMA controller in the host with the desired count and memory address ...
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... AME, Inc. AT7601F 5-3-2-12 Programmed I/O - Transfer from the FIFO to Host In the reverse direction an interrupt occurs when Servicelntr is 0 and ReadlntrThreshold bytes are available in the FIFO this time the FIFO is full it can be emptied completely in a single burst, otherwise ReadlntrThreshold bytes may be read from the FIFO in a single burst. ReadlntrThreshold=16- < ...
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... AME, Inc. AT7601F 6. Configuration Register The configuration registers of AT7601F are implemented to provide special function control, such as power-down mode, I/O port tri-state control, and select address-decoding modes. The current IRQ and DMA channel used for AT7601F can be setting in configuration registers. The configuration registers can only be accessed through configuration I/O ports (INDEX and DATA) under configura- tion mode ...
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... AME, Inc. AT7601F 6-1 Configuration Register Description CR20 CHIP ID REGISTER 1(Default 0x76) This register is read-only. CR21 CHIP ID REGISTER 2(Default 0x01) This register is read-only. CRF0 MODE CONTROL REGISTER (Default 0x3F) Bit 7: Parallel Port Interrupt Type This bit is valid except Parallel Port Mode is set in Printer Mode(Bit[2:0]=100), os Standard& Bi-directional Mode(Bit[2:0]=000) ...
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... AME, Inc. AT7601F CRF2 CHIP CONTROL REGISTER 1(Default 0x00) Bit 7: Power-Down Chip is operating Chip is power-down. Bit 6: Tri-state Control Output ports are driving Output ports are tri-state if bit7 is set. Bit 5: Legacy IRQ/DRQ Select Enable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is effective on selecting IRQ. ...
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... AME, Inc. AT7601F 0-70 C, Vcc = 5.0V 10% unless otherwise specified. Symbol Parameter T1 ANE setup to command active T2 Command width T3 ANE hold from command inactive T4 Data access from IOR# active T5 Data setup to IOW# inactive T6 Data hold from command inactive PD [0:7], STB#, AFD#, INIT, SLIN# T7 delay from IOW# inactive ...
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... AME, Inc. AT7601F O TA=0 ~70 C, Vcc=5.0V 10% unless otherwise specified. Symbol Parameter T34 Hose data setup to IOW# active T35 Hose data hold from IOW# active T36 IOW# active to IOCHRDY low T37 IOCHRDY high to Host terminate (IOW# inactive) T38 IOW# inactive to Host command active ...
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... AME, Inc. AT7601F O TA=0 ~70 C, Vcc=5.0V 10% unless otherwise specified. Symbol Parameter VILCK Clock Input Low level CIHCL Clock Input High level VIL Input Low level VIH Input High level VOL Output Low level VOL Output Low level PDIR IDL=4mA VOH Output high level ...
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... AME, Inc. AT7601F 30 Figure 3. Parallel Port Timing in SPP, PS/2 Mode Printer Port Cotroller Rev. B.02 ...
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... AME, Inc. AT7601F Rev. B.02 Printer Port Controller 31 ...
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... AME, Inc. AT7601F 32 Printer Port Cotroller Rev. B.02 ...
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... AME, Inc. AT7601F Rev. B.02 Printer Port Controller 33 ...
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... AME, Inc. AT7601F 6. Package Information LQFP-48 Outline Dimension TOP VIEW A" FRONT VIEW 0.05 max e H GAUGE PLANE SEATING PLANE DETAL : A" SYMBOLS Printer Port Cotroller MILLIMETERS INCHES MIN NOM MAX ...
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... These products of AME, Inc. are not authorized for use as critical components in life-support devices or systems, without the express written approval of the president AME, Inc. reserves the right to make changes in the circuitry and specifications of its devices and advises its customers to obtain the latest version of relevant information. ...