21154AC Intel Corporation, 21154AC Datasheet

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21154AC

Manufacturer Part Number
21154AC
Description
Interface, Transparent PCI-to-PCI Bridge
Manufacturer
Intel Corporation
Datasheet

Specifications of 21154AC

Case
BGA
Dc
00+/01+
21154 PCI-to-PCI Bridge
Product Features
1.
For the 21154–AB and later revisions only. The 21154–AA does not implement this feature.
Complies fully with the PCI Local Bus
Specification, Revision 2.1
Complies fully with the PCI Power
Management Specification, Revision 1.0
Supports 64-bit extension signals on the
primary and secondary interfaces
Implements delayed transactions for all PCI
configuration, I/O, and memory read
commands–up to three transactions
simultaneously in each direction
address) for upstream posted memory write
commands and 88 bytes of buffering for
downstream posted memory write
commands—up to nine upstream and five
downstream posted write transactions
simultaneously
Allows 152 bytes of read data buffering
upstream and 152 bytes of read data
buffering downstream
Provides concurrent primary and secondary
bus operation to isolate traffic
Provides ten secondary clock outputs:
Provides arbitration support for nine
secondary bus devices:
— Low skew, permitting direct drive of
— Individual clock disables, capable of
— A programmable 2-level arbiter
— Hardware disable control, permitting use
Allows 152 bytes of buffering (data and
option slots
automatic configuration during reset
of an external arbiter
1
Provides a 4-pin general-purpose I/O
interface, accessible through device-
specific configuration space
Provides enhanced address decoding:
Includes live insertion support
Supports PCI transaction forwarding for the
following commands:
Includes downstream lock support
Supports both 5-V and 3.3-V signaling
environments
Available in both 33 MHz and 66 Mhz
versions
Provides an IEEE standard 1149.1 JTAG
interface
— A 32-bit I/O address range
— A 32-bit memory-mapped I/O address
— A 64-bit prefetchable memory address
— ISA-aware mode for legacy support in
— VGA addressing and VGA palette
— All I/O and memory commands
— Type 1 to Type 1 configuration
— Type 1 to Type 0 configuration
— All Type 1 to special cycle configuration
range
range
the first 64KB of I/O address range
snooping support
commands
commands (downstream only)
commands
Order Number: 278108-002
Datasheet
July 1999

Related parts for 21154AC

21154AC Summary of contents

Page 1

PCI-to-PCI Bridge Product Features Complies fully with the PCI Local Bus Specification, Revision 2.1 Complies fully with the PCI Power Management Specification, Revision 1.0 Supports 64-bit extension signals on the primary and secondary interfaces Implements delayed transactions for all ...

Page 2

... Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel’s website at http://www.intel.com. Copyright © Intel Corporation, 1999 *Third-party brands and names are the property of their respective owners. ...

Page 3

Contents 1.0 Introduction......................................................................................................................... 1 1.1 Architecture ........................................................................................................... 3 1.2 Data Path .............................................................................................................. 5 1.2.1 Posted Write Queue ................................................................................. 6 1.2.2 Delayed Transaction Queue..................................................................... 6 1.2.3 Read Data Queue .................................................................................... 6 2.0 Signal Pins ......................................................................................................................... 7 2.1 Primary PCI Bus Interface ...

Page 4

PCI-to-PCI Bridge 4.7.3 Type 1 to Type 1 Forwarding ................................................................. 48 4.7.4 Special Cycles........................................................................................ 49 4.8 64-Bit Operation .................................................................................................. 50 4.8.1 64-Bit and 32-Bit Transactions Initiated by the 21154............................ 50 4.8.2 Address Phase of 64-Bit Transactions ................................................... 50 4.8.3 ...

Page 5

Exclusive Access.............................................................................................................. 87 8.1 Concurrent Locks ................................................................................................ 87 8.2 Acquiring Exclusive Access Across the 21154....................................................87 8.3 Ending Exclusive Access .................................................................................... 88 9.0 PCI Bus Arbitration........................................................................................................... 91 9.1 Primary PCI Bus Arbitration ................................................................................ 91 9.2 Secondary PCI Bus Arbitration............................................................................ 91 ...

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PCI-to-PCI Bridge 15.1.19 Memory Base Address Register—Offset 20h ...................................... 118 15.1.20 Memory Limit Address Register—Offset 22h ....................................... 118 15.1.21 Prefetchable Memory Base Address Register—Offset 24h ................. 119 15.1.22 Prefetchable Memory Limit Address Register—Offset 26h.................. 119 15.1.23 Prefetchable Memory Base ...

Page 7

PCI Signal Timing Specifications .........................................................152 17.4.3 Reset Timing Specifications ................................................................. 154 17.4.4 gpio Timing Specifications.................................................................... 154 17.4.5 JTAG Timing Specifications ................................................................. 155 18.0 Mechanical Specifications .............................................................................................. 157 Figures 1 21154 on the System Board.................................................................................. 2 2 21154 with Option ...

Page 8

PCI-to-PCI Bridge 16 21154 PCI Transactions...................................................................................... 31 17 Write Transaction Forwarding ............................................................................. 33 18 Write Transaction Disconnect Address Boundaries ............................................ 38 19 Read Transaction Prefetching............................................................................. 40 20 Read Prefetch Address Boundaries .................................................................... 41 21 Device Number to IDSEL s_ad ...

Page 9

Introduction The 21154 is a second-generation PCI-to-PCI bridge and is fully compliant with PCI Local Bus Specification, Revision 2.1. The 21154 has a 64-bit primary bus interface and a 64-bit secondary interface. The 64-bit interfaces interoperate transparently with either ...

Page 10

PCI-to-PCI Bridge . Figure 1. 21154 on the System Board CPU Core Logic SCSI Option card designers can use the 21154 to implement multiple-device PCI option cards. Without a PCI-to-PCI bridge, PCI loading rules would limit option cards to ...

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Figure 2. 21154 with Option Cards 21154 Note: 1.1 Architecture The 21154 internal architecture consists of the following major functions: • PCI interface control logic for the primary and secondary PCI interfaces • Data path and data path control logic ...

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PCI-to-PCI Bridge Figure 3. 21154 Block Diagram Secondary Arbiter Clocks and Reset Primary Request and Grant Table 1 describes the major functional blocks of the 21154. Table 1. 21154 Function Blocks (Sheet Function Block Primary and ...

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Table 1. 21154 Function Blocks (Sheet Function Block Secondary-to-Primary Data Path Configuration Registers Secondary Bus Arbiter Control 1.2 Data Path The data path consists of a primary-to-secondary data path for transactions and data flowing in the downstream ...

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PCI-to-PCI Bridge 1.2.1 Posted Write Queue The posted write queue contains the address and data of memory write transactions targeted for the opposite interface. The posted write transaction can consist of an arbitrary number of data phases, subject to ...

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Signal Pins This chapter provides detailed descriptions of the 21154 signal pins, grouped by function. Table 2 describes the signal pin functional groups, and the following sections describe the signals in each group. Table 2. Signal Pin Functional Groups ...

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PCI-to-PCI Bridge Note: The _l signal name suffix indicates that the signal is asserted when low voltage level and corresponds to the "#" suffix in the PCI Local Bus Specification. If this suffix is not ...

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Table 4. Primary PCI Bus Interface Signals (Sheet Signal Name Type p_irdy_l STS p_trdy_l STS p_devsel_l STS p_stop_l STS p_lock_l I p_idsel I Datasheet Description Primary PCI interface IRDY#. Signal p_irdy_l is driven by the initiator of ...

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PCI-to-PCI Bridge Table 4. Primary PCI Bus Interface Signals (Sheet Signal Name Type p_perr_l STS p_serr_l OD p_req_l TS p_gnt_l I 10 Description Primary PCI interface PERR#. Signal p_perr_l is asserted when a data parity error ...

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Primary PCI Bus Interface 64-Bit Extension Signals Table 5 describes the primary PCI bus interface 64-bit extension signals. Table 5. Primary PCI Bus Interface 64-Bit Extension Signals Signal Name p_ad<63:32> p_cbe_l<7:4> p_par64 p_req64_l p_ack64_l Datasheet Type Description Primary PCI ...

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PCI-to-PCI Bridge 2.3 Secondary PCI Bus Interface Signals Table 6 describes the secondary PCI bus interface signals. Table 6. Secondary PCI Bus Interface Signals (Sheet Signal Name s_ad<31:0> s_cbe_l<3:0> s_par s_frame_l s_irdy_l 12 Type Description Secondary ...

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Table 6. Secondary PCI Bus Interface Signals (Sheet Signal Name s_trdy_l s_devsel_l s_stop_l s_lock_l s_perr_l s_serr_l Datasheet Type Description Secondary PCI interface TRDY#. Signal s_trdy_l is driven by the target of a transaction to indicate the target’s ...

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PCI-to-PCI Bridge 2.4 Secondary PCI Bus Interface 64-Bit Extension Signals Table 7 describes the secondary PCI bus interface 64-bit extension signals. Table 7. Secondary PCI Bus Interface 64-Bit Extension Signals Signal Name Type s_ad<63:32> TS s_cbe_l<7:4> TS s_par64 TS ...

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Secondary Bus Arbitration Signals describes the secondary bus arbitration signals Table 8 Table 8. Secondary PCI Bus Arbitration Signals Signal Name Type s_req_l<8:0> I s_gnt_l<8:0> TS s_cfn_l I 2.6 General-Purpose I/O Interface Signals describes the general-purpose I/O interface signals ...

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PCI-to-PCI Bridge 2.7 Clock Signals Table 10 describes the clock signals. Table 10. Clock Signals Signal Name Type p_clk I s_clk I s_clk_o<9:0> O 2.8 Reset Signals describes the reset signals. Table 11 Table 11. Reset Signals (Sheet 1 ...

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Table 11. Reset Signals (Sheet Signal Name Type s_rst_l O 1. For 21154–AB and later revisions only. 2.9 Miscellaneous Signals Table 12 describes the miscellaneous signals. Table 12. Miscellaneous Signals (Sheet Signal Name Type ...

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PCI-to-PCI Bridge Table 12. Miscellaneous Signals (Sheet Signal Name Type config66 I p_m66ena I s_m66ena I/OD 2.10 JTAG Signals Table 13 describes the JTAG signals. Table 13. JTAG Signals Signal Name Type tdi I tdo O ...

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Pin Assignment This chapter describes the 21154 pin assignment and lists the pins according to location and in alphabetic order. Figure 5 shows the 21154 304-point ball grid array, representing the pins in vertical rows labeled alphabetically, and horizontal ...

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PCI-to-PCI Bridge 3.1 Numeric Pin Assignment Table 14 lists the 21154 pins in order of location, showing the location code, name, and signal type of each pin. Figure 5 provides the map for identifying the pin location codes, listed ...

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Table 14. 21154 PBGA Pin List (Sheet PBGA Location Pin Name B17 s_ad<4> B19 s_req64_l B21 vss B23 vdd C1 s_req_l<1> C3 s_ad<31> C5 s_ad<25> C7 vss C9 s_irdy_l C11 s_perr C13 s_ad<15> C15 s_ad<9> C17 s_ad<5> ...

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PCI-to-PCI Bridge Table 14. 21154 PBGA Pin List (Sheet PBGA Location Pin Name F23 s_ad<51> G1 s_gnt_l<4> G3 s_gnt_l<7> — G21 s_ad<47> G23 vss H1 s_gnt_l<8> H3 vss — — H21 s_ad<44> H23 s_ad<46> J1 vdd ...

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Table 14. 21154 PBGA Pin List (Sheet PBGA Location Pin Name P3 s_clk_o<7> — — P21 tms P23 tdi R1 vdd R3 p_rst_l — — R21 msk_in R23 vdd T1 vdd T3 p_clk — — T21 p_par64 ...

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PCI-to-PCI Bridge Table 14. 21154 PBGA Pin List (Sheet PBGA Location Pin Name Y17 p_ad<59> Y19 p_ad<52> Y21 p_ad<45> Y23 p_ad<43> AA1 p_ad<21> AA3 p_ad<20> AA5 p_frame_l AA7 p_cbe_l<1> AA9 p_ad<11> AA11 p_ad<6> AA13 p_ad<2> AA15 ...

Page 33

Table 14. 21154 PBGA Pin List (Sheet PBGA Location Pin Name AC19 p_ad<55> AC21 p_ad<49> AC23 vss 1. Pertains to the 21154–AB and later revisions only. For the 21154–AA, this pin is vss. 3.2 Pins Listed in ...

Page 34

PCI-to-PCI Bridge Table 15. 21154 PBGA Pin List (Sheet PBGA Pin Name Location p_ad<16> Y5 p_ad<17> AA4 p_ad<18> AB3 p_ad<19> Y4 p_ad<20> AA3 p_ad<21> AA1 p_ad<22> Y3 p_ad<23> W4 p_ad<24> W1 p_ad<25> W2 p_ad<26> V3 p_ad<27> ...

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Table 15. 21154 PBGA Pin List (Sheet PBGA Pin Name Location s_ack64_l C18 s_ad<0> A18 s_ad<1> B18 s_ad<2> A17 s_ad<3> D17 s_ad<4> B17 s_ad<5> C17 s_ad<6> B16 s_ad<7> C16 s_ad<8> B15 s_ad<9> C15 s_ad<10> B14 s_ad<11> C14 ...

Page 36

PCI-to-PCI Bridge Table 15. 21154 PBGA Pin List (Sheet PBGA Pin Name Location s_clk J4 s_clk_o<0> L2 s_clk_o<1> L3 s_clk_o<2> M3 s_clk_o<3> M1 s_clk_o<4> M2 s_clk_o<5> N3 s_clk_o<6> N1 s_clk_o<7> P3 s_clk_o<8> P2 s_clk_o<9> P1 s_devsel_l ...

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Table 15. 21154 PBGA Pin List (Sheet PBGA Pin Name Location vdd T20 vdd W3 vdd Y6 vdd Y10 vdd Y14 vdd Y18 vdd Y22 vdd AB1 vdd AB19 vdd AB23 vdd AC2 vdd AC3 vdd AC8 ...

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...

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PCI Bus Operation This chapter presents detailed information about PCI transactions, transaction forwarding across the 21154, and transaction termination. operation. Section 4.8 4.1 Types of Transactions This section provides a summary of PCI transactions performed by the 21154. command ...

Page 40

PCI-to-PCI Bridge special cycle transactions on other PCI buses, either upstream or downstream, a Type 1 configuration command must be used. • The 21154 does not generate Type 0 configuration transactions on the primary interface, nor does it respond ...

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Memory write and invalidate • Memory read • Memory read line • Memory read multiple Use of other transaction codes may result in a master abort. Any memory transactions addressing the first 4GB space should use a single address ...

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PCI-to-PCI Bridge 4.5.1 Posted Write Transactions Posted write forwarding is used for memory write and for memory write and invalidate transactions. When the 21154 determines that a memory write transaction forwarded across the bridge, the 21154 ...

Page 43

Figure 6. Flow-Through Posted Memory Write Transaction CY0 Cycle CY1 < 15ns > p_clk p_ad Addr p_cbe_l 7 p_frame_l p_irdy_l p_devsel_l p_trdy_l p_stop_l s_clk s_ad s_cbe_l s_frame_l s_irdy_l s_devsel_l s_trdy_l s_stop_l The 21154 ends the transaction on the target bus ...

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PCI-to-PCI Bridge The 21154 disconnects memory write and invalidate commands at aligned cache line boundaries. The cache line size value in the 21154 cache line size register gives the number of Dwords in a cache line. For the 21154 ...

Page 45

When the initiator repeats the same write transaction (same command, address, byte enable bits, and data), and the completed delayed transaction is at the head of the queue, the 21154 claims the access by asserting DEVSEL# and returns TRDY# to ...

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PCI-to-PCI Bridge The 21154 implements a discard timer that starts counting when the delayed write completion is at the head of the delayed transaction queue. The initial value of this timer can be set to one of two values, ...

Page 47

Fast Back-to-Back Write Transactions The 21154 can recognize and post fast back-to-back write transactions. When the 21154 cannot accept the second transaction because of buffer space limitations, it returns a target retry to the initiator. When the 21154 has ...

Page 48

PCI-to-PCI Bridge 4.6 Read Transactions Delayed read forwarding is used for all read transactions crossing the 21154. Delayed read transactions are treated as either prefetchable or nonprefetchable. Table 19 shows the read behavior, prefetchable or nonprefetchable, for each type ...

Page 49

If extra read transactions could have side effects, for example, when accessing a FIFO, use nonprefetchable read transactions to those locations. Accordingly important to retain the value of the byte enable bits during the data phase, use ...

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PCI-to-PCI Bridge 21154 terminates the transaction by signaling a target retry to the initiator. Upon reception of the target retry, the initiator is required to continue to repeat the same read transaction until at least one data transfer is ...

Page 51

Figure 9 shows a nonprefetchable delayed read transaction. Figure 9. Nonprefetchable Delayed Read Transaction CY0 Cycle < 15ns > p_clk p_ad p_cbe_l p_frame_l p_irdy_l p_devsel_l p_trdy_l p_stop_l s_clk s_ad s_cbe_l s_frame_l s_irdy_l s_devsel_l s_trdy_l s_stop_l Datasheet CY2 CY4 CY6 CY1 ...

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PCI-to-PCI Bridge Figure 10 shows a prefetchable delayed read transaction. Figure 10. Prefetchable Delayed Read Transaction CY0 CY2 Cycle CY1 < 15ns > p_clk p_ad Addr p_cbe_l 6 Byte Enables p_frame_l p_irdy_l p_devsel_l p_trdy_l p_stop_l s_clk s_ad s_cbe_l s_frame_l ...

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Figure 11 shows a flow-through prefetchable read transaction. Figure 11. Flow-Through Prefetchable Read Transaction CY0 Cycle <15ns> p_clk p_ad p_cbe_l p_frame_l p_irdy_l p_devsel_l p_trdy_l p_stop_l s_clk s_ad s_cbe_l s_frame_l s_irdy_l s_devsel_l s_trdy_l s_stop_l The 21154 implements a discard timer that ...

Page 54

PCI-to-PCI Bridge 4.7 Configuration Transaction Configuration transactions are used to initialize a PCI system. Every PCI device has a configuration space that is accessed by configuration commands. All 21154 registers are accessible in configuration space only. In addition to ...

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Low 2 address bits p_ad<1:0> must be 00b. • Signal p_idsel must be asserted. The function code is ignored because the 21154 is a single-function device. The 21154 limits all configuration accesses to a single Dword data transfer and ...

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PCI-to-PCI Bridge Table 21 presents the mapping that the 21154 uses. Table 21. Device Number to IDSEL s_ad Pin Mapping Device Number 10h–1Eh ...

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The low 2 address bits are equal to 01b. • The bus number falls in the range defined by the lower limit (exclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number ...

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PCI-to-PCI Bridge 4.8 64-Bit Operation The 21154 provides 64-bit extension support on the primary and secondary interfaces. Both 64-bit and 32-bit operation are supported on both interfaces. This section describes how to use the 64-bit extensions. It describes the ...

Page 59

When the transaction is a dual address cycle (DAC)—that is, the address falls above the 4GB boundary, and the upper 32 bits of the address are nonzero—signals AD<63:32> contain the upper 32 bits of the address for both address phases. ...

Page 60

PCI-to-PCI Bridge • Only 1 Dword of data was read from the target. When the 21154 is the target of a 64-bit memory write transaction able to accept 64 bits of data during each data phase. When ...

Page 61

It would then be possible for the posted write buffer to empty during the write transaction result, additional wait states would be introduced on the ...

Page 62

PCI-to-PCI Bridge 4.10.1 Master Termination Initiated by the 21154 The 21154 initiator, uses normal termination if DEVSEL# is returned by the target within five clock cycles of the 21154’s assertion of FRAME# on the target bus. As ...

Page 63

Figure 13. Delayed Write Transaction Terminated with Master Abort CY0 Cycle < 15ns > p_clk p_ad p_cbe_l p_frame_l p_irdy_l p_devsel_l p_trdy_l p_stop_l s_clk s_ad s_cbe_l s_frame_l s_irdy_l s_devsel_l s_trdy_l s_stop_l When a master abort is received in response to a ...

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PCI-to-PCI Bridge • Target disconnect • Target abort The 21154 handles these terminations in different ways, depending on the type of transaction being performed. 4.10.3.1 Delayed Write Target Termination Response When the 21154 initiates a delayed write transaction, the ...

Page 65

Table 23. 21154 Response to Posted Write Target Termination Target Termination Normal Target retry Target disconnect Target abort Note that when a target retry or target disconnect is returned and posted write data associated with that transaction remains in the ...

Page 66

PCI-to-PCI Bridge Figure 14. Delayed Read Transaction Terminated with Target Abort CY0 Cycle < 15ns > p_clk p_ad p_cbe_l p_frame_l p_irdy_l p_devsel_l p_trdy_l p_stop_l s_clk s_ad s_cbe_l s_frame_l s_irdy_l s_devsel_l s_trdy_l s_stop_l 58 CY2 CY4 CY6 CY1 CY3 CY5 ...

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The 21154 repeats a delayed read transaction until one of the following conditions is met: • The 21154 completes at least one data transfer. • The 21154 receives a master abort. • The 21154 receives a target abort. • The ...

Page 68

PCI-to-PCI Bridge — The posted write data buffer does not have enough space for address and at least 8 Dwords of write data. — A locked sequence is being propagated across the 21154, and the write transaction is not ...

Page 69

Address Decoding The 21154 uses three address ranges that control I/O and memory transaction forwarding. These address ranges are defined by base and limit address registers in the 21154 configuration space. This chapter describes these address ranges, as well ...

Page 70

PCI-to-PCI Bridge Configure the I/O base and limit address registers, ISA enable bit, VGA mode bit, and VGA snoop bit before setting the I/O enable and master enable bits, and change them subsequently only when the primary and secondary ...

Page 71

The I/O limit register consists of an 8-bit field at configuration offset 1Dh and a 16-bit field at offset 32h. The top 4 bits of the 8-bit field define bits <15:12> of the I/O limit address. The bottom 4 bits ...

Page 72

PCI-to-PCI Bridge Figure 16 illustrates I/O forwarding when the ISA enable bit is set. Figure 16. I/O Transaction Forwarding in ISA Mode 5.3 Memory Address Decoding The 21154 has three mechanisms for defining memory address ranges for forwarding of ...

Page 73

Configure the memory-mapped I/O base and limit address registers, prefetchable memory base and limit address registers, and VGA mode bit before setting the memory enable and master enable bits, and change them subsequently only when the primary and secondary ...

Page 74

PCI-to-PCI Bridge Figure 17 shows how transactions are forwarded using both the memory-mapped I/O range and the prefetchable memory range. Figure 17. Memory Transaction Forwarding Using Base and Limit Registers 5.3.2 Prefetchable Memory Base and Limit Address Registers Locations ...

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The prefetchable memory base address upper 32 bits register must order to pass any single address cycle transactions downstream. Section 5.3.3 further describes 64-bit addressing support. The prefetchable memory ...

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PCI-to-PCI Bridge If the secondary interface prefetchable memory space resides entirely above the first 4GB of memory, both the prefetchable memory base address upper 32 bits register and the prefetchable memory limit address upper 32 bits register must be ...

Page 77

Read transactions to frame buffer memory are treated as nonprefetchable. The 21154 requests only a single data transfer from the target, and read byte enable bits are forwarded to the target bus. The VGA I/O addresses consist of the following ...

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...

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Transaction Ordering To maintain data coherency and consistency, the 21154 complies with the ordering rules set forth in the PCI Local Bus Specification, Revision 2.1, for transactions crossing the bridge. This chapter describes the ordering rules that control transaction ...

Page 80

PCI-to-PCI Bridge 6.2 General Ordering Guidelines Independent transactions on the primary and secondary buses have a relationship only when those transactions cross the 21154. The following general ordering guidelines govern transactions crossing the 21154: • The ordering relationship of ...

Page 81

The entries without superscripts reflect the 21154’s implementation choices. The following ordering rules describe the transaction relationships. Each ordering rule is followed by an explanation, and the ordering rules ...

Page 82

PCI-to-PCI Bridge The 21154 does not have a hardware mechanism to guarantee data synchronization for posted write transactions. Therefore, all posted write transactions must be followed by a read operation, either from the device to the location just written ...

Page 83

Error Handling The 21154 checks, forwards, and generates parity on both the primary and secondary interfaces. To maintain transparency, the 21154 always tries to forward the existing parity condition on one bus to the other bus, along with address ...

Page 84

PCI-to-PCI Bridge — The parity error response bit is set in the bridge control register. 7.2 Data Parity Errors When forwarding transactions, the 21154 attempts to pass the data parity condition from one interface to the other unchanged, whenever ...

Page 85

The 21154 sets the data parity detected bit in the primary status register, if the primary interface parity error response bit is set in the command register. • The 21154 forwards the bad parity with the data back to ...

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PCI-to-PCI Bridge • The 21154 captures the parity error condition to forward it back to the initiator on the primary bus. Similarly, for upstream transactions, when the 21154 is delivering data to the target on the primary bus and ...

Page 87

The primary interface parity error response bit is set in the command register. — The secondary interface parity error response bit is set in the bridge control register. • The 21154 completes the transaction normally. 7.2.4 Posted Write Transactions ...

Page 88

PCI-to-PCI Bridge — The primary interface parity error response bit is set in the command register. — The 21154 did not detect the parity error on the secondary (initiator) bus; that is, the parity error was not forwarded from ...

Page 89

Table 27. Setting the Secondary Interface Detected Parity Error Bit Secondary Detected Transaction Parity Type Error Bit 0 Read 1 Read 0 Read 0 Read 0 Posted write 0 Posted write 0 Posted write 1 Posted write 0 Delayed ...

Page 90

PCI-to-PCI Bridge Table 28. Setting the Primary Interface Data Parity Detected Bit Primary Data Transaction Parity Type Detected Bit 0 Read 0 Read 1 Read 0 Read 0 Posted write 0 Posted write 1 Posted write 0 Posted write ...

Page 91

Table 29. Setting the Secondary Interface Data Parity Detected Bit (Sheet Secondary Data Parity Transaction Detected Type Bit 1 Delayed write 0 Delayed write 0 Delayed write 1. x — don’t care. Table 30 shows assertion of ...

Page 92

PCI-to-PCI Bridge Table 31. Assertion of s_perr_l Transaction s_perr_l Type 1 (deasserted) Read 0 (asserted) Read 1 Read 1 Read 1 Posted write 1 Posted write 1 Posted write 0 Posted write 1 Delayed write 1 Delayed write 2 ...

Page 93

Table 32. Assertion of p_serr_l for Data Parity Errors Transaction p_serr_l Type 1 (deasserted) Read 1 Read 1 Read 1 Read 1 Posted write 2 0 (asserted) Posted write 3 0 Posted write 1 Posted write 1 Delayed write 1 ...

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PCI-to-PCI Bridge • Delayed read data cannot be transferred from target after 2 received) • Master timeout on delayed transaction The device-specific p_serr_l status register reports the reason for the 21154’s assertion of p_serr_l. Most of these events have ...

Page 95

Exclusive Access This chapter describes the use of the LOCK# signal to implement exclusive access to a target for transactions that cross the 21154. 8.1 Concurrent Locks The primary and secondary bus lock mechanisms operate concurrently except when a ...

Page 96

PCI-to-PCI Bridge existing lock on the secondary bus could not have crossed the 21154; otherwise, the pending queued locked transaction would not have been queued. When the 21154 is able to complete a data transfer with the locked read ...

Page 97

When the 21154 receives a target abort or a master abort in response to a locked delayed transaction, the 21154 returns a target abort when the initiator repeats the locked transaction. The initiator must then deassert p_lock_l at the end ...

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...

Page 99

PCI Bus Arbitration The 21154 must arbitrate for use of the primary bus when forwarding upstream transactions, and for use of the secondary bus when forwarding downstream transactions. The arbiter for the primary bus resides external to the 21154, ...

Page 100

PCI-to-PCI Bridge low priority group. Using this example, if all requests are always asserted, the highest priority rotates among the masters in the following fashion (high priority members are given in italics, low priority members, in boldface type): B, ...

Page 101

Secondary Bus Arbitration Using an External Arbiter The internal arbiter is disabled when the secondary bus central function control pin, s_cfn_l, is pulled high. An external arbiter must then be used. When s_cfn_l is tied high, the 21154 reconfigures ...

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...

Page 103

General-Purpose I/O Interface The 21154 implements a 4-pin general-purpose I/O gpio interface. During normal operation, the gpio interface is controlled by device-specific configuration registers. In addition, the gpio interface can be used for the following functions: • During secondary ...

Page 104

PCI-to-PCI Bridge 10.2 Secondary Clock Control The 21154 uses the gpio pins and the msk_in signal to input a 16-bit serial data stream. This data stream is shifted into the secondary clock control register and is used for selectively ...

Page 105

The first eight bits contain the PRSNT#<1:0> signal values for four slots, and these bits control the s_clk_o<3:0> outputs. If one or both of the PRSNT#<1:0> signals are 0, that indicates that a card is present in the slot and ...

Page 106

PCI-to-PCI Bridge The eight least significant bits are connected to the PRSNT# pins for the slots. The next five bits are tied high to disable their respective secondary clocks because those clocks are not connected to anything. The next ...

Page 107

Clocks This chapter provides information about the 21154 clocks. 11.1 Primary and Secondary Clock Inputs The 21154 implements a separate clock input for each PCI interface. The primary interface is synchronized to the primary clock input, p_clk, and the ...

Page 108

PCI-to-PCI Bridge The rules for using secondary clocks are: • Each secondary clock output is limited to one load. • One of the secondary clock outputs must be used for the 21154 s_clk input. • Intel recommends using an ...

Page 109

Operation Some versions of the 21154 support 66 MHz operation. Signal config66 must be tied high on the board to enable 66 MHz operation and to set the 66 MHz Capable bit in the Status register and Secondary ...

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...

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PCI Power Management 1 The 21154 incorporates functionality that meets the requirements of the PCI Power Management Specification, Revision 1.0. These features include: • PCI power management registers using the enhanced capabilities port (ECP) address mechanism • Support for ...

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Reset This chapter describes the primary interface, secondary interface, and chip reset mechanisms. 14.1 Primary Interface Reset The 21154 has one reset input, p_rst_l. When p_rst_l is asserted, the following events occur: • The 21154 immediately tristates all primary ...

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PCI-to-PCI Bridge 14.3 Chip Reset The chip reset bit in the diagnostic control register can be used to reset the 21154 and the secondary bus. When the chip reset bit is set, all registers and chip state are reset ...

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Configuration Space Registers This chapter provides a detailed description of the 21154 configuration space registers. The chapter is divided into three sections: configuration registers, and Section 15.3 describes the configuration register values after reset. The 21154 configuration space uses ...

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PCI-to-PCI Bridge Figure 22 shows a summary of configuration space: Figure 22. 21154 Configuration Space Map 31 Device ID Primary Status Reserved Secondary Latency Timer Secondary Status Memory Limit Address Prefetchable Memory Limit Address I/O Limit Address Upper 16 ...

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Vendor ID Register—Offset 00h This section describes the vendor ID register. Dword address = 00h Byte enable p_cbe_l<3:0> = xx00b Dword Bit Name 15:0 Vendor ID 15.1.2 Device ID Register—Offset 02h This section describes the device ID register. Dword ...

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PCI-to-PCI Bridge Dword Bit Name I/O space 0 enable Memory 1 space enable 2 Master enable Special cycle 3 enable Memory write 4 and invalidate enable VGA snoop 5 enable 110 R/W Description Controls the 21154’s response to I/O ...

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Dword Bit Name Parity error 6 response Wait cycle 7 control SERR# 8 enable Fast back-to- 9 back enable 15:10 Reserved 15.1.4 Primary Status Register—Offset 06h This section describes the primary status register. These bits affect the status of the ...

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PCI-to-PCI Bridge Dword Bit Name 66-MHz 21 capable 22 Reserved Fast back-to- 23 back capable Data parity 24 detected DEVSEL# 26:25 timing Signaled 27 target abort Received 28 target abort Received 29 master abort Signaled 30 system error Detected ...

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Programming Interface Register—Offset 09h This section describes the programming interface register. Dword address = 08h Byte enable p_cbe_l<3:0> = xx0xb Dword Bit Name Programming 15:8 interface 15.1.7 Subclass Code Register—Offset 0Ah This section describes the subclass code register. Dword ...

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PCI-to-PCI Bridge 15.1.10 Primary Latency Timer Register—Offset 0Dh This section describes the primary latency timer register. Dword address = 0Ch Byte enable p_cbe_l<3:0> = xx0xb Dword Bit Name Master 15:8 latency timer 15.1.11 Header Type Register—Offset 0Eh This section ...

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Secondary Bus Number Register—Offset 19h This section describes the secondary bus number register. This register must be initialized by configuration software. Dword address = 18h Byte enable p_cbe_l<3:0> = xx0xb Dword Bit Name Secondary bus 15:8 number 15.1.14 Subordinate ...

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PCI-to-PCI Bridge Dword Bit Name Secondary 31:24 latency timer 15.1.16 I/O Base Address Register—Offset 1Ch This section describes the I/O base address register. This register must be initialized by configuration software. Dword address = 1Ch Byte enable p_cbe_l<3:0> = ...

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Dword Bit Name I/O limit 15:12 address <15:12> 15.1.18 Secondary Status Register—Offset 1Eh This section describes the secondary status register. These bits reflect the status of the the 21154 secondary interface. W1TC indicates that writing 1 to that bit sets ...

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PCI-to-PCI Bridge Dword Bit Name Received target 28 abort Received master 29 abort Received system 30 error Detected parity 31 error 15.1.19 Memory Base Address Register—Offset 20h This section describes the memory base address register. This register must be ...

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Dword Bit Name 19:16 Reserved Memory limit address 31:20 <31:20> 15.1.21 Prefetchable Memory Base Address Register—Offset 24h This section describes the prefetchable memory base address register. This register must be initialized by configuration software. Dword address = 24h Byte enable ...

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PCI-to-PCI Bridge Dword Bit Name 19:16 64-bit indicator Prefetchable memory 31:20 limit address <31:20> 15.1.23 Prefetchable Memory Base Address Upper 32 Bits Register—Offset 28h This section describes the prefetchable memory base address upper 32 bits register. This register must ...

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Dword Bit Name Upper 32 prefetchable 31:0 memory limit address <63:32> 15.1.25 I/O Base Address Upper 16 Bits Register—Offset 30h This section describes the I/O base address upper 16 bits register. Dword address = 30h Byte enable p_cbe_l<3:0> = xx00b ...

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PCI-to-PCI Bridge Dword Bit Name 15:0 Subsystem vendor ID R/W 15.1.28 ECP Pointer Register—Offset 34h This section describes the ECP pointer register. Dword address = 34h Byte enable p_cbe_l<3:0> = xx00b Dword Bit Name 7:0 ECP_PTR 31:8 Reserved 15.1.29 ...

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Dword Bit Name 15:8 Interrupt pin 15.1.31 Bridge Control Register—Offset 3Eh This section describes the bridge control register. This register must be initialized by configuration software. Dword address = 3Eh Byte enable p_cbe_l<3:0> = 00xxb Dword Bit Name Parity error ...

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PCI-to-PCI Bridge Dword Bit Name 19 VGA enable 20 Reserved Master abort 21 mode Secondary 22 bus reset Fast back-to- 23 back enable 124 R/W Description Modifies the 21154’s response to VGA-compatible addresses. When 0: VGA transactions are ignored ...

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Dword Bit Name Primary 24 master timeout Secondary 25 master timeout Master 26 timeout status Master timeout 27 SERR# enable 31:28 Reserved 15.1.32 Capability ID Register—Offset DCh This section describes the capability ID register. (Implemented in the 21154–AB and later ...

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PCI-to-PCI Bridge 15.1.33 Next Item Ptr Register—Offset DDh This section describes the next item ptr register. (Implemented in the 21154–AB and later revisions only. In the 21154–AA, this register is reserved.) Dword address = DCh Byte enable p_cbe_l<3:0> = ...

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Power Management Control and Status Register—Offset E0h This section describes the power management control and status register. (Implemented in the 21154–AB and later revisions only. In the 21154–AA, this register is reserved.) Dword address = E0h Byte enable p_cbe_l ...

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PCI-to-PCI Bridge Dword Bit Name 21:16 Reserved 22 B2_B3 23 BPCC_En 15.1.37 Data Register — Offset E3h This section describes the data register. Dword address = E0h Byte enable p_cbe_l<3:0> = 0xxxb Dword Bit Name 31:24 Data 15.2 Device-Specific ...

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Dword Bit Name 0 Reserved Memory write 1 disconnect control 3:2 Reserved Secondary bus 4 prefetch disable Live insertion 5 mode 7:6 Reserved Datasheet R/W Description R Reserved. Returns 0 when read. Controls when the 21154 target, disconnects ...

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PCI-to-PCI Bridge 15.2.2 Diagnostic Control Register—Offset 41h This section describes the diagnostic control register. W1TR indicates that writing 1 in this bit position causes a chip reset to occur. Writing 0 has no effect. Dword address = 40h Byte ...

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Event Disable Register—Offset 64h This section describes the p_serr_l event disable register. Dword address = 64h Byte enable p_cbe_l<3:0> = xxx0b Dword Bit Name 0 Reserved Posted write parity 1 error Posted write 2 nondelivery Target abort during ...

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PCI-to-PCI Bridge Dword Bit Name Delayed write 5 nondelivery Delayed read—no data 6 from target 7 Reserved 15.2.5 gpio Output Data Register—Offset 65h This section describes the gpio output data register. Dword Address = 64h Byte enable p_cbe_l<3:0> = ...

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Output Enable Control Register—Offset 66h This section describes the gpio output enable control register. Dword Address = 64h Byte enable p_cbe_l<3:0> = x0xxb Dword Bit Name GPIO output 19:16 enable write-1-to- clear GPIO output 23:20 enable write-1-to- set ...

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PCI-to-PCI Bridge Dword Bit Name Slot 0 clock 1:0 disable Slot 1 clock 3:2 disable Slot 2 clock 5:4 disable Slot 3 clock 7:6 disable Device 1 8 clock disable Device 2 9 clock disable Device 3 10 clock ...

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Dword Bit Name Device 5 12 clock disable The 21154 13 clock disable 15:14 Reserved 15.2.9 p_serr_l Status Register—Offset 6Ah This section describes the p_serr_l status register. This status register indicates the reason for the 21154’s assertion of p_serr_l. Dword ...

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PCI-to-PCI Bridge Dword Bit Name Delayed write 5 nondelivery Delayed 6 read—no data from target Delayed 7 transaction master timeout 15.3 Configuration Register Values After Reset Table 36 lists the value of the 21154 configuration registers after reset. Reserved ...

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Table 36. Configuration Register Values After Reset (Sheet Byte Address Register Name 26—27h Prefetchable memory limit address 28—2Bh Prefetchable memory base address upper 32 bits 2C—2Fh Prefetchable memory limit address upper 32 bits 30—31h I/O base address ...

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JTAG Test Port This chapter describes the 21154’s implementation of a joint test action group (JTAG) test port according to IEEE Std 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture. 16.1 Overview The 21154 contains a serial-scan test ...

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PCI-to-PCI Bridge 16.4 Instruction Register The 5-bit instruction register selects the test modes and features. The instruction register bits are interpreted as instructions, as shown in of the boundary-scan and bypass registers. Table 38 describes the 21154’s instructions. Table ...

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Boundary-Scan Register Cells Each boundary-scan cell operates in conjunction with the current instruction and the current state in the test access port controller state machine. The function of the BSR cells is determined by the associated pins, as follows: ...

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PCI-to-PCI Bridge Table 39. Boundary Scan Order (Sheet Pin Signal Name Number F2 s_gnt_l<3> — Vss G1 s_gnt_l<4> G4 s_gnt_l<5> G2 s_gnt_l<6> G3 s_gnt_l<7> H1 s_gnt_l<8> H2 s_rst_l J4 s_clk K1 s_cfn_l K2 gpio<3> K3 gpio<2> ...

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Table 39. Boundary Scan Order (Sheet Pin Signal Name Number W1 p_ad<24> Y2 p_cbe_l<3> Y1 p_idsel W4 p_ad<23> Y3 p_ad<22> AA1 p_ad<21> AA3 p_ad<20> Y4 p_ad<19> AB3 p_ad<18> AA4 p_ad<17> Y5 p_ad<16> AC4 Vss AB4 p_cbe_l<2> AA5 ...

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PCI-to-PCI Bridge Table 39. Boundary Scan Order (Sheet Pin Signal Name Number AB12 p_ad<4> AB13 p_ad<3> AA13 p_ad<2> Y13 p_ad<1> AA14 p_ad<0> AB14 p_ack64_l AC14 p_req64_l AA15 p_cbe_l<7> AB15 p_cbe_l<6> Y15 p_cbe_l<5> AC15 p_cbe_l<4> AA16 p_ad<63> ...

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Table 39. Boundary Scan Order (Sheet Pin Signal Name Number V22 p_ad<37> U23 p_ad<36> U20 p_ad<35> U22 p_ad<34> U21 Vss T23 p_ad<33> T22 p_ad<32> T21 p_par64 R22 config66 R21 msk_in P23 tdi P22 tdo N21 s_par64 M21 ...

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PCI-to-PCI Bridge Table 39. Boundary Scan Order (Sheet Pin Signal Name Number E20 s_ad<56> D21 s_ad<57> C22 s_ad<58> C23 s_ad<59> C21 s_ad<60> D20 s_ad<61> A21 s_ad<62> C20 s_ad<63> D19 s_cbe_l<4> A20 s_cbe_l<5> C19 s_cbe_l<6> A19 s_cbe_l<7> ...

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Table 39. Boundary Scan Order (Sheet Pin Signal Name Number A11 s_lock_l C10 s_stop_l B10 s_devsel_l A10 s_trdy_l C9 s_irdy_l — Vss B9 s_frame_l D9 s_cbe_l<2> A9 s_ad<16> C8 s_ad<17> B8 s_ad<18> A8 s_ad<19> B7 s_ad<20> D7 ...

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Electrical Specifications This chapter specifies the following electrical behavior of the 21154: • PCI electrical conformance • Absolute maximum ratings • dc specifications • ac timing specifications 17.1 PCI Electrical Specification Conformance The 21154 PCI pins conform to the ...

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PCI-to-PCI Bridge 17.3 DC Specifications Table 42 defines the dc parameters met by all 21154 signals under normal operating conditions. Table 42. DC Parameters Symbol Parameter V Supply voltage cc V Low-level input voltage il V High-level input voltage ...

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Figure 23 shows the ac parameter measurements for the p_clk and s_clk signals, and Table 44 specify p_clk and s_clk parameter values for clock signal ac timing. See also for a further illustration of signal timing. Unless otherwise noted, all ...

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PCI-to-PCI Bridge Table 44. 66 MHz PCI Clock Signal AC Parameters Symbol Parameter T p_clk,s_clk cycle time cyc T p_clk, s_clk high time high T p_clk, s_clk low time low p_clk, s_clk slew rate T Delay from p_clk to ...

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Table 45. 33 MHz PCI Signal Timing (Sheet Symbol Parameter Input setup time to CLK — bused T 1,2,3 su signals Input setup time to CLK—point-to- T 1,2,3 su(ptp) point T Input signal hold time from CLK ...

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PCI-to-PCI Bridge 17.4.3 Reset Timing Specifications Table 47 shows the reset timing specifications for p_rst_l and s_rst_l. Table 47. Reset Timing Specifications Symbol Parameter T p_rst_l active time after power stable rst T p_rst_l active time after p_clk stable ...

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Table 49. 66 MHz gpio Timing Specifications Symbol T vgpio T gon T goff T gsu gcval T gcyc T gsval T msu T mh 17.4.5 JTAG Timing Specifications Table 50 shows the JTAG timing specifications. Table ...

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Mechanical Specifications The 21154 is contained in an industry-standard 304-point 2-layer plastic ball grid array (PBGA) package, shown in Figure Figure 25. 304-Point 2-Layer PBGA Package Pin 1 Corner Pin 1 I. Chamfer 4 Places 22 23 ...

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PCI-to-PCI Bridge Table 51 lists the package dimensions in millimeters. Table 51. 304-Point 2-Layer PBGA Package Dimensions Symbol Dimension e Ball Pitch A Overall package height A Package standoff height 1 A Encapsulation thickness 2 b Ball diameter c ...

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Support, Products, and Documentation If you need technical support, a Product Catalog, or help deciding which documentation best meets your needs, visit the Intel World Wide Web Internet site: http://www.intel.com Copies of documents that have an ordering number and are ...

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