MC68839FE Motorola, MC68839FE Datasheet
MC68839FE
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... FDDI System Interface MOTOROLA MOTOROLA, 1993 FDDI User’s Manual MC68839 ...
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... MOTOROLA, 1993 ...
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... Ring State Registers.(RSR 3-20 3.3.7 FIFO Watermark Register (FWR 3-22 3.3.8 Limit Register (LMT 3-22 3.3.9 Receive Frame Type Registers (RFR 3-23 3.3.10 Receive Buffer Length Register (RBR 3-24 3.3.11 Header Length Register (HLR 3-25 MOTOROLA TABLE OF CONTENTS Title Section 1 Introduction Section 2 Functional Block Description Section 3 Registers MC68839 USER’S MANUAL Page ...
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... Set Local Memory Start Address Command . . . . . . . . . . . . . . . . 5-12 5.2.2.4 Using Define and Set Ring Commands . . . . . . . . . . . . . . . . . . . . 5-13 5.2.2.5 Stop Transmit Ring Command 5-13 5.2.2.6 Read Ring Parameters Command 5-14 5.2.2.7 Read Ring Parameters Indication . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.2.2.8 Ring Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 iv Title Section 4 Signal Descriptions Section 5 Commands and Indications MC68839 USER’S MANUAL Page Number MOTOROLA ...
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... FSI Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.2.1 FDDI Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.2.2 Example Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6.2.3 Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6.2.4 Descriptor Rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6.2.5 Destination Rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6.2.5.1 Buffer Descriptor Ring States . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 6.2.5.1.1 State Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 6.2.5.1.2 State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 6.3 Transmission Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 6.3.1 Transmit Commands in Rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 6.3.2 Linked Ring Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 MOTOROLA Title Section 6 Functional Operation MC68839 USER’S MANUAL Page Number v ...
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... Port CNTL Signals 8-3 8.2.3 ABORT Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.2.4 NOP Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.3 Port Chip Select Signals 8-5 8.4 Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.4.1 Port Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.4.2 Interport Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.4.3 Port Operational Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.5 Programmed I/O Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.5.1 Programmed I/O Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 8.6 Functional Port Operation Examples . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 vi Title Section 7 Section 8 Port Operation MC68839 USER’S MANUAL Page Number MOTOROLA ...
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... REJECT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 10.9 JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 11.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.2 Pin Assignments 11-2 11.2.1 Pin Grid Array (PGA 11-2 11.2.2 Ceramic Surface Mount (CQFP 11-3 11.3 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 MOTOROLA Title Section 9 Boundary Scan Section 10 Electrical Specifications Section 11 Ordering Information and Mechanical Data Appendix A Bus Control Logic Example Appendix B System Configurations MC68839 USER’ ...
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... Ring Memory Structure and the FSI Implementation D.1 Ring Memory Structure: General Discussion . . . . . . . . . . . . . . . . . . . D-1 E.1 Operational Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1 E.1.1 Parity Treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1 E.1.1.1 Parity Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1 E.1.1.2 Transmit Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1 E.1.1.3 Buffer Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-2 E.1.1.4 Directly Accessed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-2 E.1.2 First or Last Bit Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-3 viii Title Appendix C Performance Requirements Appendix D Appendix E Error Discussion and Reference MC68839 USER’S MANUAL Page Number MOTOROLA ...
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... Figure Number 1-1 Motorola FDDI Chip Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 2-1 Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 3-1 Internal and Common Registers 3-2 4-1 FSI Pinout 4-1 6-1 Direct Transmission and Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6-2 Extended Local Memory Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6-3 Direct and Expanded Local Memory Options 6-3 6-4 Dual Ports with Local Memory Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6-5 Memory to Memory DMA ...
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... MC68020 Bus Control Logic Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 B-1 Basic Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 B-2 Basic Configuration With Separate Node Processor . . . . . . . . . . . . . . . . . B-2 B-3 Basic Configuration with Local Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3 B-4 Local Memory with Separate Node Processor . . . . . . . . . . . . . . . . . . . . . . B-4 B-5 Slave Configuration With 64-Bit Data B-4 B-6 64-Bit Data With FSI DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5 x Title M68020 USER’S MANUAL Page Number MOTOROLA ...
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... Table Number 3-1 Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-2 FSI Indirect Registers 3-14 3-3 Ring Status Register Bit Values for Ring States . . . . . . . . . . . . . . . . . . . . . 3-21 5-1 FIRST and LAST Bit Settings 5-3 5-2 L(Local) and I(Indication) Bit Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 MOTOROLA LIST OF TABLES Title MC68839 USER’S MANUAL Page Number xi ...
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... MC68839 USER’S MANUAL MOTOROLA ...
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... SECTION 1 INTRODUCTION Motorola's FDDI chipset consists of an FDDI Clock Generator (FCG) timing and data recov- ery circuit, an Elasticity and Link Management (ELM) physical layer circuit, a Media Access Control (MAC) circuit, and an FDDI System Interface (FSI). The relationship of the circuits in this chipset is detailed in Figure 1. ...
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... For further examples of the different configurations that may be supported as well as more detailed explanations of the above configurations, refer to Appendix B. 1-2 MC68839 USER’S MANUAL MOTOROLA ...
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... FUNCTIONAL BLOCK DESCRIPTION The FDDI System Interface has four main blocks: the MAC Interface Unit, the Internal Mem- ory Array, the Port Control Unit, and the Main Control Unit. INTERNAL MEMORY ADDRESS CAM MOTOROLA . PORT A PORT B PORT CONTROL UNIT MAC INTERFACE UNIT CAM INTERFACE Figure 2-1 ...
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... The CAM has two access paths: the main control port, which includes address and data for setting up and controlling CAM entries, and the MAC interface, which takes data from the PHDAT pins in the ELM to be compared with the contents of the CAM. 2-2 MC68839 USER’S MANUAL MOTOROLA ...
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... Data FIFO. If the Receive Ring is Ready, the FSI reads Buffer Descriptors and transfers the data into the location pointed to by the buffer descriptor. The internal memory space reserved for each receive Ring is used for both the Internal Data FIFO and the Internal Ring FIFO. MOTOROLA MC68839 USER’S MANUAL Functional Block Description 2-3 ...
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... The accesses to the Ring are handled by the Port Control Unit which generates the address for each one of the rings in order to read commands and descriptors, and to write indica- tions. 2-4 MC68839 USER’S MANUAL MOTOROLA ...
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... Endian). According to its initial definition, each port is able to transfer the data between the system and internal memory according to the type of bus the FSI is connected to. (See Fig- ure A1 for an example connection to a Motorola 68020 bus.) It must be noted that the com- mand and indication definitions (bit and field assignment), and the addresses in the Ring Buffer Descriptors, are independent of the type of bus the FSI is connected to ...
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... Functional Block Description 2-6 MC68839 USER’S MANUAL MOTOROLA ...
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... The selection, and programming and/or reading of the registers is accomplished through either port. The FSI register set consists of two types: a directly addressable set and an internal, indi- rectly addressable set. The latter set is accessed through the FSI Control Register (FCR). MOTOROLA MC68839 USER’S MANUAL 3-1 ...
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... ADDRESS REGISTER PORT A ADDRESS REGISTER M PORT B U INTERRUPT MASK REG X PORT B PORT STATUS REG PORT B COMMAND REG PORT B COMMAND EXT REG PORT B INPUT/OUTPUT REG PORT B FSI CONTROL REG FIFO RECV WATER FRAME MARK TYPE REG REG INTERN S/W ERROR RESET STATUS REG MOTOROLA ...
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... Command Register 1010 Reserved 1011 Command Extension Register 1100 Interrupt Mask Register 2 1101 1110 1111 FSI Control Register MOTOROLA Table 3-1. Register Addresses Port B NOP Status Register 1 Data Register Data Register Input/Output Register Input/Output Register Address Register Reserved Interrupt Mask Interrupt Mask ...
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... Data access width (32- or 64-bits). The address will not be updated in the following situations: a. When reading the entries of the Ring, the Ring Read Address will not be incremented if the read entry does not belong to the FSI, (i.e., the Ring became Empty). 3-4 MC68839 USER’S MANUAL MOTOROLA ...
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... This will cause the CDN to be set. CDN is a real time status bit and is not affected by writing to the SR1. CRF—Control Register Free When the SR1 is read from one of the ports, the CRF bit indicates the status of the re- spective port FCR (FSI Control Register ). When the CRF bit is set, the FCR of the port MOTOROLA ...
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... The FSI has experienced an internal memory overrun causing the Memory Over- run (MOV) bit in IER to be set. This error may be caused by an incorrect definition of an internal FIFOs' Watermark. Therefore, the FSI parameter definitions should be checked and the FSI should be reinitialized. 3-6 MC68839 USER’S MANUAL MOTOROLA ...
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... RNR(5-0—Ring Not Ready Each RNR bit is set when any condition in the FSI causes the ring to become Not Ready, even if the ring is currently Not Ready. These bits are sticky bits and must be cleared by the host. MOTOROLA MC68839 USER’S MANUAL Registers 3-7 ...
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... Each DNR bit is set when its Destination Ring has changed its state from Ready to Empty state. 3 INT2 INT1 INT0 DRE7 DRE6 MC68839 USER’S MANUAL DRE3 DRE2 DRE1 DRE0 DNR3 DNR2 DNR1 DNR0 MOTOROLA 0 ...
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... When the REE(i) and RER(i) are both set, an interrupt is generated. RXE(5-4)—Receive Complete Interrupt Enable When the RXE(i) and RXC(i) are both set, an interrupt is generated. RCCE(5-0)—Ring Command Complete Interrupt Enable When the RCCE(i) and RCC(i) are both set, an interrupt is generated. MOTOROLA ...
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... On bus accesses the IOR could be read and used as the upper 32 bits of address as desired. 3- INE2 INE1 INE0 DREE7 DREE6 MC68839 USER’S MANUAL DREE3 DREE2 DREE1 DREE0 DNRE3 DNRE2 DNRE1 DNRE0 MOTOROLA 0 ...
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... During a Ring FIFO Read operation, the TCN will indicate the number of bytes that the FSI expects to read from the Ring. d. The TCN has no meaning during a Ring Write operation. MOTOROLA TCN MC68839 USER’ ...
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... Command Register is set, (i.e., the previous command is done), and should be written prior to writing its associated command to the Command Register (CMR parity error occurs (indicated by the HER bit in the port's SR1) during the CER access, the CER should be rewritten prior to writing to the CMR. 3-12 MC68839 USER’S MANUAL MOTOROLA ...
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... Ring Ready (RDY) Destination Ring Ready (DRY) Signal Register (SIG) User Register (USR) Revision Register (REV) Internal Error Status Register (IER) Software Reset(SWR) DATA—Internal Control Register Data Data for a register write and returned data on a register read. MOTOROLA IRI 0 IRT B 8 ...
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... Ready Ready Reg 6 Reg 7 — — — — Port Con- Port Con- trol Reg A trol Reg B Maximum — — Rx Memory Space Reg 5 Signal Signal Signal Reg 5 Reg 6 Reg 7 Ring State Ring State Ring State Reg 5 Reg 6 Reg 7 — Software Reset MOTOROLA ...
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... This bit defines the structure of the data bus and the order of bytes inside the 32-bit or 64- bit data structures then the byte order is most significant byte first (Motorola or IBM style then the byte order is least significant byte first (Intel or Digital style). DW— ...
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... The port memory page length, in bytes, is specified in the following table. PMP(7:0) Length in Bytes 0000 0000 0000 0001 0000 0011 0000 0111 0000 1111 0001 1111 0011 1111 0111 1111 1111 1111 3-16 PMP 16 32 256 512 16k MC68839 USER’S MANUAL 0 MOTOROLA ...
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... When RPA is zero, the Ring entries are accessed through Port A. When RPA is set, the Ring entries are accessed through Port B. Note that a Ring may be assigned one Port space and its data may be assigned the other Port space. In 64-bit operation this bit should be zero. MOTOROLA ...
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... Channels (6,7) these registers define the Destination Ring Maximum Length and its Ring and Data assignment as shown in Figure 4-12 (similar to RPR RPE 0 3-18 Maximum Length in Bytes 128k 256k RPA RDA MC68839 USER’S MANUAL 128 256 512 16k 32k 64k 0 RML MOTOROLA ...
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... For example, with an RML set to 3, i.e., 64 bytes, using 32-bit transfers, a current Ring address of 1BF8 (hex) will be incremented to 1BFC (hex) and then on another increment will wrap to 1BC0 (hex). MOTOROLA Maximum Length in Bytes 128 256 512 16k ...
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... DRY bit is provided PER EX—Exists When EX is reset, this Ring does not exist in the system. 3- LPA 0 8K 16K 32K 64K 128K 256K 512K OER DRY STP RDY MC68839 USER’S MANUAL 2 0 LML EMP CPL MOTOROLA ...
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... Ring Ready control access, but a descriptor read access has not yet been performed. Also parity or operation error is detected during a descriptor read operation, the Ring is Empty (with no more valid descriptors), and the PER or OER is set in conjunction with the EMP bit zero, the other bits have no meaning. MOTOROLA STP RDY EMP ...
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... There are six Limit Registers, one for each Transmit and Receive Channel. The Limit regis- ter specifies the maximum number of frames allowed inside Local Memory Space for each channel The minimum number of frames is 1 (LMT= 000 0000) and the maximum value is 128 (LMT= 111 1111).. 3-22 FWM LMT MC68839 USER’S MANUAL 0 0 MOTOROLA ...
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... Bit # Bit Name MOTOROLA Frame Type Void frame SMT Frame MAC Frame LLC Asynchronous Frame LLC Synchronous Frames Other Frames Reserved Token Cycle End indication from MAC . This mode cannot be used when using split header operation with Not Im- mediate header indication ...
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... In 64-bit mode, the minimum allowed Receive Buffer Length is 128 bytes. Note that if the Receive Buffer Length Registers are used, the Header Length Register should not be programmed. 3-24 RBR Buffer Length 64 bytes 128 bytes 256 bytes 512 bytes 1K bytes 2K bytes 4K bytes 8K bytes MC68839 USER’S MANUAL 0 MOTOROLA ...
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... Included in the RMR value are both the Receive Internal Ring FIFO and the Receive Internal Data FIFO. The value for the Maximum Receive Memory Space is calculated as follows: Max_Receive_Memory_Space = (RMR +1)x32 bytes. Therefore the largest is 8K bytes (RMR = 255). The minimum value of RMR should be 10 (Max_Receive_Memory_Space = 352 bytes).. MOTOROLA HLR RMR MC68839 USER’S MANUAL Registers ...
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... When RMI is set, the MACIF receives an indication for frames which have been previously transmitted by this station. These indications are transferred to one of the Receive Rings according to its frame type. 3- TD1 TD0 TD7 TD6 RMI RAL RCM ROB/IHI MC68839 USER’S MANUAL RE5 RE4 MOTOROLA ...
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... Ring was already in the Ready state, the Ring Ready control will have no effect. There are six Ring Ready Registers. The Ring Ready Access is not allowed to be performed on a Ring that does not exist in the System. MOTOROLA MC68839 USER’S MANUAL Registers ...
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... When IFDDI=0 the FSI operates as stand alone device. When IFDDI=1 the FSI operates in the IFDDI device. MRV—Major Revision This field indicates the Major Revision Number of the FSI. SRV—Sub Revision 3- MRV MC68839 USER’S MANUAL SRV MOTOROLA ...
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... The FSI has detected a protocol handshake error between the MAC and the FSI during the reception of a frame. The MACIF will generate an RABORT to the MAC and will try to resynchronize with the MAC on the next frame. This error may be caused by some tem- porary problems (e.g., noise on control lines), therefore no special recovery functions are MOTOROLA ...
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... Mask Registers (IMR1 and IMR2) are unaffected by Software Reset. The CRF bit of Status Register 1 will be set when the Software Reset has been completed. This will gen- erate an interrupt if the CFE bit of Interrupt Mask Register 1 (IMR1) is set. 3-30 MC68839 USER’S MANUAL MOTOROLA ...
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... Registers 3-31 MC68839 USER’S MANUAL MOTOROLA ...
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... Registers 3-32 MC68839 USER’S MANUAL MOTOROLA ...
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... ADDR16 LDADDR PHDAT7–PHDAT0 MATCHO REJECT RABORT RCCTL4–RCCTL0 RPATH7–RPATH0 RPRITY TABORT TXRDY TPRITY TPATH7–TPATH0 TXCTL1–TXCTL0 MOTOROLA . BINT MC68839 FSI Figure 4-1. FSI Pinout MC68839 USER’S MANUAL AINT APRTY3–APRTY0 ADATA31–ADATA0 ACS0 ACS1 AR/W ACNTL3–ACNTL0 AREQ3–AREQ0 ...
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... These lines should be asserted a set-up time before Chip Select asser- tion, and should remain stable at least hold time after Chip Select assertion. 4-2 AREQ(0) 1 Idle State 1 Read Cycle 0 Read Cycle with address on the same memory page 1 Write Cycle 0 Write Cycle with address on the same memory page MC68839 USER’S MANUAL MOTOROLA ...
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... CTL lines are not included in the parity generation. Transmit Control Signals (TXCTL1–TXCTL0) These CMOS-level output signals are used by the FSI to indicate the type of data transfer. The encoding of these signals is as follows: TXCTL(1:0) Transfer Type MOTOROLA Filler Tx_Start Tx_Data Tx_End MC68839 USER’S MANUAL Signal Descriptions 4-3 ...
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... FIFO to store the information, if the data FIFO is disabled for reception the REJECT signal is asserted when doing a CAM or external recognition logic match. 4-4 Transfer Type Filler Start Data Data End Data Frame Status Token Cycle End Filler MC68839 USER’S MANUAL MOTOROLA ...
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... Source Address or Destination Address fields. When this signal is asserted, the received address belongs to this station's set of long addresses and the appropriate ac- tions should be taken by the MAC. The user must supply a pull-up resistor for this signal to operate correctly. MOTOROLA or left connected to the MC68838 ADDR16 signal. CC MC68839 USER’S MANUAL ...
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... When TRST changes from '0' to '1', the TMS must be held at '1' in order to ensure deterministic operation of the Test Logic. If separate JTAG control of this signal is not required, i.e., JTAG is not implemented, then this signal should be tied to RESET or to GND. 4 MC68839 USER’S MANUAL MOTOROLA ...
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... These indications are then written back to the Buffer Descriptor Ring or to the Command Register. For transmit and receive frames, the frame indication status is placed inside the last buffer descriptor. No other descriptors will include frame status infor- mation. MOTOROLA MC68839 USER’S MANUAL 5-1 ...
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... However, the entire field must be provided when the command is issued as a Descriptor Ring entry. All indications are written out as 64-bit entities. When a 64-bit com- mand is issued directly to the FSI, bits 31:0 are first written to the CER and then bits 64:32 are written to the CMR. 5 MC68839 USER’S MANUAL MOTOROLA ...
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... Table 5-1. FIRST and LAST Bit Settings FIRST Bit MOTOROLA LAST Bit Condition 1 Single Buffer Frame 0 First Buffer of a Multiple Buffer Frame 1 ...
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... FCR accesses the user can prepare an initialization ring which includes control register write commands. 5 MC68839 USER’S MANUAL IRT IRI 32 16 DATA 0 MOTOROLA ...
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... C—Change Port When C is reset, the external memory space has the same port assignment as indicated by the RPA bit in the PER register. When C is set, the external memory space is assigned to the port opposite that indicated by the RPA bit in the PER register. MOTOROLA ...
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... External Address High External Address Low MC68839 USER’S MANUAL MOTOROLA ...
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... If there are multiple Resouce Request Commands pending, the resource, when released, will be assigned according to the priority of the requesting channels then MOTOROLA ...
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... Since the address wraps at the modulo value given in the Ring Parameter Reg- ister RPR (section 3.3.3), the Descriptor Ring memory block is defined as the pointer address modulo the RML value in the RPR. 5 MC68839 USER’S MANUAL MOTOROLA ...
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... Empty. Ring#— Ring Number (0-5) Ring number 5), of the Ring to be defined. The Ring number cannot be the Ring num- ber of the Ring containing the command. Ring Read Pointer Low Ring Read Pointer Low Order start address in external memory. MOTOROLA ...
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... If the user had defined the transmit ring with the option to provide an indication after the transfer of data from system to local memory, then the transmit indication has meaning only for that transfer. In this case the success or failure of transmission of data from local memory to the network will not be reported.. 5-10 MC68839 USER’S MANUAL MOTOROLA ...
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... The region of the address space used for the ring does not necessarily begin with the Ring Pointer. Rather, the region is defined such that the most significant bits of the pointer remain constant. For example: Ring Pointer = 3445 4FF8 and an RML = 128 bytes (0100) provides an address range of 3445 4F80 to 3445 4FFC. MOTOROLA ...
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... For example: Local Memory Start Address= 9454 3578 and an LML = 32K bytes (010) provides an address range of 9454 0000 to 9454 7FFC. 5- Local Memory Start Address High MC68839 USER’S MANUAL Ring MOTOROLA ...
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... When a frame is currently being transmitted from this Ring, its transmission is com- pleted. If the current operation is a DMA data move, the transfer is continued until the end of the frame more frames are transmitted from this Ring, even if they are already inside the FSI internal memory. MOTOROLA ...
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... This command may be issued at any time by the host processor through one of the Ports' Command Registers or may be placed inside one of the Transmit Buffer Descriptors Rings. 5- MC68839 USER’S MANUAL Ring MOTOROLA ...
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... Ring Read Pointer Low Order next descriptor read address in external memory. Ring Read/Write Pointer High This is the High Order address bits for the Read and Write pointer addresses. Ring Write Pointer Low Ring Write Pointer Low Order next descriptor write address in external memory.. MOTOROLA ...
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... Transmit Buffer Descriptor Ring entries FIRST LAST Tog Mode Buffer Length Buffer Address High Buffer Address Low MC68839 USER’S MANUAL Ring MOTOROLA ...
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... These parameters are called the Packet Header. They are transparent to the FSI and are forwarded to the MAC. They are fully described in the MC68838 MAC Specification. MOTOROLA MC68839 USER’S MANUAL Commands and Indications ...
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... In this case the success or failure of transmission of data from local memory to the network will not be reported.. 5- Unchanged Unchanged Unchanged MC68839 USER’S MANUAL PER mory MOTOROLA ...
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... INFO This field is transferred into the DMA indication on the Destination side. It may be used in order to attach transferred data. If DMA frame is formed from several buffers, the INFO in the last descriptor is used. MOTOROLA Buffer Length Buffer Address High Buffer Address Low MC68839 USER’ ...
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... Transfer from the Data FIFO to an Destination Buffer was aborted either by a Port Operation Error or an Abort Access or Discard Frame (Descriptor with D=1) 111 Parity error during data transfer from the Data FIFO to a Destination Buffer 5- Unchanged Unchanged Unchanged MC68839 USER’S MANUAL PER MOTOROLA ...
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... D—Discard Frame set then the rest of current DMA frame is discarded, that is, the DMA transfer is aborted for this frame. MOTOROLA 0 37 Buffer Length Buffer Address High ...
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... This field is a copy of the same field in last source descriptor. Cmd This field is a copy of the same (bits 47,46,45) field in last source descriptor. Frame Length The length of entire frame. modulo 8K. 5- Frame Length Unchanged Unchanged MC68839 USER’S MANUAL 48 INFO MOTOROLA ...
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... Parity error during data transfer from a Source memory to an Internal memory 100 Transfer from an Internal memory to a Destination Buffer was aborted either by a Port Opera- tion Error or an Abort Access or Discard Frame (Descriptor with D=1). 111 Parity error during data transfer from an Internal memory to a Destination Buffer MOTOROLA ...
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... Indications are mixed with DMA Commands the indications are indistinguishable in the case of error Indication The indication field is a copy of the same field in Make Indication command. 5- Indication Indication Unchanged Unchanged MC68839 USER’S MANUAL 48 Indication Indication MOTOROLA ...
Page 83
... The address of the first byte in the associated data buffer. Note that this address must be aligned on longword (64-bit) boundaries for 64-bit accesses and aligned to 32-bit bound- aries for 32-bit accesses. D—Discard Frame set then the rest of current Receive frame is discarded. MOTOROLA 0 37 Buffer Length Buffer Address High ...
Page 84
... CF—C Flag F0—First Additional Flag F1—Second Additional Flag DA—Destination Address Match Field 11 Local Match 01 External CAM Match 10 Promiscuous reception 00 Reserved Frame Length 5- FNUM Frame Length Unchanged Unchanged MC68839 USER’S MANUAL MOTOROLA ...
Page 85
... F—First Bit 0 for a multiple buffer frame and 1 for a single buffer frame. OE—Overrun Error Overrun Error in the FSI PE—Parity Error Detected by the MACIF on the receive path. FNUM—Number of Valid Flags EF—E Flag AF—A Flag MOTOROLA FNUM ...
Page 86
... IER register, bits this indication will be zero and the STT field is not valid nor meaningful. The FNUM, EF, AF, CF, F0, F1 fields are taken from Frame Status information received from MAC. This is further described in the MC68838 (MAC) doc- ument.. 5-28 NOTES: MC68839 USER’S MANUAL MOTOROLA ...
Page 87
... OE—Overrun Error Overrun Error in the FSI PE—Parity Error Detected by the MACIF on the receive path. FNUM—Number of Valid Flags EF—E Flag AF—A Flag CF—C Flag F0—First Additional Flag F1—Second Additional Flag MOTOROLA FNUM 0 ...
Page 88
... If the received data had already been partially or com- pletely transferred and an error occurs the result will be a Receive Error Indication as described above 5- Unchanged Unchanged MC68839 USER’S MANUAL MOTOROLA ...
Page 89
... CF—C Flag F0—First Additional Flag F1—Second Additional Flag SA—Source Address Match Field 11 Local match 10 External Match 01 Bridge Match 00 The MAC aborted the frame prior match.. Refer to the MAC MC68838 manual on Frame Status indications.. MOTOROLA FNUM 0 Unchanged Unchanged MC68839 USER’ ...
Page 90
... CAM at CAM_ID.. Bit 47 is the I/G bit. 5- Unchanged Unchanged CAM Entry CAM Entry CAM Entry MC68839 USER’S MANUAL Frame Counter CAM_ID MOTOROLA ...
Page 91
... V—Valid 0 for invalid entry, 1 for a valid entry. CAM_ID—FSI CAM entry address. CAM Entry—Address Entry 48-bit address entry inside the CAM at CAM_ID. Bit 47 is the I/G bit. MOTOROLA ...
Page 92
... CAM Entry (47–32) CAM Entry (31–16) CAM Entry (15– Unchanged Unchanged Unchanged MC68839 USER’S MANUAL CAM_ID MOTOROLA ...
Page 93
... DMA engine and transfer data from one memory area to another This chapter serves as an overview for the data DMA functionality and as an introduction to the data types used with the Motorola FSI. The chapter on Programming the FSI has more detailed information on realizing the functionality introduced here. ...
Page 94
... It is possible to expand the size of the latency buffer through the use of external memory using a local memory option. Such an implementation is shown in figure 6-5. Figure 6-2. Extended Local Memory Option 6-2 . SYSTEM MEMORY 4 1 LOCAL FSI MEMORY FDDI INTERFACE MC68839 USER’S MANUAL MOTOROLA ...
Page 95
... All of the transmit and receive channels may make use of the expanded memory and even mixed use is possible. Figure 6-6 shows two channels using the expanded memory and two channels using the direct transfer method. Figure 6-3. Direct and Expanded Local Memory Options MOTOROLA . SYSTEM MEMORY 2 ...
Page 96
... Figure 6-7 shows the assignment of Tx ring 1 and Rx ring 5 on the System memory port, implemented perhaps due to a low bus latency. Tx Ring 3 and Rx ring 4 are assigned to the local bus using direct transfer. 6-4 . SYSTEM MEMORY 5 LOCAL MEMORY FSI 3 4 FDDI INTERFACE MC68839 USER’S MANUAL 1 MOTOROLA ...
Page 97
... For example, host processors on one port may use this facility to down- load data or code to another processor's memory space on the other port. Any transmit ring (0-3), not using local memory, or Command channel (6-7) may be used for DMA operations as well as frame data transmission to the FDDI interface. MOTOROLA . SYSTEM MEMORY 3 ...
Page 98
... FCS, ED and FS fields as well as the interpacket Idle stream. The user must supply the FC, DA, SA and INFO fields. Bridge applications have the option of supplying the CRC for the FCS field and suppressing the CRC generation by the MAC for data integrity. 6-6 SA INFO MC68839 USER’S MANUAL FCS ED FS MOTOROLA ...
Page 99
... FCS field and re-transmit the data frame without re-computing the FCS. Only 48-bit addresses are shown here. The user must note that the FSI does not inter- pret any of the data fields! 10A0 Figure 6-7. Example Memory Data Organization MOTOROLA . FRAME #1 FRAME #2 FC ...
Page 100
... For data transmission the frame data may be described by up to16 descriptors. A frame which is received data structure which is the destination of a memory to memory trans- fer, may require the use of an indefinite number of descriptors and buffers. Thus a very large receive frame may be characterized by a large number of small buffers. 6-8 MC68839 USER’S MANUAL MOTOROLA ...
Page 101
... Ring Buffer Descriptor FIFO until either the internal Ring Buffer Descriptor FIFO is full (20 entries) or until no other valid external Ring Buffer Descriptors exist. The internal copy of the descriptor Ring reduces bus accesses especially during crit- ical data transfers. This is illustrated in Figure 6-12. MOTOROLA . DATA BUFFERS F L ...
Page 102
... Note that, if frames are placed into a higher priority Transmit Descriptor Ring while a lower priority Transmit Descriptor Ring is being serviced, then the frames in the higher priority 6-10 . EXTERNAL MEMORY INTERNAL MEMORY CTP - CURRENT TRANSFER POINTER TXP - TRANSMIT POINTER RING FIFO MC68839 USER’S MANUAL MOTOROLA ...
Page 103
... DMA data transfers. SYSTEM "A" MEMORY SYSTEM "B" MEMORY DESTINATION RING DATA FIFO FSI Figure 6-10. Source and Destination Descriptor Rings MOTOROLA . SOURCE RING DESTINATION RING RING FIFO RING FIFO (a) MC68839 USER’S MANUAL Functional Operation SYSTEM "A" MEMORY ...
Page 104
... Complete The Ring is empty. All the entries have been executed by the FSI and all the indications have been written back to the Ring. Only when the Ring is in the Complete or Stopped state can the Ring be redefined. 6-12 NOTE MC68839 USER’S MANUAL MOTOROLA ...
Page 105
... D. A Ring Ready control access (access to the FCR register) has been done by the host. E. All indications have been written back to the Ring. F. The Ring Stop command has been executed Parity or Operational Error has been detected during a descriptor read. H. The Ring Reset command has been executed. MOTOROLA MC68839 USER’S MANUAL Functional Operation 6-13 ...
Page 106
... MAC and the FSI Transmis- sion Logic, the FSI Main Controller, and the FSI Port Control working with the system Bus Control Logic. 6- READY EMPTY MC68839 USER’S MANUAL STOPPED COMPLETE MOTOROLA ...
Page 107
... F. The FDDI System Interface transmits the data onto the network. G. The FSI generates indications and writes them over the buffer descriptors or to anoth- er location as programmed enabled, an interrupt is generated. I. The processor reads the indications. MOTOROLA . A B MEMORY I ...
Page 108
... Ring 0 consists of three Define Ring commands. The first two commands point to ring struc- tures for Ring 1 which the FSI will act on. The third Define Ring command points to a null ring structure and is used merely to insure that an interrupt is provided when Ring 1(b) is complete. 6-16 MC68839 USER’S MANUAL MOTOROLA ...
Page 109
... RING 0 DEFINE RING 1 DEFINE RING 2 DEFINE RING 3 NOT VALID Figure 6-13. Linked Transmission Rings MOTOROLA . RING 1.A FR #0.FIRST FR #0.MID FR #0.LAST FR_1 NOT VALID RING 1.B FR #0.FIRST FR #0.LAST FR_1 FR_2 NOT VALID RING 1.C NOT VALID MC68839 USER’S MANUAL Functional Operation FR #0 FIRST BUFFER MID BUFFER ...
Page 110
... Transmit Com- mands. RING FR_#3 RING LENGTH = 32 (4 ENTRIES) RING FR #0 RING LENGTH = 8 (1 ENTRY) Figure 6-14. Endless Repeat of Frame Data Transmission 6-18 . MC68839 USER’S MANUAL MOTOROLA ...
Page 111
... F. The FSI writes a Receive Indication into all of the Receive Buffer Descriptors of the frame. The information on the status of the entire frame is contained in the last Re- ceive Buffer Descriptor of the frame enabled, an interrupt is generated. H. The processor then reads this Receive Indication. I. The data buffers may now be read by the processor. MOTOROLA . ...
Page 112
... This portion is defined by the length of the Receive Data Buffer in the appropriate Ring as specified by the FC of the frame being received. Trailing flags and a complete frame status indication, including the total frame length and the CRC status, are gen- erated by the FSI and put into the frame's indication. 6-20 MC68839 USER’S MANUAL MOTOROLA ...
Page 113
... FSI internal memory. Some possible data flow configurations with local Memory are shown in Fig 7-15. In this fig- ure two channels are defined to operate in a Normal mode (1,5) and two other channels are operating in a Local Memory Mode (3,4). MOTOROLA MC68839 USER’S MANUAL Functional Operation 6-21 ...
Page 114
... FSI requirements for access. The FSI sees the Local Memory as six large cyclic buffers. Each one of the areas is assigned to one FSI channel that operates in "Local Mem- ory mode" 6-22 . SYSTEM MEMORY LOCAL FSI MEMORY FDDI INTERFACE MC68839 USER’S MANUAL 1 MOTOROLA ...
Page 115
... Limit Register (LMT). The FSI will stop receiving frames for a Receive channel when the number of frames waiting to be transferred to the system memory in the Local Memory area of this channel reaches the programmed limit. Note, therefore, that an indication for "Local Memory Area Full" is based on the number of MOTOROLA . ADDRESS 0000_0000 ...
Page 116
... The next and last step of the transmit process is to write the indications of the frame to the system memory (8). At this point, all the frame descriptors will be cleared from the inter- nal memory. 6-24 MC68839 USER’S MANUAL MOTOROLA ...
Page 117
... Normal Mode operation. The data will then be written into the Local Memory area assigned to the receive channel (2). When the entire frame has been received, a Frame Descriptor entry is generated by the FSI and stored inside the internal Intermediate Command FIFO of the receive Channel (3). MOTOROLA . SYSTEM MEMORY 2 1 INTERM ...
Page 118
... Either Single Mode should be used for the Transmit commands (bit 45 set Make Indi- cation command should be inserted before each DMA command that follows a Transmit command. 6-26 . SYSTEM MEMORY 6 INTERM. DATA FIFO 7 5 RING FIFO 2 DATA FIFO 1 FSI Figure 6-19. Receive Process MC68839 USER’S MANUAL INTERM. CMD FIFO MOTOROLA ...
Page 119
... The DMA operation is executed by the FSI as a result of a DMA command given through a Source Ring or through the Command Register. The DMA command format is similar to the Transmit Command and may be seen as a transmit operation directed to a destination memory space specified by the Destination Ring descriptors. MOTOROLA . SYSTEM "A" MEMORY CHANNEL #3 ...
Page 120
... When the entire frame has been transferred from the source to the destination, the indication is made and placed inside the last source descriptor. (8) All the indications waiting inside the Ring FIFO are written back to the Source Ring. 6-28 MC68839 USER’S MANUAL MOTOROLA ...
Page 121
... The FSI will transfer the data from a source memory space to a destination memory space through the Internal Data FIFO of the channel. This transfer is accomplished in quanta of 256 bytes. (5) Once one destination buffer has been used, its descriptor is turned into an indica- tion. MOTOROLA . SYSTEM MEMORY SOURCE RING 3 DATA ...
Page 122
... FSI will treat this first buffer as a whole frame). The remainder of the frame is directed to the Receive Channel selected by the FC of the frame 6-30 . HOST PROCESSOR SYSTEM MEMORY 3 CMD_A DATA FIFO 4 2 INTERM. CMD FIFO 6 MC68839 USER’S MANUAL FSI MOTOROLA ...
Page 123
... Because the FSI treats the Header buffer as a small frame, the Receive Complete status bit (RXC(4)) will be set when the indication of this buffer is written back to the Ring. This status bit in the SR1 will cause an interrupt (if enabled) which may actually be considered as an "Early Receive" interrupt when operating in Mode A. MOTOROLA . HEADER DATA ...
Page 124
... Functional Operation 6-32 MC68839 USER’S MANUAL MOTOROLA ...
Page 125
... Additionally, the bits of the PSR indicate both Ports are in the Idle state, the Interrupt Mask Registers are cleared which disables all interrupts. All the entries in the internal CAM are undefined and the user must initialize the ENTIRE CAM if the CAM feature used.. MOTOROLA Rings are not defined yet. No Ring is Complete. ...
Page 126
... MAC Interface Receive Control Register should be defined and enabled to specify the operation of the MAC Interface Receiver. Once RE4 or RE5 is set, data may be received and stored inside the internal memory which could lead to a receive 7-2 MC68839 USER’S MANUAL MOTOROLA ...
Page 127
... Since most busses are capable of emptying the internal FIFO very quickly, setting a low watermark means that the external bus will be requested repeatedly following from an emptying/filling cycle. MOTOROLA Initialization, Programming and Examples MC68839 USER’S MANUAL 7-3 ...
Page 128
... The total data space in a non-active state. Additional data space in an active state. The total control space in a non-active state. Additional control space in an active state. =============================== Total FSI internal memory required. MC68839 USER’S MANUAL MOTOROLA ...
Page 129
... Additionally, the average rate of trans- fer to the system from the FSI must also exceed the rate of reception on the FSI-MAC inter- face to allow for buffer and descriptor handling overhead. MOTOROLA Initialization, Programming and Examples MC68839 USER’S MANUAL ...
Page 130
... Initialization, Programming and Examples 7-6 MC68839 USER’S MANUAL MOTOROLA ...
Page 131
... Ring state becomes Ready again. The RRP is incremented within the limits defined by Ring Maximum Length (RML). The other transfer types occur based upon the information in the first transfer type, such as receive and transmit buffer pointers, or upon internal information such as current receive or transmit indication pointers. MOTOROLA MC68839 USER’S MANUAL 8-1 ...
Page 132
... The port will transition to this state when a Read operation (Descriptors or Tx DMA read) is required by the Main Controller. Transition "a" from the IDLE state is performed synchronously or asynchronously with the Chip Select sig- nal depending on the mode of port operation. 8-2 . IDLE MC68839 USER’S MANUAL B WRITE MOTOROLA ...
Page 133
... BCNTL(3:0), for each port when one of the Chip Selects is asserted as defined in figure 7- 1. The full address range for the CNTL lines is shown in figure 3-2, only the values directly associated with data transfer are explicated here: MOTOROLA MC68839 USER’S MANUAL Port Operation ...
Page 134
... Port. Therefore, an additional data access is required after the Abort access in order to complete the current data transfer operation. 8-4 . Read Port A Port A Port B NOP DTR(A) DTR(B) DTR(A) ADR(A) ADR(B) Reserved ADR(B) ADR(A) Reserved Abort MC68839 USER’S MANUAL Write Port B DTR(B) Reserved Reserved MOTOROLA ...
Page 135
... Active state will occur synchronously with the Chip Select line and may be sampled by the Bus Control Logic when the Chip Select line is negated. Note that this transition will take place only when the external Bus Control Logic performs a NOP access to the port. MOTOROLA MC68839 USER’S MANUAL Port Operation ...
Page 136
... For transmit or receive descriptor reads, the Ring state is changed to Empty with the Operation Error status bit set in the appropriate Ring State Register. The RNR and RER bits in the SR1 are set. 8-6 MC68839 USER’S MANUAL MOTOROLA ...
Page 137
... As in the case of data, the port may go to the Idle state after a number of indications. Additional attempts to read the indications are ignored by the FSI. When the last indication of a frame is transferred to the host, the Transmit Complete status bit in the SR1 is asserted. MOTOROLA MC68839 USER’S MANUAL Port Operation 8-7 ...
Page 138
... This mechanism may also be used to transmit other types of frames in addition to immediate frames. These frames may be of high priority or frames that do not properly belong in one of the four transmission rings. 8-8 MC68839 USER’S MANUAL MOTOROLA ...
Page 139
... R/W lines as indicated around the rising edge of chip select, are meant to emphasize that the FSI sam- ples the Control and R/W lines on Chip Select Assertion. MOTOROLA . BURST READ BURST READ ...
Page 140
... BURST READ BURST READ DATA_WR DATA_WR 0010 0010 DATA0 DATA1 ADDR_RD ADDR_RD ADDR_RD 1000 1000 1000 ADDR0 ADDR1 MC68839 USER’S MANUAL NEW READ IDLE DATA_WR DATA_WR 0010 0010 DATA2 DATA3 ADDR_RD 1000 ADDR2 ADDR3 MOTOROLA ...
Page 141
... The initial access is a New Read in which an address is presented followed by a single data transfer for that address, the Burst Read, and then another New Read cycle due to a change of page. MOTOROLA . IDLE ...
Page 142
... FSICLK CSx# REQ# Figure 8-8. Request Negation to Request Assertion in Asynchronous Mode 8-12 . NEW WRITE DATA_WR ADDR_RD 0010 0010 . Minimum 5 FSICLK cycles IDLE (1111) MC68839 USER’S MANUAL BURST WRITE NEW READ DATA_RD DATA_RD 0010 0010 REQ MOTOROLA ...
Page 143
... The JTAG technique of testing implemented in the FSI can detect many of the faults that testers currently address without the need for extensive bed-of-nails access and without the need of expensive test equipment, particularly for surface mount components. MOTOROLA MC68839 USER’S MANUAL 9-1 ...
Page 144
... Boundary Scan BOUNDARY SCAN REGISTER BYPASS REGISTER TDI INSTRUCTION DECODE SHIFT DATA UPDATE DATA RESET TMS TCK TAP CONTROLLER TRST Figure 9-1. JTAG Architecture Model 9-2 . MUX INSTRUCTION REGISTER SHIFT INSTRUCTION UPDATE INSTRUCTION RESET MC68839 USER’S MANUAL D FF TDO D MUX EN CLK MOTOROLA ...
Page 145
... The state machine is shown in the following figure where the value shown adjacent to each arc represents the value of the TMS signal sampled at the rising edge of the TCK. TEST LOGIC 1 RESET RUN-TEST/IDLE Figure 9-2. TAP Controller State Machine MOTOROLA . 1 SELECT-DR_SCAN 0 1 CAPTURE- SHIFT-DR ...
Page 146
... The Bypass Register consists of a single shift register stage that is connected between TDI and TDO when the BYPASS instruction is selected. When the TAP is in the Capture-DR state the Bypass Register is loaded with zero. 9-4 MC68839 USER’S MANUAL MOTOROLA ...
Page 147
... B_OEN is the Active Control of the BDATA(31:0) and BPRTY(3:0) lines for the EXTEST instruction where: B_OEN = 1 The Output Buffers of the lines mentioned above are in Active state. B_OEN = 0 The Output Buffers of the lines mentioned above are in Three-State. MOTOROLA MC68839 USER’S MANUAL Boundary Scan 9-5 ...
Page 148
... BDATA(21) I/O TTL 132 BDATA(22) I/O TTL 133 BDATA(23) I/O TTL 134 BDATA(24) I/O TTL 135 BDATA(25) I/O TTL 136 BDATA(26) I/O TTL 137 BDATA(27) I/O TTL 138 BDATA(28) I/O TTL 139 BDATA(29) I/O TTL 140 BDATA(30) I/O TTL 141 BDATA(31) I/O TTL 142 AINT OUT TTL 143 BINT OUT TTL MOTOROLA ...
Page 149
... Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or V 10.2 THERMAL CHARACTERISTICS Characteristic Thermal Resistance for PGA Thermal Resistance for CQFP MOTOROLA Symbol Value Unit V –0.3 to +7.0 V ...
Page 150
... C can be obtained from • JA) and can be neglected. INT and 273 MC68839 USER’S MANUAL Max Unit Vcc — 0.5 0.5 0 1.65@5.5V Watts 300@5. neglected): J I/O MOTOROLA (1) (2) ...
Page 151
... Values for thermal resistance presented in this document, unless estimated, were derived using the procedure described in Motorola Reliability Report 7843, “Thermal Resistance Measurement Method for MC68XX Micro component Devices,” and are provided for design purposes only ...
Page 152
... Note that rise and fall times are not measured 4. This timing is for low frequencies, for 25MHz limited to 3ns. 10-4 Min Max 80 — 40 — — — — — — 1,2 — 25 MC68839 USER’S MANUAL Unit MOTOROLA ...
Page 153
... FSI on the rising edge of BYTCLK. The FSI outputs and MAC in- puts operate in a similar fashion. BYTCLK T5 SYMCLK RPATH, RPRITY RCCTL TXRDY, TABORT, REJECT TPATH, TPRITY TXCTL, RABORT Figure 10-1. FSI Clocks and MAC Interface Timing MOTOROLA NOTE . T8A T9A T10 MC68839 USER’ ...
Page 154
... Min Max Unit 18 — — — — — — — — — — ns — — — — — — — — ns T22 T31 MOTOROLA ...
Page 155
... CNTL3–CNTL0 CSI R/W DATA31–DATA0 REQ3–REQ0 BCNTL3–BCNTL0 BCSx ACNTL3–ACNTL0 ACSx Figure 10-4. FSI Nonmultiplexed Two-Port Timing MOTOROLA T23 T24 T21 T26 T25 T27 T32 Figure 10-3. FSI Write Timing . T33 MC68839 USER’S MANUAL Electrical Specifications T22 T28 10-7 ...
Page 156
... BYTCLK SYMCLK T41 T42 LDADDR ADDR16 PHDAT MATCHO Figure 10-5. FSI-CAM Interface Timing 10-8 Min Max 1 0 — — — 3 — — — — . T43 T44 T46 T47 MC68839 USER’S MANUAL Unit T45 MOTOROLA ...
Page 157
... When REJECT is asserted, the FSI asserts RABORT to the MAC on the next rising edge of BYTCLK result, the MAC will supply the end data indication to the FSI. BYTCLK SYMCLK REJECT RABORT Figure 10-6. FSI REJECT/RABORT Timing MOTOROLA . MC68839 USER’S MANUAL Electrical Specifications 10-9 ...
Page 158
... TCK Negated to TDO Valid NOTE: 1. For every 10 pF Loading capacitance more than 50-pF, add 1 ns. TCK TDO TDI TMS DATA-OUT 10-10 Min Max 2 — 6 — 1 — 0 — 1 — T65 T63 T61 T62 T64 T66 Figure 10-7. JTAG Timing MC68839 USER’S MANUAL Unit MOTOROLA ...
Page 159
... ORDERING INFORMATION AND MECHANICAL DATA This section contains ordering information, pin assignments, and package dimensions for the MC68839 FSI. 11.1 ORDERING INFORMATION Package Type Pin Grid Array (PGA) Ceramic Surface Mount (CQFP) MOTOROLA Frequency Temperature 25 MHz 0– MHz 0–70 C MC68839 USER’S MANUAL ...
Page 160
... V CC ADATA12 ADATA11 GND ADATA16 ADATA14 ADATA13 ADATA18 ADATA15 ADATA20 ADATA23 ADATA21 ADATA17 BR/W ACNTL0 ADATA29 ADATA25 ADATA24 ADATA19 BCNTL0 ACNTL2 AR/W* ADATA28 ADATA26 ADATA22 BCNTL1 ACNTL3 ACNTL1 ADATA31 ADATA30 ADATA27 184 Pin PGA MOTOROLA ...
Page 161
... BDATA14 BDATA15 35 BDATA16 GND BDATA17 BDATA18 BDATA19 BDATA20 BDATA21 BDATA22 GND BDATA23 BDATA24 46 47 MOTOROLA Ordering Information and Mechanical Data . 173 172 162 161 MC68839 (TOP VIEW) 184 Pin QFP MC68839 USER’S MANUAL 150 149 139 138 ADATA25 ...
Page 162
... .030 .010 .030 M MATRIX .008 M A PINS MC68839 USER’S MANUAL M A .006 A MILLIMETERS INCHES DIM MAX MIN MAX MIN A 0.17 0.19 1.774 B 1.746 1.746 1.774 C D 1.6 1.6 G .10 .10 H .95 .97 J .578 .59 K 0.070 0.070 0.9 0.11 M MOTOROLA ...
Page 163
... CASE TO BE DETERMINED (PRELIMINARY MILLIMETERS DIM MIN MAX A 30.98 32.85 B 30.98 32.85 C 3.27 4.58 D 0.41 0.22 G 0.65 H 0.25 0.88 J 0.13 0.25 K 0.65 0. 0.325 R 0.50 S 34.95 35.45 34.95 35.45 V MOTOROLA Ordering Information and Mechanical Data . TOP VIEW 184 PINS (NOT TO SCALE S/V SIDE VIEW INCHES MAX MIN 0 8 MC68839 USER’S MANUAL Q R 2xR0.200 11-5 ...
Page 164
... Ordering Information and Mechanical Data 11-6 MC68839 USER’S MANUAL MOTOROLA ...
Page 165
... ADATA31–ADATA0 ACNTL3 ACNTL2 ACNTL1 ACNTL0 ARW# ACS0# MC68839 FSI ACS1# AREQ3–AREQ0 BCS1# BCNTL3 BCNTL2 BCNTL1 BCNTL0 BCS0# BDATA31–BDATA0 Figure A-1. MC68020 Bus Control Logic Signals MOTOROLA . DATA BUS CONTROL LOGIC ADDRESS MC68839 USER’S MANUAL R/W# CS# BR# BG# BGACK# AS# DS# R/W# ...
Page 166
... Bus Control Logic Example A-2 MC68839 USER’S MANUAL MOTOROLA ...
Page 167
... FSI to operate with no local memory. If the bus shown is the main or a local microprocessor bus, this configuration assumes the bus can give the FDDI system enough of its bandwidth to handle FDDI traffic. In this case, the bus shown can be the system bus. MOTOROLA . 32+4 ...
Page 168
... In this configuration, the data frames are loaded directly from the system mem- ory . B-2 . SYSTEM BUS ADDRESS/DATA 32/32 ADDRESS/ DATA FSI 32/32 MAC PHY MC68839 USER’S MANUAL BUS CONTROL MOTOROLA ...
Page 169
... FDDI System Interface to give it commands, read its status, and to handle the transmission of Immediate frames. With this configuration, the host processor must handle the control of the MAC and PHY, and the operation of SMT. MOTOROLA . COMMON MEMORY ...
Page 170
... Figure B-5. Slave Configuration With 64-Bit Data B-4 . COMMON MEMORY ADDRESS/DATA 32 ADDRESS /DATA FSI 32 MAC PHY HOST PROCESSOR 32 32 FSI TO/FROM MAC AND PHY MC68839 USER’S MANUAL MEMORY CONTROL MOTOROLA ...
Page 171
... DMA of the FDDI System Interface is used. Port A Data Register holds the most signif- icant portion of the data and the Port B Data Register holds the least significant portion of the data. The address is generated in Port A but can be accessed via either port. MOTOROLA . HOST PROCESSOR ...
Page 172
... System Configurations B-6 MC68839 USER’S MANUAL MOTOROLA ...
Page 173
... In the following subsections the user is provided with formulae which describe the transmis- sion and reception of back to back frames. The user may determine the bus utilization for any given frame size or amount of data to be transferred. Alternatively, the user may deter- MOTOROLA MC68839 USER’S MANUAL Eq ...
Page 174
... K is the bus coefficient and X is the amount of data in a frame Computing for 20 data frames, and thereby 20 descriptors, with X data in each frame and a total network time as given above yields: 20 (16 + KX (8))) = 12) Solving for (24 + K40 K)) C-2 MC68839 USER’S MANUAL Eq. 4 MOTOROLA ...
Page 175
... The external bus utilization for data only is calculated as follows (X+12) For example assuming the average access time to be 160ns for 32 bit word, i (8+12)) = 0.20 or 20% Therefore, in this case the minimum frame length should be 16 bytes or ZERO bytes of INFO. MOTOROLA MC68839 USER’S MANUAL Performance Requirements C-3 ...
Page 176
... U = 0.5 (64 + 16) / (64 + 12) = 0.53 or 53% Therefore, in this case the minimum frame length should be 64 bytes or 48 bytes of INFO for continuous reception. B. assuming the average access time to be 160ns for 64 bit word, i 0.75 0.25 (40 + 16) / (40 + 12) = 0.27 or 27% C-4 MC68839 USER’S MANUAL following equation 3 MOTOROLA ...
Page 177
... It is not required to have a node processor. The chip set handles enough of the real time portions of SMT such that very little of the host processor is needed to run SMT. The decision of whether or not to have a separate node processor is an architectural prefer- ence. MOTOROLA MC68839 USER’S MANUAL Performance Requirements C-5 ...
Page 178
... Performance Requirements C-6 MC68839 USER’S MANUAL MOTOROLA ...
Page 179
... Port output is busy. The indication not being written out does not prevent the FSI from reading more descriptors. This applies only to a descrip- tor ring that is smaller than the internal memory (8Kb or 1K descriptors). MOTOROLA MC68839 USER’S MANUAL D-1 ...
Page 180
... Ring Memory Structure and the FSI Implementation D-2 MC68839 USER’S MANUAL MOTOROLA ...
Page 181
... Transmission of the frame is aborted, possibly creating a remnant frame, if the frame was currently being transmitted. c. The error indication for this frame is written back to the descriptor ring Note that the activities on the Ring, (descriptor fetching, data reading, frame transmission and indication writing), will otherwise continue normally. MOTOROLA MC68839 USER’S MANUAL E-1 ...
Page 182
... If the access command register the command is not executed. If the access FCR the internal control register is not read or written. b. The Host Error (HER) bit in the Status Register 1 is set which causes an interrupt if enabled. If the CER is written with a parity error, the command written to the CMR is ignored. E-2 MC68839 USER’S MANUAL MOTOROLA ...
Page 183
... ER: Set when the DMA transfer is aborted due to an error specified by the PER bits PER: 3 bit field specifying an error during data transfer through the FSI ports DMA Error Indication: (destination side) Section 5.2.3.6 PER: Specifies an error during data transfer through the FSI ports MOTOROLA MC68839 USER’S MANUAL Error Discussion and Reference E-3 ...
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... Underrun occurs if the FSI transmitter is unable to move data from system memory to it's transmit buffers in adequate time to prevent transmit buffer underflow. The transmitter is sending data to the MAC in much less time than the FSI is receiving data from the system bus. E-4 MC68839 USER’S MANUAL MOTOROLA ...
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... If the parity error was a severe error the Ring should be re-defined to avoid this memory block this the host processor first issues the Stop command to transfer the Ring to the Stopped state and then re-defines the ring. MOTOROLA Location of error: MACIF sees parity error on tx data ...
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... Status Register 2 : Section 3.2.5 DRE: set by Parity Error or Port Operation Error Receive Frame Normal Indication : Section 5.2.3. CRC error. The Cyclical Redundancy check on the frame does not agree/pass. There are no guarentees that the frame is good if this bit is set. E-6 MC68839 USER’S MANUAL MOTOROLA ...
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... Only the frame which is delimited by the descriptors when the underrun occured is discarded. PE: Indicates that transmission of the frame was aborted due to the occurence of a parity error. -> if AB=1, UN=PE=0 implies that the decision to abort frame transmission is due to asser- tion of the TABORT signal. MOTOROLA MC68839 USER’S MANUAL Error Discussion and Reference E-7 ...
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... Error Discussion and Reference E-8 MC68839 USER’S MANUAL MOTOROLA ...