PSD313-B-70J SGS-Thomson-Microelectronics, PSD313-B-70J Datasheet
PSD313-B-70J
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PSD313-B-70J Summary of contents
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Low Cost Field Programmable Microcontroller Peripherals FEATURES SUMMARY Single Supply Voltage: – 5 V±10% for PSD3xx, ZPSD3xx, PSD3xxR, ZPSD3xxR – 2.7 to 5.5 V for ZPSD3xxV, ZPSD3xxRV Mbit of EPROM Kbit SRAM Input Latches ...
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Introduction ...........................................................................................................................................................1 2 Notation ................................................................................................................................................................2 3 Key Features ........................................................................................................................................................4 4 PSD3XX Family Feature Summary ......................................................................................................................5 5 Partial Listing of Microcontrollers Supported ........................................................................................................6 6 Applications ..........................................................................................................................................................6 7 ZPSD Background ................................................................................................................................................6 7.1 Integrated Power Management 8 Operating Modes (MCU Configurations) ............................................................................................................10 ...
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PSD3XXR Low Cost Microcontroller Peripherals 18 Specifications......................................................................................................................................................37 18.1 Absolute Maximum Ratings .....................................................................................................................37 18.2 Operating Range .....................................................................................................................................37 18.3 Recommended Operating Conditions......................................................................................................37 18.4 Pin Capacitance.......................................................................................................................................37 18.5 AC/DC Characteristics – PSD3XX/ZPSD3XX (All 5 V devices) ..............................................................38 18.6 AC/DC Characteristics – PSD3XXV (3 V ...
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The low cost PSD3XX family integrates high-performance and user-configurable blocks of EPROM, programmable logic, and optional SRAM into one part. The PSD3XX products Introduction also provide a powerful microcontroller interface that eliminates the need for external “glue logic”. The ...
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PSD3XX Family 1.0 The PSD3XX I/O ports can be used for: Introduction • Standard I/O ports • Programmable chip select outputs (cont.) • Address inputs • Demultiplexed address outputs • A data bus port for non-multiplexed MCU applications • A ...
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Figure 1. PSD3XX Family Architecture AD8–AD15 AD0–AD7 ALE/AS RD/E/DS WR/R/W BHE/PSEN RESET A19/CSI ** Not available for 3X1 devices. ** SRAM not available on “R” versions. OPTIONAL * PAGE LOGIC P3–P0 A11–A15 L A8–A10 CSIOPORT A A19/CSI T C ALE/AS ...
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PSD3XX Family 3.0 Single-chip programmable peripheral for microcontroller-based applications Key Features 256K to 1 Mbit of UV EPROM with the following features: • Configurable as 32, 64, or 128 16, 32 ...
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... PSD312 PSD303 PSD313 ZPSD301 ZPSD311 ZPSD302 ZPSD312 ZPSD303 ZPSD313 ZPSD301V ZPSD311V ZPSD302V ZPSD312V ZPSD303V ZPSD313V NOTES: 1. Low power versions of the ZPSD3XX (ZPSD3XXV) can only accept an active-low level Reset input. # PLD EPROM SRAM Page Inputs Size Size Reg 14 256 Kb 14 256 Kb 18 ...
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PSD3XX Family 5.0 Motorola family: 68HC11, 68HC16, M68000/10/20, M68008, M683XX, 68HC05C0 Partial Listing Intel family: 80C31, 80C51, 80C196/198, 80C186/188 of Microcontrollers Philips family: 80C31 and 80C51 based MCUs Supported Zilog: Z8, Z80, Z180 National: HPC16000, HPC46400 Echelon/Motorola/Toshiba: NEURON 6.0 Telecommunications: ...
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Integrated Power Management ZPSD Upon each address or logic input change to the ZPSD, the device powers up from low Background power standby for a short time. Then the ZPSD consumes only the necessary power to deliver new logic ...
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PSD3XX Family Table 2. Name PSD3XX Pin Descriptions BHE/ PSEN WR/V or R/W/V RD/E/DS A19/CSI Reset ALE/AS PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 Legend: 8 Type When the data bus is 8 bits: This pin is for 8031 ...
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Table 2. Name PSD3XX Pin Descriptions (cont.) PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 AD8/A8 AD9/A9 AD10/A10 AD11/A11 AD12/A12 AD13/A13 AD14/A14 AD15/A15 GND V CC Legend: Type These ...
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PSD3XX Family 8.0 The PSD3XX’s four operating modes enable it to interface directly to most 8- and 16-bit microcontrollers with multiplexed and non-multiplexed address/data busses. The 16-bit Operating modes are not available to some devices; see Table 1. The following ...
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Figure 3A. Connecting a PSD3XX to an 8-Bit Multiplexed-Bus MCU Operating Modes (MCU Configurations) (cont.) Figure 3B. Connecting a PSD3XX to a 16-Bit Multiplexed-Bus MCU Figure 3C. Connecting a PSD3XX to an 8-Bit Non-Multiplexed-Bus MCU Figure 3D. Connecting a ...
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PSD3XX Family 8.0 Table 3. Bus and Port Configuration Options Operating Modes (MCU 8-bit Data Bus Configurations) (cont.) Port A Port B AD0/A0–AD7/A7 AD8/A8–AD15/A15 16-bit Data Bus Port A Port B AD0/A0–AD7/A7 AD8/A8–AD15/A15 9.0 The PSD3XX contains two programmable arrays, ...
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Figure 4. PAD Description ALE or AS RD/E/ R/W A19 A18 A17 A16 A15 A14 A13 A12 A11 CSI RESET * SRAM no available on “R” versions NOTES: 1. CSI ...
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PSD3XX Family Table 4. PSD3XX PAD A and PAD B Inputs PAD A and A19/CSI PAD B Functions A16–A18 A11–A15 P0–P3 RD/E/ R/W ALE/AS RESET PAD A Outputs ES0–ES7 RS0 CSIOPORT CSADIN CSADOUT1 CSADOUT2 PAD B Outputs CS0–CS3 ...
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The PSD3XX has three I/O ports (Ports A, B, and C) that are configurable at the bit level. This permits great flexibility and a high degree of customization for specific applications. I/O Port The next section describes the control ...
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PSD3XX Family PSD3XX Family 10.0 10.2 Port A (PA0-PA7) I/O Port The control registers of Port A are located in CSIOPORT space; see Table 5. Functions 10.2.1 Port A (PA0-PA7) in Multiplexed Address/Data Mode ( cont.) Each pin of Port ...
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Port A (PA0-PA7) in Non-Multiplexed Address/Data Mode In this mode, Port A becomes the low-order data bus byte of the chip. When reading an I/O Port internal location, data is presented on Port A pins to the MCU. ...
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PSD3XX Family PSD3XX Family 10. 10.3 Port B (PB0-PB7) I/O Port The control registers of Port B are located in CSIOPORT space; see Table 5A and 5B. Functions 10.3.1 Port B (PB0-PB7) in Multiplexed Address/Data Mode ( cont.) Each pin ...
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Port B (PB0-PB7) in 16-bit Multiplexed Address/Data Mode In this mode, Port B becomes the low-order data bus byte to the MCU chip. When reading I/O Port an internal high-order location, data is presented on Port B pins ...
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PSD3XX Family 10. 10.4 Port C (PC0-PC2) Each pin of Port C (Figure 7) can be configured as an input to PAD A and PAD I/O Port output from PAD B. As inputs, the pins are ...
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The following sections explain the various memory blocks and memory options within the PSD3XX. PSD Memory 11.1 EPROM For all of the PSD3XX devices, the EPROM is built using Zero-power technology. This means that the EPROM powers up only ...
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PSD3XX Family 12.0 Consult your MCU data sheet to determine which control signals your MCU generates, and how they operate. This section is intended to show which control signals should be Control Signals connected to what pins on the PSD3XX. ...
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A19/CSI Control Signals This pin is configured using PSDsoft to be either a chip select for the entire PSD device or an additional PAD input. If your MCU can generate a chip-select signal, and you wish to (cont.) ...
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PSD3XX Family 12.0 12.6 Reset Input Control Signals This is an asynchronous input to initialize the PSD device. (cont.) Refer to tables 8A and 8B for information on device status during and after reset. The standard-voltage PSD3XX and ZPSD3XX (non-V) ...
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Table 8B. Internal PSD Signal States During and Just After Reset Control Signals (cont.) PAD A and PAD B All registers in CSIOPORT address space, including: Direction Data Page PMR (turbo bit, ZPSD3XX only) NOTE: N/A = Not Applicable ...
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PSD3XX Family 13.0 This section only applies to users who have an 8031 or compatible MCU that outputs a signal such as PSEN when accessing program space. If this applies to you, be aware of the Program/Data following: Space and ...
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In Figure 11, the PSD3XX is configured to interface with Intel’s 80C31, which is a 16-bit address/8-bit data bus microcontroller. Its data bus is multiplexed with the low-order System address byte. The 80C31 uses signals RD to read from ...
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PSD3XX Family 14.0 In Figure 12, the PSD3XX is configured to interface with Motorola’s 68HC11, which is a 16-bit address/8-bit data bus microcontroller. Its data bus is multiplexed with the low-order System address byte. The 68HC11 uses E and R/W ...
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In Figure 13, the PSD3XX is configured to work directly with Intel’s 80C196KB microcontroller, which is a 16-bit address/16-bit data bus processor. The Address and data System lines multiplexed. The PSD3XX is configured to use PC0, PC1, PC2, and ...
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PSD3XX Family 15.0 Security Mode in the PSD3XX locks the contents of PAD A, PAD B, and all the configuration bits. The EPROM, optional SRAM, and I/O contents can be accessed only through the Security Mode PAD. The Security Mode ...
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Turbo Bit (ZPSD only) Power The turbo bit is controlled by the MCU at run-time and is accessed through bit zero of the Power Management Register (PMR). The PMR is located in CSIOPORT space at offset 10h. Management ...
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PSD3XX Family 16.0 16.5 Composite Frequency of the Input Signals to the PAD Logic Power The composite frequency of the input signals to the PADs is calculated by considering all transitions on any PAD input signal (including the MCU address ...
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All the inputs shown, except CSI the PAD logic. These signals must be taken into consideration when calculating the composite frequency. Before we make the calculation, Power let’s establish the following conditions: Management • The input with ...
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PSD3XX Family 17. Once you have read the “Power Management” section, you should be able to calculate power. The following is a sample power calculation: Calculating Power Conditions Part Used MCU ALE Clock Frequency Composite ZPLD Input Frequency % EPROM ...
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Figure 14. Typical I Calculating Power (cont.) Figure 15. Typical I vs. Frequency for the PAD ( Turbo Non -Turbo 10 PT Turbo Non -Turbo ...
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PSD3XX Family Figure 16 ± 10 ZPSD3XXV 0.00 0.10 0.20 0.30 0. (V) Figure 18. Normalized I (AC) CC ZPSD3XXV 2.2 2.0 ...
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Absolute Maximum Ratings Specifications Symbol T STG NOTE: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of ...
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PSD3XX Family 18.5 AC/DC Characteristics – PSD3XX/ZPSD3XX (All 5 V devices) Symbol Parameter V Supply Voltage CC V High-Level Input Voltage IH V Low-Level Input Voltage IL V Output High Voltage OH Output Low Voltage V OL (See Figure 16) ...
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AC/DC DC Characteristics – ZPSD3XXV (3 V devices only) Symbol Parameter V Supply Voltage CC V High-Level Input Voltage IH V Low-Level Input Voltage IL V Output High Voltage OH V Output Low Voltage Standby Supply ...
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PSD3XX Family 18.7 Timing Parameters – PSD3XX/ZPSD3XX (All 5 V devices) Symbol Parameter T1 ALE or AS Pulse Width T2 Address Set-up Time T3 Address Hold Time Leading Edge of Read T4 to Data Active T5 ALE Valid to Data ...
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Timing Parameters – PSD3XX/ZPSD3XX (All 5 V devices) Symbol Parameter Track Mode Address Propagation Delay: CSADOUT1 Already True T23 Latched Address Outputs, Port A Track Mode Address Propagation Delay: T23A CSADOUT1 Becomes True During ALE or AS Track Mode ...
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PSD3XX Family 18.8 Timing Parameters – ZPSD3XXV (3 V devices only) Symbol Parameter T1 ALE or AS Pulse Width T2 Address Set-up Time T3 Address Hold Time Leading Edge of Read T4 to Data Active T5 ALE Valid to Data ...
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Timing Parameters – ZPSD3XXV (3 V devices only) Symbol Parameter Track Mode Address Propagation Delay: CSADOUT1 Already True T23 Latched Address Outputs, Port A Track Mode Address Propagation Delay: T23A CSADOUT1 Becomes True During ALE or AS Track Mode ...
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PSD3XX Family 18.9 Timing Diagrams for all PSD3XX Parts Figure 20. Timing of 8-Bit Multiplexed Address/Data Bus Using RD, WR (PSD3X1) CSI/A19 as CSI (1) Direct STABLE INPUT PAD Input (2) Multiplexed Inputs A0/AD0- ADDRESS A A7/AD7 2 3 Active ...
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Figure 21. Timing of 8-Bit Multiplexed Address/Data Bus Using RD, WR (PSD3X2/3X3) CSI/A19 as CSI (1) Direct STABLE INPUT PAD Input (2) Multiplexed Inputs A0/AD0- ADDRESS A A7/AD7 2 3 Active High 1 ALE Active Low ALE RD/E/ ...
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PSD3XX Family Figure 22. Timing of 8-Bit Multiplexed Address/Data Bus Using R/ R/W, DS (PSD3X1) CSI/A19 as CSI (1) Direct PAD Input (2) Multiplexed Inputs A0/AD0- ADDRESS A A7/AD7 2 3 Active High 1 AS Active Low 35 ...
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Figure 23. Timing of 8-Bit Multiplexed Address/Data Bus Using R R/W, DS (PSD3X2/3X3) CSI/A19 as CSI (1) Direct STABLE INPUT PAD Input (2) Multiplexed Inputs A0/AD0- ADDRESS A A7/AD7 2 3 Active High 1 AS Active Low 35 ...
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PSD3XX Family Figure 24. Timing of 16-Bit Multiplexed Address/Data Bus Using RD, WR (PSD3X1) CSI/A19 as CSI (1) Direct STABLE INPUT PAD Input (2) Multiplexed Inputs BHE/PSEN as BHE A0/AD0- ADDRESS A A15/AD15 2 3 Active High 1 ALE Active ...
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Figure 25. Timing of 16-Bit Multiplexed Address/Data Bus Using RD, WR (PSD3X2/3X3) CSI/A19 as CSI (1) Direct STABLE INPUT PAD Input (2) Multiplexed Inputs BHE/PSEN as BHE A0/AD0- ADDRESS A A15/AD15 2 3 Active High 1 ALE Active Low ALE ...
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PSD3XX Family Figure 26. Timing of 16-Bit Multiplexed Address/Data Bus Using R/ R/W, DS (PSD3X1) CSI/A19 as CSI (1) Direct PAD Input (2) Multiplexed Inputs BHE/PSEN as BHE A0/AD0- ADDRESS A A15/AD15 2 3 Active High 1 AS ...
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Figure 27. Timing of 16-Bit Multiplexed Address/Data Bus Using R/ R/W, DS (PSD3X2/3X3) CSI/A19 as CSI (1) Direct STABLE INPUT PAD Input (2) Multiplexed Inputs BHE/PSEN as BHE A0/AD0- ADDRESS A A15/AD15 2 3 Active High 1 AS ...
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PSD3XX Family Figure 28. Timing of 8-Bit Non-Multiplexed Address/Data Bus Using RD, WR (PSD3X1) CSI/A19 as CSI (1) Direct STABLE INPUT PAD Input A0/AD0- STABLE INPUT A15/AD15 as A0-A15 PC0-PC2, CSI/A19 as Multiplexed Inputs PA0-PA7 2 3 Active High 1 ...
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Figure 29. Timing of 8-Bit Non-Multiplexed Address/Data Bus Using RD, WR (PSD3X2/3X3) CSI/A19 as CSI (1) Direct STABLE INPUT PAD Input A0/AD0- A15/AD15 STABLE INPUT as A0-A15 (2) Multiplexed Inputs PA0-PA7 2 3 Active High 1 ALE Active Low ALE ...
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PSD3XX Family Figure 30. Timing of 8-Bit Non-Multiplexed Address/Data Bus Using R/ R/W, DS (PSD3X1) CSI/A19 as CSI (1) Direct STABLE INPUT PAD Input A0/AD0- A15/AD15 STABLE INPUT as A0-A15 PC0-PC2, CSI/A19 as Multiplexed Inputs PA0-PA7 2 3 ...
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Figure 31. Timing of 8-Bit Non-Multiplexed Address/Data Bus Using R/ R/W, DS (PSD3X2/3X3) CSI/A19 as CSI (1) Direct STABLE INPUT PAD Input A0/AD0- A15/AD15 STABLE INPUT as A0-A15 (2) Multiplexed Inputs PA0-PA7 2 3 Active High 1 ALE ...
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PSD3XX Family Figure 32. Timing of 16-Bit Non-Multiplexed Address/Data Bus Using RD, WR (PSD3X1) CSI/A19 as CSI Direct (1) STABLE INPUT PAD Input A0/AD0- A15/AD15 STABLE INPUT as A0-A15 PC0-PC2, CSI/A19 as Multiplexed Inputs BHE/PSEN as BHE PA0-PA7 (Low Byte) ...
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Figure 33. Timing of 16-Bit Non-Multiplexed Address/Data Bus Using RD, WR (PSD3X2/3X3) CSI/A19 as CSI (1) Direct STABLE INPUT PAD Input A0/AD0- A15/AD15 STABLE INPUT as A0-A15 (2) Multiplexed Inputs BHE/PSEN as BHE PA0-PA7 (Low Byte) PB0-PB7 (High Byte) 2 ...
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PSD3XX Family Figure 34. Timing of 16-Bit Non-Multiplexed Address/Data Bus Using R/ R/W, DS (PSD3X1) CSI/A19 as CSI (1) Direct PAD Input A0/AD0- A15/AD15 as A0-A15 PC0-PC2, CSI/A19 as Multiplexed Inputs BHE/PSEN as BHE PA0-PA7 (Low Byte) PB0-PB7 ...
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Figure 35. Timing of 16-Bit Non-Multiplexed Address/Data Bus Using R/ R/W, DS (PSD3X2/3X3) CSI/A19 as CSI (1) Direct STABLE INPUT PAD Input A0/AD0- A15/AD15 STABLE INPUT as A0-A15 (2) Multiplexed Inputs BHE/PSEN as BHE PA0-PA7 (Low Byte) PB0-PB7 ...
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PSD3XX Family Figure 36. Chip-Select Output Timing 60 30 A19/CSI as CSI (1) Direct PAD INPUT STABLE Input (2) Multiplexed PAD Inputs 2 3 ALE (Multiplexed 1 Mode Only) or ALE (Multiplexed Mode Only) 21 (3,8) CSOi See referenced notes ...
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Figure 37. Port A as AD0–AD7 Timing (Track Mode) Using RD, WR (PSD3X1) Direct PAD Input (1,4) 2 Multiplexed STABLE INPUT PAD Inputs (5, A0/AD0- ADDRESS A7/AD7 ALE 1 or ALE RD WR ...
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PSD3XX Family Figure 38. Port A as AD0–AD7 Timing (Track Mode) Using RD, WR (PSD3X2/3X3) Direct PAD Input (1,4) 2 Multiplexed STABLE INPUT PAD Inputs (5,7) 2 A0/AD0- ADDRESS A7/AD7 ALE 1 or ALE RD/E/ WR ...
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Figure 39. Port A as AD0–AD7 Timing (Track Mode) Using R/ R/W, DS (PSD3X1) Direct PAD Input STABLE INPUT (1,4) 2 Multiplexed STABLE INPUT PAD Inputs (5, A0/AD0- ADDRESS A7/AD7 RD/E as ...
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PSD3XX Family Figure 40. Port A as AD0–AD7 Timing (Track Mode) Using R/ R/W, DS (PSD3X2/3X3) Direct PAD Input (1,4) 2 Multiplexed STABLE INPUT PAD Inputs (5,7) 2 A0/AD0- ADDRESS A7/AD7 RD/E/ ...
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Figure 41A. AC Testing Input/Output Waveform (5 V Versions) 18.10 AC Testing Figure 41B. AC Testing Input/Output Waveform (3 V Versions) Figure 42A. AC Testing Load Circuit (5 V Versions) Figure 42B. AC Testing Load Circuit (3 V Versions) 3.0V ...
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PSD3XX Family 19.0 Pin Assignments BHE/PSEN WR/V RESET PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 RD/E AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 AD8/A8 AD9/A9 AD10/A10 ...
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Package Information Figure 43. Drawing J2 – 44 Pin Plastic Leaded Chip Carrier (PLDCC) without Window (Package Type J) OR Drawing L4 – 44 Pin Ceramic Leaded Chip Carrier (CLDCC) with Window (Package Type L) (TOP VIEW) Figure 44. ...
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PSD3XX Family 21.0 Package Drawings Drawing J2 – 44-Pin Plastic Leaded Chip Carrier (PLDCC) (Package Type Family: Plastic Leaded Chip Carrier Symbol Min A 4.19 A1 2.54 A2 3.76 B ...
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Drawing L4 – 44-Pin Pocketed Ceramic Leaded Chip Carrier (CLDCC) – CERQUAD (Package Type Family: Ceramic Leaded Chip Carrier – CERQUAD Millimeters Symbol Min A 3.94 A1 2.29 A2 3.05 ...
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PSD3XX Family Drawing M1 – 44-Pin Plastic Quad Flatpack (PQFP) (Package Type Index 3 Mark B Family: Plastic Quad Flatpack (PQFP) Symbol Min 0° A – A1 1.075 A2 1.95 B 0.30 C ...
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Drawing U1 – 44-Pin Plastic Thin Quad Flatpack (TQFP) (Package Type Index 3 Mark B Family: Plastic Thin Quad Flatpack (TQFP) Symbol Min 0° A – A1 0.54 A2 1.15 B 0.35 C ...
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... X PSD302R ZPSD302R X PSD313R ZPSD313R X PSD303R ZPSD303R X PSD311 ZPSD311 ZPSD311V X PSD301 ZPSD301 ZPSD301V X PSD312 ZPSD312 ZPSD312V X PSD302 ZPSD302 ZPSD302V X PSD313 ZPSD313 ZPSD313V X PSD303 ZPSD303 ZPSD303V X MCU PLDs/Decoders I/O PLD Page Ports Data Terms Outputs Reg. STD STD STD 18 40 ...
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PSD3XX 22.2 Part Number Construction Ordering Information Z PSD (cont.) 22.3 Ordering Information Part Number PSD301-B-70J PSD301-B-70L PSD301-B-70M PSD301-B-70U PSD301-B-90JI PSD301-B-90LI PSD301-B-90MI PSD301-B-90UI PSD301-B-15J PSD301-B-15L PSD301-B-15M PSD301-B-15U PSD301R-B-70J PSD301R-B-90JI PSD301R-B-15J I 413A2 V -A -20 J Speed (ns) Package Type ...
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PSD3XX Family PSD3XX Ordering Information Ordering Information (cont.) Part Number PSD302-B-70J PSD302-B-70L PSD302-B-70M PSD302-B-70U PSD302-B-90JI PSD302-B-90LI PSD302-B-90MI PSD302-B-90UI PSD302-B-15J PSD302-B-15L PSD302-B-15M PSD302-B-15U PSD302R-B-70J PSD302R-B-90JI PSD302R-B-15J PSD303-B-70J PSD303-B-70L PSD303-B-70M PSD303-B-70U PSD303-B-90JI PSD303-B-90LI PSD303-B-90MI PSD303-B-90UI PSD303-B-15J PSD303-B-15L PSD303-B-15M PSD303-B-15U PSD303R-B-70J PSD303R-B-90JI PSD303R-B-15J ...
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... PSD312-B-90LI PSD312-B-90MI PSD312-B-90UI PSD312-B-15J PSD312-B-15L PSD312-B-15M PSD312-B-15U PSD312R-B-70J PSD312R-B-90JI PSD312R-B-15J PSD313-B-70J PSD313-B-70L PSD313-B-70M PSD313-B-70U PSD313-B-90JI PSD313-B-90LI PSD313-B-90MI PSD313-B-90UI PSD313-B-15J PSD313-B-15L PSD313-B-15M ...
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PSD3XX Family PSD3XX Ordering Information Ordering Information (cont.) Part Number ZPSD301-B-70J ZPSD301-B-70L ZPSD301-B-70M ZPSD301-B-70U ZPSD301-B-90JI ZPSD301-B-90LI ZPSD301-B-90MI ZPSD301-B-90UI ZPSD301-B-15J ZPSD301-B-15L ZPSD301-B-15M ZPSD301-B-15U ZPSD301R-B-70J ZPSD301R-B-90JI ZPSD301R-B-15J ZPSD301V-B-15J ZPSD301V-B-15L ZPSD301V-B-15U ZPSD301V-B-20J ZPSD301V-B-20JI ZPSD301V-B-20L ZPSD301V-B-20M ZPSD301V-B-20MI ZPSD301V-B-20U ZPSD301V-B-20UI ZPSD301V-B-25J ZPSD301V-B-25L ZPSD301V-B-25M ZPSD301V-B-25U ZPSD302-B-70J ...
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PSD3XX Ordering Information Ordering Information (cont.) Part Number ZPSD302V-B-20J ZPSD302V-B-20JI ZPSD302V-B-20L ZPSD302V-B-20M ZPSD302V-B-20MI ZPSD302V-B-20U ZPSD302V-B-20UI ZPSD302V-B-25J ZPSD302V-B-25L ZPSD302V-B-25M ZPSD302V-B-25U ZPSD303-B-70J ZPSD303-B-70L ZPSD303-B-70M ZPSD303-B-70U ZPSD303-B-90JI ZPSD303-B-90LI ZPSD303-B-90MI ZPSD303-B-90UI ZPSD303-B-15J ZPSD303-B-15L ZPSD303-B-15M ZPSD303-B-15U ZPSD303R-B-70J ZPSD303R-B-90JI ZPSD303R-B-15J ZPSD303V-B-20J ZPSD303V-B-20JI ZPSD303V-B-20L ZPSD303V-B-20M ZPSD303V-B-20MI ZPSD303V-B-20U ...
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PSD3XX Family PSD3XX Ordering Information Ordering Information (cont.) Part Number ZPSD311-B-70J ZPSD311-B-70L ZPSD311-B-70M ZPSD311-B-70U ZPSD311-B-90JI ZPSD311-B-90LI ZPSD311-B-90MI ZPSD311-B-90UI ZPSD311-B-15J ZPSD311-B-15L ZPSD311-B-15M ZPSD311-B-15U ZPSD311R-B-70J ZPSD311R-B-70M ZPSD311R-B-90JI ZPSD311R-B-90MI ZPSD311R-B-15J ZPSD311R-B-15M ZPSD311V-B-15J ZPSD311V-B-15L ZPSD311V-B-15M ZPSD311V-B-15U ZPSD311V-B-20J ZPSD311V-B-20JI ZPSD311V-B-20L ZPSD311V-B-20M ZPSD311V-B-20MI ZPSD311V-B-20U ZPSD311V-B-20UI ZPSD311V-B-25J ...
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... ZPSD312V-B-20JI ZPSD312V-B-20L ZPSD312V-B-20M ZPSD312V-B-20MI ZPSD312V-B-20U ZPSD312V-B-20UI ZPSD312V-B-25J ZPSD312V-B-25L ZPSD312V-B-25M ZPSD312V-B-25U ZPSD313-B-70J ZPSD313-B-70L ZPSD313-B-70M ZPSD313-B-70U ZPSD313-B-90JI ZPSD313-B-90LI ZPSD313-B-90MI ZPSD313-B-90UI ZPSD313-B-15J ZPSD313-B-15L ZPSD313-B-15M ...
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... ZPSD313R-B-70M ZPSD313R-B-90JI ZPSD313R-B-90MI ZPSD313R-B-15J ZPSD313R-B-15M ZPSD313V-B-20J ZPSD313V-B-20JI ZPSD313V-B-20L ZPSD313V-B-20M ZPSD313V-B-20MI ZPSD313V-B-20U ZPSD313V-B-20UI ZPSD313V-B-25J ZPSD313V-B-25L ZPSD313V-B-25M ZPSD313V-B-25U 23. Revisions History May, 1995 May, 1998 May, 1998 February, 1999 ...
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PSD3XX, ZPSD3XX, ZPSD3XXV, PSD3XXR, ZPSD3XXR, ZPSD3XXRV REVISION HISTORY Table 1. Document Revision History Date Rev. May-1995 1.0 Documents written in the WSI format. Initial release ZPSD3XX SRAM-less (R suffix) version added. PQFP package added. PSD3XX PQFP package added, Specifications updated, ...
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PSD3XX, ZPSD3XX, ZPSD3XXV, PSD3XXR, ZPSD3XXR, ZPSD3XXRV Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties ...