IS42S16128-10T Integrated Silicon Solution, IS42S16128-10T Datasheet
IS42S16128-10T
Available stocks
Related parts for IS42S16128-10T
IS42S16128-10T Summary of contents
Page 1
... Ground for I/O Pin NC No Connection ORDERING INFORMATION Commercial Range: 0⋅ ⋅ ⋅ ⋅ ⋅ 70⋅ ⋅ ⋅ ⋅ ⋅ C Frequency Speed (ns) Order Part No. 125 MHz 8 IS42S16128-8T 100 MHz 10 IS42S16128-10T 83 MHz 12 IS42S16128-12T ISSI ® FEBRUARY 2000 Package 400-mil TSOP II 400-mil TSOP II 400-mil TSOP II 1 ...
Page 2
... IS42S16128 PIN FUNCTIONS Pin No. Symbol Type 20 to 24, A0-A8 Input Pin Input Pin CAS 16 Input Pin 34 CKE Input Pin 35 CLK Input Pin CS 18 Input Pin I/O0 to I/O Pin 12, 39, 40, 42, 43, I/O15 45, 46, 48, 49 14, 36 LDQM, Input Pin UDQM RAS ...
Page 3
... IS42S16128 FUNCTIONAL BLOCK DIAGRAM CLK CKE CS COMMAND DECODER RAS CAS & CLOCK WE MODE A9 GENERATOR REGISTER A8 A7 REFRESH A6 CONTROLLER CONTROLLER A5 A4 REFRESH A3 COUNTER ROW ADDRESS LATCH 9 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/13/00 ROW ADDRESS 512 BUFFER SELF REFRESH ...
Page 4
... IS42S16128 ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Maximum Supply Voltage CC MAX VccQ Maximum Supply Voltage for Output Buffer MAX V Input Voltage IN V Output Voltage OUT P Allowable Power Dissipation D MAX I Output Shorted Current CS T Operating Temperature OPR T Storage Temperature STG DC RECOMMENDED OPERATING CONDITIONS ...
Page 5
... IS42S16128 DC ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.) Symbol Parameter I Input Leakage Current IL I Output Leakage Current OL V Output High Voltage Level OH V Output Low Voltage Level OL I Operating Current (1, Precharge Standby Current CC I 2PS (In Power-Down Mode ...
Page 6
... IS42S16128 (1,2,3) AC CHARACTERISTICS Symbol Parameter t 3 Clock Cycle Time ( Access Time From CLK CLK HIGH Level Width CHI t CLK LOW Level Width Output Data Hold Time Output LOW Impedance Time LZ ( Output HIGH Impedance Time ...
Page 7
... IS42S16128 OPERATING FREQUENCY / LATENCY RELATIONSHIPS Symbol Parameter — Clock Cycle Time — Operating Frequency CAS Latency t CAC t Active Command To Read/Write Command Delay Time RCD RAS Latency ( RAC RCD CAC t Command Period (REF to REF / ACT to ACT Command Period (ACT to PRE) ...
Page 8
... IS42S16128 COMMANDS Active Command CLK HIGH CKE CS RAS CAS WE A0- Write Command CLK HIGH CKE CS RAS CAS WE A0-A7 AUTO PRECHARGE A8 NO PRECHARGE A9 No-Operation Command CLK HIGH CKE CS RAS CAS WE A0- Read Command CLK HIGH CKE CS RAS CAS WE A0-A7 ROW ROW A8 BANK 1 A9 ...
Page 9
... IS42S16128 COMMANDS (cont.) Mode Register Set Command CLK HIGH CKE CS RAS CAS WE A0- Self-Refresh Command CLK CKE CS RAS CAS WE A0- Clock Suspend Command CLK CKE BANK(S) ACTIVE CS RAS CAS WE A0- Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/13/00 Auto-Refresh Command CLK HIGH ...
Page 10
... MCD command execution. Active Command (CS, RAS = LOW, CAS, WE= HIGH) The IS42S16128 includes two banks of 512 rows each. This command selects one of the two banks according to the A9 pin and activates the row selected by the pins A0 to A8. This command corresponds to the fall of the RAS signal from HIGH to LOW in conventional DRAMs ...
Page 11
... IS42S16128 Self-Refresh Command (CS, RAS, CAS, CKE = LOW HIGH) This command executes the self-refresh operation. The row address to be refreshed, the bank, and the refresh interval are generated automatically internally during this operation. The self-refresh operation is started by drop- ping the CKE pin from HIGH to LOW. The self-refresh operation continues as long as the CKE pin remains LOW and there is no need for external control of any other pins ...
Page 12
... IS42S16128 (1,2) COMMAND TRUTH TABLE Symbol Command (3,4) MRS Mode Register Set REF Auto-Refresh (5) (5,6) SREF Self-Refresh PRE Precharge Selected Bank PALL Precharge Both Banks (7) ACT Bank Activate WRIT Write WRITA Write With Auto-Precharge (8) READ Read READA Read With Auto-Precharge (9) BST Burst Stop NOP ...
Page 13
... IS42S16128 OPERATION COMMAND TABLE Current State Command Idle DESL NOP BST READ / READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Row Active DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Read DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Write DESL ...
Page 14
... IS42S16128 OPERATION COMMAND TABLE Current State Command Write With DESL Auto-Precharge NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Row Precharge DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Immediately DESL Following NOP Row Active BST READ/READA WRIT/WRITA ACT PRE/PALL ...
Page 15
... This is possible depending on the state of the bank selected by the A9 pin. 11. Time to switch internal busses is required. 12. The IS42S16128 can be switched to power-down mode by dropping the CKE pin LOW when both banks in the idle state. Input pins other than CKE are ignored at this time. ...
Page 16
... IS42S16128 CKE RELATED COMMAND TRUTH TABLE Current State Operation Self-Refresh Undefined Self-Refresh Recovery Self-Refresh Recovery (2) Illegal (2) Illegal Self-Refresh Self-Refresh Recovery Idle State After t Idle State After t Illegal Illegal Power-Down on the Next Cycle Power-Down on the Next Cycle Illegal Illegal Clock Suspend Termination on the Next Cycle ...
Page 17
... IS42S16128 TWO BANKS OPERATION COMMAND TRUTH TABLE CS RAS CAS WE Operation DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF MRS Notes HIGH level input, L: LOW level input, X: HIGH or LOW level input, RA: Row Address, CA: Column Address 2 ...
Page 18
... IS42S16128 SIMPLIFIED STATE TRANSITION DIAGRAM (One Bank Operation) MODE REGISTER BST WRIT WRITE CKE_ CKE CLOCK WRITA SUSPEND CKE_ CKE WRITE WITH AUTO PRECHARGE POWER ON POWER APPLIED Automatic transition following the completion of command execution. Transition due to command input. 18 SREF entry SREF exit ...
Page 19
... The burst length field in Q reach their CC the mode register stipulates the number of data items input or output in sequence. In the IS42S16128 product, a burst length full page can be specified. See the table on the next page for details on setting the mode register. ...
Page 20
... IS42S16128 MODE REGISTER WRITE MODE LT MODE Write Mode Burst Read & Burst Write Burst Read & Single Write Address Bus Mode Register (Mx Burst Length Burst Type ...
Page 21
... IS42S16128 Burst Length and Column Address Sequence Column Address Burst Length Full Page (256) Notes: 1. The burst length in full page mode is 256. ...
Page 22
... IS42S16128 Burst Read The read cycle is started by executing the read command. The address provided during read command execution is used as the starting address. First, the data correspond- ing to this address is output in synchronization with the clock signal after the CAS latency period. Next, data ...
Page 23
... IS42S16128 Read With Auto-Precharge The read with auto-precharge command first executes a burst read operation and then puts the selected bank in the precharged state automatically. After the precharge completes, the bank goes to the idle state. Thus this command performs a read command and a precharge command in a single operation ...
Page 24
... IS42S16128 Write With Auto-Precharge The write with auto-precharge command first executes a burst write operation and then puts the selected bank in the precharged state automatically. After the precharge completes the bank goes to the idle state. Thus this command performs a write command and a precharge command in a single operation ...
Page 25
... IS42S16128 Interval Between Read Command A new command can be executed while a read cycle is in progress, i.e., before that cycle completes. When the second read command is executed, after the CAS latency has elapsed, data corresponding to the new read com- mand is output in place of the data due to the previous read command ...
Page 26
... IS42S16128 Interval Between Write and Read Commands A new read command can be executed while a write cycle is in progress, i.e., before that cycle completes. Data corresponding to the new read command is output after the CAS latency has elapsed from the point the new read command was executed. The I/On pins must be placed in the HIGH impedance state at least one cycle before data is output during this operation ...
Page 27
... IS42S16128 Interval Between Read and Write Commands A read command can be interrupted and a new write command executed while the read cycle is in progress, i.e., before that cycle completes. Data corresponding to the new write command can be input at the point new write command is executed. To prevent collision between ...
Page 28
... IS42S16128 Precharge The precharge command sets the bank selected by pin A9 to the precharged state. This command can be executed at a time t following the execution of an active com- RAS mand to the same bank. The selected bank goes to the idle state at a time t following the execution of the ...
Page 29
... IS42S16128 Write Cycle Interruption Using the Precharge Command A write cycle can be interrupted by the execution of the precharge command before that cycle completes. The delay time (t ) from the precharge command to the WDL point where burst input is invalid, i.e., the point where input data is no longer written to device internal memory is zero clock cycles regardless of the CAS ...
Page 30
... The IS42S16128 can output data continuously from the burst start address (a) to location a+255 during a read cycle in which the burst length is set to full page. The IS42S16128 repeats the operation starting at the 256th cycle with the data output returning to location (a) and continuing with a+1, a+2, a+3, etc. A burst stop command must be executed to terminate this cycle ...
Page 31
... The IS42S16128 can input data continuously from the burst start address (a) to location a+255 during a write cycle in which the burst length is set to full page. The IS42S16128 repeats the operation starting at the 256th cycle with data input returning to location (a) and continu- ing with a+1, a+2, a+3, etc. A burst stop command must ...
Page 32
... COMMAND I/O CAS latency = The IS42S16128 will revert to accepting input as soon as that pin is dropped to LOW and data will be written to the device. This input control operates independently on a byte basis with the UDQM pin controlling upper byte input (pin I/O8 to I/O15) and the LDQM pin controlling the lower byte input (pins I/O0 to I/O7) ...
Page 33
... CAS latency = 3 Clock Suspend When the CKE pin is dropped from HIGH to LOW during a read or write cycle, the IS42S16128 enters clock sus- pend mode on the next CLK rising edge. This command reduces the device power dissipation by stopping the device internal clock. Clock suspend mode continues as long as the CKE pin remains low ...
Page 34
... IS42S16128 OPERATION TIMING EXAMPLE Power-On Sequence, Mode Register Set Cycle CLK t CHI HIGH CKE RAS CAS A0- BANK 0 & DQM HIGH I/O WAIT TIME t RP T=100 µs < ...
Page 35
... IS42S16128 Power-Down Mode Cycle CLK t CHI CKS CK CL CKE t CKA RAS CAS A0- BANK 0 & 1 BANK BANK 1 BANK 0 DQM I < > PRE < > PALL CAS latency = 2, 3 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev ...
Page 36
... IS42S16128 Auto-Refresh Cycle CLK t CHI CKS CK CL CKE RAS CAS A0- BANK 0 & DQM I < > PALL CAS latency = < > < > REF REF Integrated Silicon Solution, Inc. — 1-800-379-4774 ...
Page 37
... IS42S16128 Self-Refresh Cycle CLK t CHI CKS CK CL CKE t CKA RAS CAS A0- BANK 0 & DQM I < > PALL CAS latency = 2, 3 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A ...
Page 38
... IS42S16128 Read Cycle CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A7 ROW ROW BANK 1 A9 BANK 0 DQM I/O t RCD t RAS t RC < > < > ACT READ CAS latency = 2, burst length = 4 ...
Page 39
... IS42S16128 Read Cycle / Auto-Precharge CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A7 ROW ROW BANK 1 A9 BANK 0 DQM I/O t RCD t RAS t RC < > < ACT READA CAS latency = 2, burst length = 4 Integrated Silicon Solution, Inc. — ...
Page 40
... IS42S16128 Read Cycle / Full Page CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A7 ROW ROW BANK 0 A9 DQM I/O t RCD t RAS t RC (BANK 0) < > < ACT 0 ...
Page 41
... IS42S16128 Read Cycle / Ping-Pong Operation (Bank Switching CLK t CHI t t CKS CKE t CKA RAS CAS A0-A7 ROW ROW BANK 0 A9 DQM I/O t RRD (BANK RCD ...
Page 42
... IS42S16128 Write Cycle CLK t CHI t CKS CKE t CKA RAS CAS A0-A7 ROW ROW BANK 1 A9 BANK 0 DQM I/O t RCD t RAS t RC < > ACT CAS latency = 2, burst length = 4 ...
Page 43
... IS42S16128 Write Cycle / Auto-Precharge CLK t CHI CKS CK CL CKE t CKA RAS CAS A0-A7 ROW ROW BANK 1 BANK 0 DQM I/O t RCD t RAS t RC < > ACT CAS latency = 2, burst length = 4 Integrated Silicon Solution, Inc. — ...
Page 44
... IS42S16128 Write Cycle / Full Page CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A7 ROW ROW BANK 0 A9 DQM I/O t RCD t RAS t RC < > ACT 0 CAS latency = 2, burst length = full page ...
Page 45
... IS42S16128 Write Cycle / Ping-Pong Operation CLK t CHI t t CKS CKE t CKA RAS CAS ROW A0- ROW BANK 0 A9 DQM I/O t RRD (BANK RCD (BANK 0) t RAS ...
Page 46
... IS42S16128 Read Cycle / Page Mode CLK t CHI t t CKS CKE t CKA RAS CAS A0-A7 ROW ROW BANK 1 A9 BANK 0 DQM I/O t RCD t RAS t RC < > ACT CAS latency = 2, burst length = 2 ...
Page 47
... IS42S16128 Read Cycle / Page Mode; Data Masking CLK t CHI t CKS CKE t CKA RAS CAS A0-A7 ROW ROW BANK 1 BANK 0 DQM I/O t RCD t RAS t RC < ...
Page 48
... IS42S16128 Write Cycle / Page Mode CLK t CHI t CKS CKE t CKA RAS CAS A0-A7 ROW ROW BANK 1 A9 BANK 0 DQM I/O t RCD t RAS t RC < > ACT CAS latency = 2, burst length = 2 ...
Page 49
... IS42S16128 Write Cycle / Page Mode; Data Masking CLK t CHI t CKS CKE t CKA RAS CAS A0-A7 ROW ROW BANK 1 A9 BANK 0 DQM I/O t RCD t RAS t RC < ...
Page 50
... IS42S16128 Read Cycle / Clock Suspend CLK t CHI CKS CL CK CKE t CKA RAS CAS ROW A0- ROW BANK 1 A9 BANK 0 DQM I/O t RCD t RAS t RC < > ACT 0 CAS latency = 2, burst length = 2 ...
Page 51
... IS42S16128 Write Cycle / Clock Suspend CLK t CHI t t CKS CKE t CKA RAS CAS A0-A7 ROW ROW BANK 1 A9 BANK 0 DQM I/O t RCD t RAS t RC < > ACT CAS latency = 2, burst length = 2 Integrated Silicon Solution, Inc. — ...
Page 52
... IS42S16128 Read Cycle / Precharge Termination CLK t CHI CKS CL CK CKE t CKA RAS CAS ROW A0- ROW BANK 0 DQM I/O t RCD t RAS t RC < > ACT 0 CAS latency = 2, burst length = 4 ...
Page 53
... IS42S16128 Write Cycle / Precharge Termination CLK t CHI t t CKS CKE t CKA RAS CAS A0-A7 ROW ROW BANK DQM t DS I/O t RCD t RAS t RC < > ACT 0 CAS latency = 2, burst length = 4 Integrated Silicon Solution, Inc. — ...
Page 54
... IS42S16128 Read Cycle / Byte Operation CLK t CHI t t CKS CKE t CKA RAS CAS A0-A7 ROW ROW BANK 1 BANK 0 UDQM LDQM I/O8-15 I/O0-7 t RCD t RAS t RC < > ACT ...
Page 55
... IS42S16128 Write Cycle / Byte Operation CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A7 ROW ROW BANK 1 BANK 0 UDQM LDQM I/O8-15 I/O0-7 t RCD t RAS t RC < > ACT CAS latency = 2, burst length = 4 Integrated Silicon Solution, Inc. — ...
Page 56
... IS42S16128 Read Cycle, Write Cycle / Burst Read, Single Write CLK t CHI CKS CK CL CKE t CKA RAS CAS A0-A7 ROW ROW BANK 1 A9 BANK 0 DQM I/O t RCD t RAS ...
Page 57
... IS42S16128 Read Cycle CLK t CHI CKS CK CL CKE t CKA RAS CAS A0-A7 ROW ROW BANK 1 A9 BANK 0 DQM I/O t RCD t RAS t RC < > ACT CAS latency = 3, burst length = 4 Integrated Silicon Solution, Inc. — ...
Page 58
... IS42S16128 Read Cycle / Auto-Precharge CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A7 ROW ROW BANK 1 A9 BANK 0 DQM I/O t RCD t RAS t RC < > ACT CAS latency = 3, burst length = 4 ...
Page 59
... IS42S16128 Read Cycle / Full Page CLK t CHI t t CKS CKE t CKA RAS CAS A0-A7 ROW ROW BANK 0 A9 DQM I/O t RCD (BANK 0) t RAS (BANK (BANK 0) < ...
Page 60
... IS42S16128 Read Cycle / Ping Pong Operation (Bank Switching CLK t CHI t CKS CKE t CKA RAS CAS A0-A7 ROW ROW BANK 0 A9 DQM I/O t RRD (BANK RCD ...
Page 61
... IS42S16128 Write Cycle CLK t CHI t CKS CKE t CKA RAS CAS A0-A7 ROW ROW BANK 1 A9 BANK 0 DQM I/O t RCD t RAS t RC < > ACT CAS latency = 3, burst length = 4 Integrated Silicon Solution, Inc. — ...
Page 62
... IS42S16128 Write Cycle / Auto-Precharge CLK t CHI t t CKS CKE t CKA RAS CAS A0-A7 ROW ROW BANK 1 A9 BANK 0 DQM I/O t RCD t RAS t RC < > ACT CAS latency = 3, burst length = 4 ...
Page 63
... IS42S16128 Write Cycle / Full Page CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A7 ROW ROW BANK 0 A9 DQM I/O t RCD t RAS t RC < > ACT 0 CAS latency = 3, burst length = full page Integrated Silicon Solution, Inc. — ...
Page 64
... IS42S16128 Write Cycle / Ping-Pong Operation (Bank Switching CLK t CHI t t CKS CKE t CKA RAS CAS A0-A7 ROW ROW BANK 0 A9 DQM I/O t RRD (BANK RCD ...
Page 65
... IS42S16128 Read Cycle / Page Mode CLK t CHI t CKS CKE t CKA RAS CAS A0-A7 ROW ROW BANK 1 BANK 0 DQM I/O t RCD t RAS t RC < > ACT CAS latency = 3, burst length = 2 Integrated Silicon Solution, Inc. — ...
Page 66
... IS42S16128 Read Cycle / Page Mode; Data Masking CLK t CHI t t CKS CKE t CKA RAS CAS A0-A7 ROW ROW BANK 1 BANK 0 DQM I/O t RCD t RAS t RC < ...
Page 67
... IS42S16128 Write Cycle / Page Mode CLK t CHI t t CKS CKE t CKA RAS CAS A0-A7 ROW ROW BANK 0 A9 DQM I/O t RCD t RAS t RC < > ACT CAS latency = 3, burst length = 2 Integrated Silicon Solution, Inc. — ...
Page 68
... IS42S16128 Write Cycle / Page Mode; Data Masking CLK t CHI CKS CK CL CKE t CKA RAS CAS A0-A7 ROW ROW BANK BANK 1 A9 BANK 0 BANK DQM t DS ...
Page 69
... IS42S16128 Read Cycle / Clock Suspend CLK t CHI t t CKS CKE t CKA RAS CAS A0-A7 ROW ROW BANK 1 A9 BANK 0 DQM I/O t RCD t RAS t RC < > ACT CAS latency = 3, burst length = 2 Integrated Silicon Solution, Inc. — ...
Page 70
... IS42S16128 Write Cycle / Clock Suspend CLK t CHI t t CKS CKE t CKA RAS CAS A0-A7 ROW ROW BANK 1 A9 BANK 0 DQM I/O t RCD t RAS t RC < > ACT CAS latency = 3, burst length = 2 ...
Page 71
... IS42S16128 Read Cycle / Precharge Termination CLK t CHI t t CKS CKE t CKA RAS CAS A0-A7 ROW ROW BANK 0 DQM I/O t RCD t RAS t RC < > ACT 0 CAS latency = 3, burst length = 4 Integrated Silicon Solution, Inc. — ...
Page 72
... IS42S16128 Write Cycle / Precharge Termination CLK t CHI t t CKS CKE t CKA RAS CAS A0-A7 ROW ROW BANK 0 DQM I/O t RCD t RAS t RC < > ACT 0 CAS latency = 3, burst length = 4 ...
Page 73
... IS42S16128 Read Cycle / Byte Operation CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A7 ROW ROW BANK 1 BANK 0 UDQM LDQM I/O8-15 I/O0-7 t RCD t RAS t RC < > ACT CAS latency = 3, burst length = 4 Integrated Silicon Solution, Inc. — ...
Page 74
... IS42S16128 Write Cycle / Byte Operation CLK t CHI t t CKS CKE t CKA RAS CAS A0-A7 ROW ROW BANK 1 BANK 0 UDQM LDQM I/O8-15 I/O0-7 t RCD t RAS t RC < > ACT ...
Page 75
... IS42S16128 Read Cycle, Write Cycle / Burst Read, Single Write CLK t CHI CKS CL CK CKE t CKA RAS CAS A0-A7 ROW ROW BANK 1 A9 BANK 0 DQM I RAS ...