IS61S6432-6PQ Integrated Silicon Solution, IS61S6432-6PQ Datasheet

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IS61S6432-6PQ

Manufacturer Part Number
IS61S6432-6PQ
Description
64K x 32 synchronous pipeline static RAM
Manufacturer
Integrated Silicon Solution
Datasheet

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IS61S6432
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
• Pentium™ or linear burst sequence control using
• Three chip enables for simple depth expansion
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 100-Pin TQFP and PQFP package
• Single +3.3V power supply
• Two Clock enables and one Clock disable to
• Control pins mode upon power-up:
• Industrial temperature available
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. • 1-800-379-4774
Rev. B
06/28/01
FAST ACCESS TIME
64K x 32 SYNCHRONOUS
PIPELINE STATIC RAM
Symbol
control
MODE input
and address pipelining
eliminate multiple bank bus contention
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GNDQ
or VCCQ to alter their power-up state
Note:
1. ADVANCE INFORMATION ONLY.
t
t
KQ
KC
Parameter
CLK Access Time
Cycle Time
Frequency
-200
200
4
5
(1)
-166
166
5
6
-133
133
7.5
5
DESCRIPTION
The
synchronous static RAM designed to provide a burstable,
high-performance, secondary cache for the Pentium™,
680X0™, and PowerPC™ microprocessors. It is organized
as 65,536 words by 32 bits, fabricated with
CMOS technology. The device integrates a 2-bit burst
counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous
inputs pass through registers controlled by a positive-edge-
triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3
controls DQ17-DQ24, BW4 controls DQ25-DQ32,
conditioned by BWE being LOW. A LOW on GW input would
cause all bytes to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally by the IS61S6432 and controlled by the ADV
(burst address advance) input pin.
Asynchronous signals include output enable (OE), sleep
mode input (ZZ), clock (CLK) and burst mode input (MODE).
A HIGH input on the ZZ pin puts the SRAM in the power-
down state. When ZZ is pulled LOW (or no connect), the
SRAM normally operates after three cycles of the wake-up
period. A LOW input, i.e., GND
LINEAR Burst. A V
INTERLEAVED Burst.
-117
ISSI
117
8.5
5
IS61S6432 is a high-speed, low-power
100
10
-5
5
CCQ
(or no connect) on MODE pin selects
12
83
-6
6
Q
ISSI
, on MODE pin selects
13
75
-7
7
ISSI
15
66
-8
8
JUNE 2001
's advanced
MHz
Unit
ns
ns
®
1

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IS61S6432-6PQ Summary of contents

Page 1

... Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally by the IS61S6432 and controlled by the ADV (burst address advance) input pin. Asynchronous signals include output enable (OE), sleep mode input (ZZ), clock (CLK) and burst mode input (MODE). ...

Page 2

... IS61S6432 BLOCK DIAGRAM CLK ADV ADSC ADSP 16 A15-A0 GW BWE BW4 BW3 BW2 BW1 CE1 CE2 CE3 OE PB MODE A0' Q0 CLK A0 BINARY COUNTER A1 CLR ADDRESS REGISTER CE CLK DQ32-DQ25 BYTE WRITE REGISTERS CLK D Q DQ24-DQ17 BYTE WRITE REGISTERS ...

Page 3

... IS61S6432 PIN CONFIGURATION 100-Pin TQFP and PQFP (Top View) 100 DQ17 3 DQ18 4 VCCQ 5 GNDQ 6 DQ19 7 DQ20 8 DQ21 9 DQ22 10 GNDQ 11 VCCQ 12 DQ23 13 DQ24 14 VCCQ 15 VCC GND 18 DQ25 19 DQ26 20 VCCQ 21 GNDQ ...

Page 4

... IS61S6432 TRUTH TABLE Address Operation Used Deselected, Power-down None Deselected, Power-down None Deselected, Power-down None Deselected, Power-down None Deselected, Power-down None Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst External Read Cycle, Begin Burst External ...

Page 5

... IS61S6432 INTERLEAVED BURST ADDRESS TABLE External Address 1st Burst Address LINEAR BURST ADDRESS TABLE A1', A0' = 1,1 ABSOLUTE MAXIMUM RATINGS Symbol Parameter T Temperature Under Bias BIAS T Storage Temperature STG P Power Dissipation D I Output Current (per I/O) OUT Voltage Relative to GND for I/O Pins ...

Page 6

... IS61S6432 DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL V Input HIGH Voltage IH V Input LOW Voltage IL I Input Leakage Current LI I Output Leakage Current LO Notes: 1. MODE pin have an internal pull-up. ZZ pin has an internal pull-down. These pins may Connect, tied to GND,or tied to V ...

Page 7

... IS61S6432 (1,2) CAPACITANCE Symbol Parameter C Input Capacitance IN C Input/Output Capacitance OUT Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions 25° MHz, Vcc = 3.3V TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times ...

Page 8

... IS61S6432 READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Clock Access Time KQ (2) t Clock High to Output Invalid KQX t (2,3) Clock High to Output Low-Z KQLZ (2,3) t Clock High to Output High-Z KQHZ t Output Enable to Output Valid ...

Page 9

... IS61S6432 READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) (Continued) Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Clock Access Time KQ (1) t Clock High to Output Invalid KQX t (1,2) Clock High to Output Low-Z KQLZ (1,2) t Clock High to Output High-Z KQHZ ...

Page 10

... IS61S6432 READ CYCLE TIMING: PIPELINE t KC CLK ADSP t SS ADSC ADV A15-A0 RD1 BWE BW4-BW1 t t CES CEH CE1 t t CES CEH CE2 t t CES CEH CE3 t OEQ OE t OELZ High-Z DATA OUT t KQLZ ...

Page 11

... IS61S6432 WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Address Setup Time AS t Address Status Setup Time SS t Write Setup Time WS t Data In Setup Time DS t Chip Enable Setup Time ...

Page 12

... IS61S6432 WRITE CYCLE TIMING t CLK ADSP ADSC ADV must be inactive for ADSP Write ADV A15-A0 WR1 BWE t WS BW4-BW1 WR1 t t CES CEH CE1 t t CES CEH CE2 t t CES CEH CE3 OE High-Z DATA ...

Page 13

... IS61S6432 READ/WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Clock Access Time KQ (2) t Clock High to Output Invalid KQX t (2,3) Clock High to Output Low-Z KQLZ (2,3) t Clock High to Output High-Z KQHZ t Output Enable to Output Valid ...

Page 14

... IS61S6432 READ/WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Clock Access Time KQ (1) t Clock High to Output Invalid KQX t (1,2) Clock High to Output Low-Z KQLZ (1,2) t Clock High to Output High-Z KQHZ t Output Enable to Output Valid ...

Page 15

... IS61S6432 READ/WRITE CYCLE TIMING: PIPELINE CLK ADSP t SS ADSC ADV A15-A0 RD1 BWE BW4-BW1 t t CES CEH CE1 t t CES CEH CE2 t t CES CEH CE3 t OEQ OE t OELZ High-Z DATA OUT t KQLZ t KQ ...

Page 16

... IS61S6432 SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Clock Access Time KQ (3) t Clock High to Output Invalid KQX (3,4) t Clock High to Output Low-Z KQLZ (3,4) t Clock High to Output High-Z KQHZ t Output Enable to Output Valid ...

Page 17

... IS61S6432 SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Continued) Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Clock Access Time KQ t (2) Clock High to Output Invalid KQX (2,3) t Clock High to Output Low-Z KQLZ t (2,3) Clock High to Output High-Z KQHZ t Output Enable to Output Valid ...

Page 18

... IS61S6432 SNOOZE AND RECOVERY CYCLE TIMING CLK ADSP ADSC ADV A15-A0 RD1 GW BWE BW4-BW1 t t CES CEH CE1 t t CES CEH CE2 t t CES CEH CE3 t OEQ OE t OELZ High-Z DATA OUT t KQLZ t High-Z DATA IN ZZ ...

Page 19

... NOTICE Integrated Silicon Solution, Inc. ISSI ® Order Part Number Package IS61S6432-117TQI TQFP IS61S6432-117PQI PQFP IS61S6432-5TQI TQFP IS61S6432-5PQI PQFP IS61S6432-6TQI TQFP IS61S6432-6PQI PQFP IS61S6432-7TQI TQFP IS61S6432-7PQI PQFP IS61S6432-8TQI TQFP IS61S6432-8PQI PQFP ISSI ® 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi ...

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