IS61LV632A-7TQ Integrated Silicon Solution, IS61LV632A-7TQ Datasheet

no-image

IS61LV632A-7TQ

Manufacturer Part Number
IS61LV632A-7TQ
Description
32K x 32 synchronous fast static RAM
Manufacturer
Integrated Silicon Solution
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IS61LV632A-7TQ
Manufacturer:
ISSC
Quantity:
992
Part Number:
IS61LV632A-7TQ
Manufacturer:
ISSI
Quantity:
20 000
Company:
Part Number:
IS61LV632A-7TQ
Quantity:
1 200
IS61LV632A
32K x 32 SYNCHRONOUS FAST STATIC RAM
FEATURES
• Fast access time:
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
• Pentium™ or linear burst sequence control
• Three chip enables for simple depth expansion
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 100-Pin TQFP and PQFP package
• 3.3V Vcc and 2.5V V
• Two Clock enables and one Clock disable to
• Control pins mode upon power-up:
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
– 4 ns-125 MHz; 5 ns-100 MHz;
control
using MODE input
and address pipelining
eliminate multiple bank bus contention.
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GND
or V
6 ns-83 MHz; 7 ns-75 MHz; 8 ns-66 MHz
CCQ
to alter their power-up state
CCQ
for 2.5V I/Os
Q
DESCRIPTION
The
nous static RAM designed to provide a burstable, high-
performance, secondary cache for the i486™, Pentium™,
680X0™, and PowerPC™ microprocessors. It is organized
as 32,768 words by 32 bits, fabricated with
CMOS technology. The device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs into
a single monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single clock
input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3
controls DQ17-DQ24, BW4 controls DQ25-DQ32, conditioned
by BWE being LOW. A LOW on GW input would cause all bytes
to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated inter-
nally by the IS61LV632A and controlled by the ADV (burst
address advance) input pin.
Asynchronous signals include output enable (OE), sleep mode
input (ZZ), clock (CLK) and burst mode input (MODE). A HIGH
input on the ZZ pin puts the SRAM in the power-down state.
When ZZ is pulled LOW (or no connect), the SRAM normally
operates after three cycles of the wake-up period. A LOW
input, i.e., GND
(or no connect) on MODE pin selects INTERLEAVED Burst.
ISSI
IS61LV632A is a high-speed, low-power synchro-
Q
, on MODE pin selects LINEAR Burst. A V
ISSI
APRIL 2001
's advanced
CCQ
®
1

Related parts for IS61LV632A-7TQ

IS61LV632A-7TQ Summary of contents

Page 1

... Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated inter- nally by the IS61LV632A and controlled by the ADV (burst Q address advance) input pin. Asynchronous signals include output enable (OE), sleep mode input (ZZ), clock (CLK) and burst mode input (MODE) ...

Page 2

... IS61LV632A BLOCK DIAGRAM CLK ADV ADSC ADSP 15 A14-A0 GW BWE BW4 BW3 BW2 BW1 CE1 CE2 CE3 OE 2 MODE A0 CLK BINARY COUNTER A1 CLR ADDRESS REGISTER CE CLK D Q DQ32-DQ25 BYTE WRITE REGISTERS CLK D Q DQ24-DQ17 BYTE WRITE REGISTERS ...

Page 3

... IS61LV632A PIN CONFIGURATION 100-Pin TQFP and PQFP (Top View) 100 DQ17 3 DQ18 4 VCCQ 5 GNDQ 6 DQ19 7 DQ20 8 DQ21 9 DQ22 10 GNDQ 11 VCCQ 12 DQ23 DQ24 VCC GND 18 DQ25 19 DQ26 20 VCCQ ...

Page 4

... IS61LV632A TRUTH TABLE ADDRESS OPERATION USED Deselected, Power-down None Deselected, Power-down None Deselected, Power-down None Deselected, Power-down None Deselected, Power-down None Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst External Read Cycle, Begin Burst External ...

Page 5

... IS61LV632A INTERLEAVED BURST ADDRESS TABLE (MODE = V External Address 1st Burst Address LINEAR BURST ADDRESS TABLE (MODE = GND A1', A0' = 1,1 ABSOLUTE MAXIMUM RATINGS Symbol Parameter T Temperature Under Bias BIAS T Storage Temperature STG P Power Dissipation D I Output Current (per I/O) OUT ...

Page 6

... IS61LV632A OPERATING RANGE Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL V Input HIGH Voltage IH V Input LOW Voltage IL I Input Leakage Current LI I Output Leakage Current ...

Page 7

... IS61LV632A (1,2) CAPACITANCE Symbol Parameter C Input Capacitance IN C Input/Output Capacitance OUT Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions 25° MHz, Vcc = 3.3V TEST CONDITIONS Parameter Input Pulse Level for I/O Pins Input Pulse Level for Input Pins ...

Page 8

... IS61LV632A READ CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Clock Access Time KQ t (2) Clock High to KQX Output Invalid t (2,3) Clock High to KQLZ Output Low-Z t (2,3) Clock High to KQHZ Output High-Z t Output Enable to OEQ Output Valid ...

Page 9

... IS61LV632A READ CYCLE TIMING CLK ADSP t SS ADSC ADV A14-A0 RD1 BWE BW4-BW1 t t CES CEH CE1 t t CES CEH CE2 t t CES CEH CE3 t OEQ OE t OELZ High-Z DATA OUT t KQLZ t KQ High-Z ...

Page 10

... IS61LV632A WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Address Setup Time AS t Address Status SS Setup Time t Write Setup Time WS t Data In Setup Time DS t Chip Enable Setup Time 2.5 CES t Address Advance ...

Page 11

... IS61LV632A WRITE CYCLE TIMING CLK ADSP ADSC ADV must be inactive for ADSP Write ADV A14-A0 WR1 BWE t WS BW4-BW1 WR1 t t CES CEH CE1 t t CES CEH CE2 t t CES CEH CE3 OE High-Z DATA ...

Page 12

... IS61LV632A READ/WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Clock Access Time KQ t (2) Clock High to KQX Output Invalid t (2,3) Clock High to KQLZ Output Low-Z t (2,3) Clock High to KQHZ Output High-Z t Output Enable to OEQ Output Valid ...

Page 13

... IS61LV632A READ/WRITE CYCLE TIMING CLK ADSP ADSC ADV A14-A0 RD1 BWE BW4-BW1 t t CES CEH CE1 t t CES CEH CE2 t t CES CEH CE3 t OEQ OE t OELZ High-Z DATA OUT t KQLZ t High-Z DATA IN Single Read Integrated Silicon Solution, Inc. — ...

Page 14

... IS61LV632A SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Clock Access Time KQ t (4) Clock High to KQX Output Invalid t (4,5) Clock High to KQLZ Output Low-Z t (4,5) Clock High to KQHZ Output High-Z t Output Enable to ...

Page 15

... IS61LV632A SNOOZE AND RECOVERY CYCLE TIMING CLK ADSP ADSC ADV A14-A0 RD1 GW BWE BW4-BW1 t t CES CEH CE1 t t CES CEH CE2 t t CES CEH CE3 t OEQ OE t OELZ High-Z DATA OUT t KQLZ High-Z DATA IN ZZ Single Read Integrated Silicon Solution, Inc. — ...

Page 16

... IS61LV632A-4PQ 5 IS61LV632A-5TQ 5 IS61LV632A-5PQ 6 IS61LV632A-6TQ 6 IS61LV632A-6PQ 7 IS61LV632A-7TQ 7 IS61LV632A-7PQ 8 IS61LV632A-8TQ 8 IS61LV632A-8PQ Order Part Number 6 IS61LV632A-6TQI 6 IS61LV632A-6PQI 7 IS61LV632A-7TQI 7 IS61LV632A-7PQI 8 IS61LV632A-8TQI 8 IS61LV632A-8PQI Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI Package TQFP PQFP TQFP PQFP TQFP PQFP TQFP PQFP TQFP PQFP Package TQFP PQFP TQFP PQFP ...

Related keywords