IS61LV12816-12T Integrated Silicon Solution, IS61LV12816-12T Datasheet
IS61LV12816-12T
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IS61LV12816-12T Summary of contents
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... Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61LV12816 is packaged in the JEDEC standard 44-pin 400-mil SOJ, 44-pin TSOP, 44-pin LQFP, and 48-pin mini BGA (6mm x 8mm). DECODER ...
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... IS61LV12816 PIN CONFIGURATIONS 44-Pin SOJ ( I/ I/O15 I/ I/O14 I/ I/O13 I/ I/O12 Vcc 11 34 GND GND 12 33 Vcc I/ I/O11 I/ I/O10 I/ I/ A16 18 27 ...
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... IS61LV12816 PIN DESCRIPTIONS A0-A16 Address Inputs I/O0-I/O15 Data Inputs/Outputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15 Connection Vcc Power GND Ground ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Power Supply Voltage Relative to GND CC V Terminal Voltage with Respect to GND ...
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... IS61LV12816 TRUTH TABLE WE Mode Not Selected X Output Disabled H X Read Write POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions = Max Vcc Operating Supply Current mA Max. OUT I TTL Standby V = Max Current • V (TTL Inputs) ...
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... IS61LV12816 (1) CAPACITANCE Symbol Parameter C Input Capacitance IN C Input/Output Capacitance OUT Note: 1. Tested initially and after any design or process changes that may affect these parameters. READ CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Read Cycle Time RC t Address Access Time AA t Output Hold Time ...
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... IS61LV12816 AC WAVEFORMS (1,2) (Address Controlled) ( READ CYCLE NO. 1 ADDRESS D OUT PREVIOUS DATA VALID READ CYCLE NO. 2 (1,3) ADDRESS LZCE LB LZB HIGH-Z D OUT Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB Address is valid prior to or coincident with CE LOW transition. ...
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... IS61LV12816 WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Write Cycle Time Write End t SCE t Address Setup Time AW to Write End t Address Hold from Write End HA t Address Setup Time SA LB, UB Valid to End of Write t PWB WE Pulse Width (OE = HIGH PWE WE Pulse Width (OE = LOW) ...
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... IS61LV12816 (1,2) (CE Controlled HIGH or LOW) WRITE CYCLE NO. 1 ADDRESS UB DATA UNDEFINED OUT VALID ADDRESS t SCE PWE1 t PWE2 t PBW t HZWE HIGH DATA VALID IN Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI ® LZWE t HD UB_CEWR1.eps Rev. A ...
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... IS61LV12816 (1) (WE Controlled HIGH during Write Cycle) WRITE CYCLE NO. 2 ADDRESS OE CE LOW UB DATA UNDEFINED OUT D IN WRITE CYCLE NO. 3 (WE Controlled LOW During Write Cycle) ADDRESS LOW OE CE LOW UB DATA UNDEFINED OUT D IN Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev ...
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... IS61LV12816 (LB, UB Controlled, Back-to-Back Write) WRITE CYCLE NO. 4 ADDRESS OE CE LOW WE UB HZWE D OUT DATA UNDEFINED D IN Notes: 1. The internal Write time is defined by the overlap LOW, UB and/ LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The referenced to the rising or falling edge of the signal that terminates the Write ...
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... IS61LV12816-10KI 400-mil Plastic SOJ IS61LV12816-10LQI LQFP IS61LV12816-10TI Plastic TSOP 12 IS61LV12816-12BI mini BGA (6mm x 8mm) IS61LV12816-12KI 400-mil Plastic SOJ IS61LV12816-12LQI LQFP IS61LV12816-12TI Plastic TSOP 15 IS61LV12816-15BI mini BGA (6mm x 8mm) IS61LV12816-15KI 400-mil Plastic SOJ IS61LV12816-15LQI LQFP IS61LV12816-15TI Plastic TSOP Integrated Silicon Solution, Inc. ...