IS61SF12832-10TQ Integrated Silicon Solution, IS61SF12832-10TQ Datasheet

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IS61SF12832-10TQ

Manufacturer Part Number
IS61SF12832-10TQ
Description
Manufacturer
Integrated Silicon Solution
Datasheet

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Part Number
Manufacturer
Quantity
Price
Part Number:
IS61SF12832-10TQ
Manufacturer:
ISSI
Quantity:
50
IS61SF12832
IS61SF12836
128K x 32, 128K x 36 SYNCHRONOUS
FLOW-THROUGH STATIC RAM
FEATURES
• Fast access times: 7.5 ns, 8 ns, 8.5 ns, 10 ns,
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data
• Pentium™ or linear burst sequence control
• Three chip enables for simple depth expansion
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and
• Single +3.3V +10%, –5% power supply
• Power-down snooze mode
FAST ACCESS TIME
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
and 12 ns
inputs and control signals
using MODE input
and address pipelining
119-pin PBGA package
Symbol
t
t
KQ
KC
Parameter
Clock Access Time
Cycle Time
Frequency
117
7.5
7.5
8.5
DESCRIPTION
The
synchronous static RAM designed to provide a burstable,
high-performance memory for high speed networking and
communication applications.
words by 32 bits or 36 bits, fabricated with
CMOS technology. The device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs into
a single monolithic circuit. All synchronous inputs pass
through registers controlled by a positive-edge-triggered
single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQa, BW2 controls DQb, BW3 controls DQc,
BW4 controls DQd, conditioned by BWE being LOW. A LOW
on GW input would cause all bytes to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally
and controlled by the ADV (burst address advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left floating.
ISSI
100
10
8
8
IS61SF12832 and IS61SF12836 are high-speed
8.5
8.5
11
90
10
10
15
66
It is organized as 131,072
ISSI
12
12
15
66
ISSI
APRIL 2001
's advanced
Units
MHz
ns
ns
®
1

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IS61SF12832-10TQ Summary of contents

Page 1

... Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 DESCRIPTION ISSI The IS61SF12832 and IS61SF12836 are high-speed synchronous static RAM designed to provide a burstable, high-performance memory for high speed networking and communication applications. words by 32 bits or 36 bits, fabricated with CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit ...

Page 2

... IS61SF12832 IS61SF12836 BLOCK DIAGRAM CLK ADV ADSC ADSP 17 A16-A0 GW BWE BW4 BW3 BW2 BW1 CE CE2 CE2 OE 2 MODE A0 CLK BINARY COUNTER A1 128K x 32, 128K x 36 CLR MEMORY ARRAY ADDRESS REGISTER CE CLK DQd BYTE WRITE ...

Page 3

... IS61SF12832 IS61SF12836 PIN CONFIGURATION 119-pin PBGA (Top View ADSP VCCQ ADSC NC CE2 VCC A12 D DQc1 NC GND NC GND E CE DQc2 DQc3 GND GND F OE VCCQ DQc4 GND GND G BW3 ADV BW2 DQc5 DQc6 H GW DQc7 ...

Page 4

... IS61SF12832 IS61SF12836 PIN CONFIGURATION 119-pin PBGA (Top View ADSP VCCQ ADSC NC CE2 VCC A12 D DQc1 DQPc GND NC GND E CE DQc2 DQc3 GND GND F OE VCCQ DQc4 GND GND G BW3 ADV BW2 DQc5 DQc6 H GW ...

Page 5

... IS61SF12832 IS61SF12836 TRUTH TABLE Address Operation Used Deselected, Power-down None Deselected, Power-down None Deselected, Power-down None Deselected, Power-down None Deselected, Power-down None Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst External Read Cycle, Continue Burst ...

Page 6

... IS61SF12832 IS61SF12836 INTERLEAVED BURST ADDRESS TABLE (MODE = V External Address 1st Burst Address LINEAR BURST ADDRESS TABLE (MODE = GND) A1', A0' = 1,1 ABSOLUTE MAXIMUM RATINGS Symbol Parameter T Temperature Under Bias BIAS T Storage Temperature STG P Power Dissipation D I Output Current (per I/O) ...

Page 7

... IS61SF12832 IS61SF12836 OPERATING RANGE Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL V Input HIGH Voltage IH V Input LOW Voltage IL I Input Leakage Current LI I Output Leakage Current ...

Page 8

... IS61SF12832 IS61SF12836 (1,2) CAPACITANCE Symbol Parameter C Input Capacitance IN C Input/Output Capacitance OUT Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions 25° MHz, Vcc = 3.3V TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times ...

Page 9

... IS61SF12832 IS61SF12836 READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol Parameter (3) f Clock Frequency MAX t (3) Cycle Time KC t Clock High Time KH t (3) Clock Low Time KL (3) t Clock Access Time KQ t (1) Clock High to Output Invalid KQX (1,2) t Clock High to Output Low-Z KQLZ ...

Page 10

... IS61SF12832 IS61SF12836 READ/WRITE CYCLE TIMING CLK ADSP ADSC ADV A16-A0 RD1 BWE BW4-BW1 t t CES CEH CES CEH CE2 t t CES CEH CE2 OE High-Z DATA OUT t KQLZ t KQ High-Z DATA IN Single Read Flow-through ...

Page 11

... IS61SF12832 IS61SF12836 WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol Parameter t (1) Cycle Time KC (1) t Clock High Time KH t (1) Clock Low Time KL (1) t Address Setup Time AS (1) t Address Status Setup Time SS (1) t Write Setup Time WS t (1) Data In Setup Time DS t (1) Chip Enable Setup Time ...

Page 12

... IS61SF12832 IS61SF12836 WRITE CYCLE TIMING CLK ADSP ADSC ADV must be inactive for ADSP Write ADV A16-A0 WR1 BWE t WS BW4-BW1 WR1 t t CES CEH CES CEH CE2 t t CES CEH CE2 OE High-Z DATA ...

Page 13

... IS61SF12832 IS61SF12836 SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol Parameter t (3) Cycle Time KC (3) t Clock High Time KH t (3) Clock Low Time KL (3) t Clock Access Time KQ (1) t Clock High to Output Invalid KQX (1,2) t Clock High to Output Low-Z KQLZ t (1,2) Clock High to Output High-Z ...

Page 14

... IS61SF12832 IS61SF12836 SNOOZE AND RECOVERY CYCLE TIMING CLK ADSP ADSC ADV A16-A0 RD1 GW BWE BW4-BW1 t t CES CEH CES CEH CE2 t t CES CEH CE2 t OEQ OE t OELZ High-Z DATA OUT t KQLZ t High-Z DATA IN ZZ ...

Page 15

... Order Part Number 7.5 IS61SF12832-7.5TQ IS61SF12832-7.5B 8 IS61SF12832-8TQ IS61SF12832-8B 8.5 IS61SF12832-8.5TQ IS61SF12832-8.5B 10 IS61SF12832-10TQ IS61SF12832-10B 12 IS61SF12832-12TQ IS61SF12832-12B Order Part Number 8 IS61SF12832-8TQI 8.5 IS61SF12832-8.5TQI 10 IS61SF12832-10TQI 12 IS61SF12832-12TQI ISSI Package TQFP PBGA TQFP PBGA TQFP PBGA TQFP PBGA TQFP PBGA Package TQFP TQFP TQFP TQFP ® 15 ...

Page 16

... IS61SF12832 IS61SF12836 ORDERING INFORMATION Commercial Range: 0°C to +70°C Frequency Industrial Range: –40°C to +85°C Frequency 16 Order Part Number 7.5 IS61SF12836-7.5TQ IS61SF12836-7.5B 8 IS61SF12836-8TQ IS61SF12836-8B 8.5 IS61SF12836-8.5TQ IS61SF12836-8.5B 10 IS61SF12836-10TQ IS61SF12836-10B 12 IS61SF12836-12TQ IS61SF12836-12B Order Part Number 8 IS61SF12836-8TQI 8.5 IS61SF12836-8.5TQI 10 IS61SF12836-10TQI 12 IS61SF12836-12TQI Integrated Silicon Solution, Inc. ...

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