PI74SSTVF16859ZBE Pericom Semiconductor, PI74SSTVF16859ZBE Datasheet

PI74SSTVF16859ZBE

Manufacturer Part Number

PI74SSTVF16859ZBE

Description

Manufacturer

Pericom Semiconductor

Datasheet

1.PI74SSTVF16859ZBE.pdf (8 pages)

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Product Features

• PI74 SSTVF16859 is designed for low-voltage operation,

• Supports SSTL_2 Class I specifications on outputs

• All Inputs are SSTL_2 Compatible, except RESET

• Designed for DDR Memory

• Flow-Through Architecture

• Packages:

Logic Block Diagram - TSSOP

Logic Block Diagram - QFN

Product Pin Description

CLK

GND

RESET

2.5V for PC1600 ~ PC2700; 2.6V for PC3200

which is LVCMOS.

64-pin, 240-mil wide plastic TSSOP (A)

56-pin, Plastic Very Thin Fine Pitch Quad Flat

(Lead-free packages are available)

RESET

Pin Name

DDQ

REF

No Lead QFN (ZB)

CLK

REF

TO 12 OTHER CHANNELS

Clock Input, Positive Differential Input

Clock Input, Negative Differential Input

Ground

Core Supply Voltage

Output Supply Voltage

Reset (Active Low) LVCMOS

Data Input, D1-D13

Data Output, Q1-Q13

Input Reference Voltage

Description

CLK

Q1A

Q1B

Product Description

Pericom Semiconductor’s PI74SSTVF16859 logic circuit is produced

using the Company’s advanced sub-micron CMOS technology,

achieving industry leading speed.

All inputs are compatible with the JEDEC standard for SSTL_2,

except the LVCMOS reset (RESET) input. All outputs are SSTL_2,

Class II compatible.

The device operates from a differential clock (CLK and CLK). Data

registered at the crossing of CLK going HIGH, and CLK going LOW.

The PI74SSTVF16859 supports low-power standby operation. When

RESET is LOW, the differential input receivers are disabled, and

undriven (floating) data, clock and reference voltage (V

are allowed. In addition, when RESET is LOW, all registers are reset,

and all outputs are forced LOW. The LVCMOS RESET input must

always be held at a valid logic HIGH or LOW level.

To ensure defined outputs from the register before a stable clock

has been supplied, RESET must be held in the LOW state during

power up.

In the DDR DIMM application, RESET is specified to be completely

asynchronous with respect to CLK and CLK. Therefore, no timing

relationship can be guaranteed between the two. When entering

RESET, the register will be cleared and the outputs will be driven

LOW quickly, relative to the time to disable the differential input

receivers, thus ensuring no glitches on the output. However, when

coming out of RESET, the register will become active quickly, relative

to the time to enable the differential input receivers. When the data

inputs are LOW, and the clock is stable, during the time from the

LOW-to-HIGH transition of RESET until the input receivers

are fully enabled, the design must ensure that the outputs will

remain LOW.

Pericom’s PI74SSTVF16859 is characterized for operation from

0°C to 70°C.

Truth Table

Notes:

1. H = High Signal Level

RESET

L = Low Signal Level

X = Irrelevant or floating

= Transition LOW-to-HIGH

= Transition HIGH-to-LOW

13-Bit to 26-Bit Registered Buffer

(1)

Floating

L or H

CLK

X or

Inputs

Floating

L or H

CLK

X or

PI74SSTVF16859

2. Output level before the

indicated steady state

input conditions were

established.

Floating

X or

PS8657A

Outputs

REF

) inputs

(2)

04/08/03

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PI74SSTVF16859ZBE Summary of contents

Page 1

... V Input Reference Voltage REF Product Description Pericom Semiconductor’s PI74SSTVF16859 logic circuit is produced using the Company’s advanced sub-micron CMOS technology, achieving industry leading speed. All inputs are compatible with the JEDEC standard for SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible ...

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... DENOTES DIMENSIONS X.XX IN MILLIMETERS Notes: 1. Controlling dimensions in millimeters 2. Ref: JEDEC MO-220 variation VLLD-2 Ordering Information Ordering Code PI74SSTVF16859A PI74SSTVF16859AE PI74SSTVF16859ZB PI74SSTVF16859ZBE 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com .665 16.9 .673 17.1 .047 1.20 Max. .002 0.05 ...

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