S29AL016D70BAI020 SPANSION, S29AL016D70BAI020 Datasheet
S29AL016D70BAI020
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S29AL016D70BAI020 Summary of contents
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S29AL016D 16 Megabit ( 8-Bit 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory Data Sheet Distinctive Characteristics Architectural Advantages Single power supply operation — Full voltage range: 2.7 to 3.6 volt read and write op- erations ...
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General Description The S29AL016D Mbit, 3.0 Volt-only Flash memory organized as 2,097,152 bytes or 1,048,576 words. The device is offered in 48-ball FBGA, and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) ...
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... The system can also place the device into the standby mode. Power consump- tion is greatly reduced in both these modes. Spansion’s Flash technology combines years of Flash memory manufacturing ex- perience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via -Nordheim tunneling ...
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Table of Contents General Description . . . . . . . . . . . . . . . . . . . . . . . . 2 Product Selector Guide ...
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Product Selector Guide Family Part Number Speed Option Voltage Range: V Max access time ACC Max CE# access time Max OE# access time Note: See AC Characteristics for full ...
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Connection Diagrams A15 1 A14 2 A13 3 A12 4 A11 5 A10 A19 WE RESET RY/BY# 15 A18 16 A17 ...
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Connection Diagrams A6 B6 A13 A12 WE# RESET RY/BY A17 Special Handling Instructions Special handling is required for Flash Memory products in FBGA packages. ...
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Pin Configuration A0–A19 DQ0–DQ14 DQ15/A-1 BYTE# CE# OE# WE# RESET# RY/BY Logic Symbol addresses = 15 data inputs/outputs = DQ15 (data ...
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... Ordering Information S29AL016D Standard Products Spansion standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. S29AL016D DEVICE NUMBER/DESCRIPTION S29AL016D 16 Megabit Flash Memory manufactured using 200 nm process technology 3.0 Volt-only Read, Program, and Erase ...
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Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is com- posed of ...
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Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins CE# is the power control and selects the device. OE# is the output control IL and ...
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Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, ...
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Output Disable Mode When the OE# input are placed in the high impedance state. Table 2. Sector Address Tables (Top Boot Device) Sector A19 A18 A17 A16 SA0 SA1 ...
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Table 3. Sector Address Tables (Bottom Boot Device) Sector A19 A18 A17 A16 SA0 SA1 SA2 SA3 SA4 SA5 0 ...
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... The alternate method intended only for programming equipment requires V address pin A9 and OE#. This method is compatible with programmer routines written for earlier 3.0 volt-only Spansion flash devices. Details on this method are provided in a supplement, publication number 21468. Contact a Spansion repre- sentative to request a copy. ...
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Notes: 1. All protected sectors unprotected. 2. All previously protected sectors are protected once again. Figure 1. Temporary Sector Unprotect Operation START RESET (Note 1) ...
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START PLSCNT = 1 RESET Wait 1 µs No First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address with ...
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... CFI data at the addresses given in command to return the device to the autoselect mode. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.amd.com/products/nvd/ overview/cfi.html. Alternatively, contact a Spansion representative for copies of these documents. Addresses Addresses ...
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Addresses Addresses (Word Mode) (Byte Mode) 1Bh 36h 1Ch 38h 1Dh 3Ah 1Eh 3Ch 1Fh 3Eh 20h 40h 21h 42h 22h 44h 23h 46h 24h 48h 25h 4Ah 26h 4Ch Addresses Addresses (Word Mode) (Byte Mode) 27h 4Eh 28h 50h ...
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Table 8. Primary Vendor-Specific Extended Query Addresses Addresses (Word Mode) (Byte Mode) 40h 80h 41h 82h 42h 84h 43h 86h 44h 88h 45h 8Ah 46h 8Ch 47h 8Eh 48h 90h 49h 92h 4Ah 94h 4Bh 96h 4Ch 98h Hardware Data ...
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Logical Inhibit Write cycles are inhibited by holding any one of OE initiate a write cycle, CE# and WE# must be a logical zero while OE logical one. Power-Up Write Inhibit If ...
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Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses ...
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Autoselect Command Sequence The autoselect command sequence allows the host system to access the manu- facturer and devices codes, and determine whether or not a sector is protected. Table 9 shows the address and data requirements. This method is an ...
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Unlock Bypass Command Sequence The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. ...
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Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is ini- tiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the ...
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Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. Note that a hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence should be ...
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The system must write the Erase Resume command (address bits are “don’t care”) to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written ...
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Command Definitions Table 9. S29AL016D Command Definitions Command Sequence (Note 1) Read (Note 6) 1 Reset (Note 7) 1 Word Manufacturer ID 4 Byte Word Device ID, 4 Top Boot Block Byte Word Device ID, 4 Bottom Boot Block Byte ...
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Write Operation Status The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for determining whether ...
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Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be ...
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RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin that indicates whether an Em- bedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. ...
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DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II ...
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Notes: 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. See text. December 17, 2004 S29AL016D_00_A2 ...
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DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified inter- nal pulse count limit. Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the program or erase cycle ...
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Absolute Maximum Ratings Storage Temperature Plastic Packages .–65°C to ...
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Operating Ranges Industrial (I) Devices Ambient Temperature (T V Supply Voltages CC V for standard voltage range . . . . . . . . . . . . . . . . . . . . . . . ...
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DC Characteristics CMOS Compatible Parameter Description I Input Load Current Input Load Current LIT I Output Leakage Current LO V Active Read Current CC I CC1 (Notes Active Write Current CC I CC2 (Notes ...
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DC Characteristics (continued) Zero Power Flash 500 Note: Addresses are switching at 1 MHz Figure 9. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 ...
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Test Conditions Output Load Output Load Capacitance, C (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels December 17, 2004 S29AL016D_00_A2 ...
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Key to Switching Waveforms WAVEFORM Don’t Care, Any Change Permitted V CC 0.5 V Input CC 0.0 V Figure 12. Input Waveforms and Measurement Levels INPUTS Steady Changing ...
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AC Characteristics Read Operations Parameter JEDEC Std Description t t Read Cycle Time AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV Output Enable to Output Delay GLQV ...
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AC Characteristics Hardware Reset (RESET#) Parameter JEDEC Std Description RESET# Pin Low (During Embedded Algorithms) t READY to Read or Write (See Note) RESET# Pin Low (NOT During Embedded t READY Algorithms) to Read or Write (See Note) t RESET# ...
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AC Characteristics Word/Byte Configuration (BYTE#) Parameter JEDEC Std Description t t CE# to BYTE# Switching Low or High ELFL/ ELFH t BYTE# Switching Low to Output HIGH Z FLQZ t BYTE# Switching High to Output Active FHQV CE# OE# BYTE# ...
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AC Characteristics CE# WE# BYTE# Note: Refer to the Erase/Program Operations table for t Figure 16. BYTE# Timings for Write Operations The falling edge of the last WE# ...
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AC Characteristics Erase/Program Operations Parameter JEDEC Std Description t t Write Cycle Time AVAV Address Setup Time AVWL Address Hold Time WLAX Data Setup Time DVWH Data Hold ...
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AC Characteristics Program Command Sequence (last two cycles Addresses 555h CE# OE# WE Data RY/BY# t VCS V CC Notes program address program data Illustration shows device in word ...
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AC Characteristics Erase Command Sequence (last two cycles Addresses 2AAh CE Data RY/BY# t VCS V CC Notes sector address (for Sector Erase Valid Address ...
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AC Characteristics t Addresses VA t ACC OE# t OEH WE# DQ7 DQ0–DQ6 t BUSY RY/BY# Note Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and ...
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AC Characteristics Enter Erase Embedded Suspend Erasing Erase Erase Suspend WE# DQ6 DQ2 Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector. Figure 21. ...
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AC Characteristics RESET# SA, A6, A1, A0 Sector Protect/Unprotect Data 60h 1 µs CE# WE# OE# Note: For sector protect For sector unprotect ...
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AC Characteristics Alternate CE# Controlled Erase/Program Operations Parameter JEDEC Std Description t t Write Cycle Time AVAV Address Setup Time AVEL Address Hold Time ELAX Data Setup Time DVEH DS t ...
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AC Characteristics 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes program address program data, DQ7# = complement of the data written ...
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Erase and Programming Performance Parameter Sector Erase Time Chip Erase Time Byte Programming Time Word Programming Time Byte Mode Chip Programming Time (Note 3) Word Mode Notes: 1. Typical program and erase times assume the following conditions: 25 data pattern. ...
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Physical Dimensions TS 048—48-Pin Standard TSOP S29AL016D S29AL016D_00_A2 December 17, 2004 ...
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STANDARD PIN OUT (TOP VIEW SEE DETAIL 0. (N/2 TIPS) B SEE DETAIL A θ° PARALLEL TO SEATING PLANE DETAIL A NOTES: CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm). ...
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Physical Dimensions VBK048—48-Ball Fine-Pitch Ball Grid Array (FBGA INDEX MARK PIN A1 CORNER 10 TOP VIEW A SEATING PLANE A1 SIDE VIEW PACKAGE VBK 048 JEDEC N/A 8. 6.15 mm NOM PACKAGE ...
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SO044—44-Pin Small Outline Package (SOP) 28. 13.30 mm December 17, 2004 S29AL016D_00_A2 S29AL016D Dwg rev AC; 10/99 57 ...
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... Spansion LLC assumes no liability for any damages of any kind arising out of the use of the information in this document. ...