AM49LV128BMH15NT SPANSION, AM49LV128BMH15NT Datasheet
AM49LV128BMH15NT
Related parts for AM49LV128BMH15NT
AM49LV128BMH15NT Summary of contents
Page 1
... Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary ...
Page 2
THIS PAGE LEFT INTENTIONALLY BLANK. ...
Page 3
SUPPLEMENT Am49LV128BM Stacked Multi-Chip Package (MCP) 128 Megabit ( 16-Bit) MirrorBit™ Uniform Sector Flash Memory and 32 Mbit ( 16-Bit) pseudo-static RAM with Page Mode DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES Single power supply operation — 3 volt ...
Page 4
GENERAL DESCRIPTION The 128 Mbit MirrorBit device is a 128 Mbit, 3.0 volt single power supply flash memory devices organized as 8,388,608 words. The device has a 16-bit wide data bus. The device can be programmed either in the host ...
Page 5
TABLE OF CONTENTS Continuity of Specifications . . . . . . . . . . . 3 Continuity of Ordering Part Numbers . . . . . 3 For More Information . . . . . . . . ...
Page 6
Read TIming #1 (Basic Timing Read Timing #2 (OE# and Address Access Read Timing #3 (LB#/UB# Byte Access Read Timing #4 ...
Page 7
PRODUCT SELECTOR GUIDE Part Number Speed/ Full Voltage Range Voltage Option V CC Max. Access Time (ns) Max. CE# Access Time (ns) Max. Page access time (t ) PACC Max. OE# Access Time (ns) Notes: 1. See “AC Characteristics” for ...
Page 8
CONNECTION DIAGRAMS CE#f J2 CE#1ps M1 NC Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (TSOP and BGA). The package 6 64-Ball ...
Page 9
LOOK AHEAD PINOUT VSSds CLK ADV WP A18 ...
Page 10
PIN DESCRIPTION A22–A21 = 2 Address inputs (Flash) A20– Address inputs (Flash and pSRAM) DQ14–DQ0 = 15 Data inputs/outputs DQ15 = DQ15 (Data input/output) CE#f = Chip Enable input (Flash) CE1#ps, CE2ps=Chip Enable (pSRAM) OE# = Output Enable ...
Page 11
ORDERING INFORMATION The order number (Valid Combination) is formed by the following: Am49LV128 AMD DEVICE NUMBER/DESCRIPTION Am49LV128BM Stacked Multi-Chip Package (MCP) Flash Memory and pSRAM Am29LV128M 128 Megabit ( 16-Bit) Flash Memory and 32 ...
Page 12
DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch ...
Page 13
Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read oper- ation. This mode provides faster read access speed for random locations within a page. The page size ...
Page 14
RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of re- setting the device to reading array data. When the RE- SET# pin is driven low for at least a period of t device immediately terminates any operation ...
Page 15
Table 2. Sector Address Table (Continued) Sector SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 ...
Page 16
Table 2. Sector Address Table (Continued) Sector SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 ...
Page 17
Table 2. Sector Address Table (Continued) Sector SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 ...
Page 18
Table 2. Sector Address Table (Continued) Sector SA173 SA174 SA175 SA176 SA177 SA178 SA179 SA180 SA181 ...
Page 19
Table 2. Sector Address Table (Continued) Sector SA221 SA222 SA223 SA224 SA225 SA226 SA227 SA228 SA229 ...
Page 20
SecSi Sector is enabled. The SecSi sector address space in this device is allo- cated as follows: Table 3. SecSi Sector Contents SecSi Sector Customer ESN Factory Address Range Lockable ...
Page 21
Sector Group Protection and Unprotection The hardware sector group protection feature disables both program and erase operations in any sector group. The hardware sector group unprotection fea- ture re-enables both program and erase operations in previously protected sector groups. Sector ...
Page 22
Write Protect (WP#) The Write Protect function provides a hardware method of protecting the last sector without using V Write Protect is one of two functions provided by the WP#/ACC input. If the system asserts V on the WP#/ACC pin, ...
Page 23
START PLSCNT = 1 RESET Wait 1 µs No First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address with ...
Page 24
Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 9 for com- mand definitions). In addition, the following hardware data protection measures prevent accidental erasure or ...
Page 25
Addresses (x16) Data 1Bh 0027h 1Ch 0036h 1Dh 0000h 1Eh 0000h 1Fh 0007h 20h 0007h 21h 000Ah 22h 0000h 23h 0001h 24h 0005h 25h 0004h 26h 0000h Addresses (x16) Data 27h 0018h 28h 0002h 29h 0000h 2Ah 0005h 2Bh 0000h ...
Page 26
Table 8. Primary Vendor-Specific Extended Query Addresses (x16) Data 40h 0050h 41h 0052h 42h 0049h 43h 0031h 44h 0033h 45h 0008h 46h 0002h 47h 0001h 48h 0001h 49h 0004h 4Ah 0000h 4Bh 0000h 4Ch 0001h 4Dh 00B5h 4Eh 00C5h 0004h/ ...
Page 27
After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same excep- tion. See the Erase Suspend/Erase Resume Com- mands section for more information. The system must issue ...
Page 28
When the Embedded Program algorithm is complete, the device then returns to the read mode and ad- dresses are no longer latched. The system can deter- mine the status of the program operation by using DQ7 or DQ6. Refer to ...
Page 29
Load a value that is greater than the page buffer size during the Number of Locations to Program step. Write to an address in a sector different than the one specified during the Write-Buffer-Load com- mand. Write an Address/Data pair ...
Page 30
Write “Write to Buffer” command and Sector Address Write number of addresses to program minus 1(WC) and Sector Address Write first address/data Yes Abort Write to Buffer Operation? (Note 1) Write next address/data pair WC = ...
Page 31
Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Increment Address Last Address? Programming Completed Note: See Tables 9 and 10 for program command sequence. Figure 4. Program Operation Program Suspend/Program Resume Command ...
Page 32
Figure 5. Program Suspend/Program Resume Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are ...
Page 33
START Write Erase Command Sequence (Notes 1, 2) Data Poll to Erasing Bank from System No Data = FFh? Yes Erasure Completed Figure 6. Erase Operation Notes: 1. See Tables 9 for erase command sequence. 2. See the section on ...
Page 34
Command Definitions Command Sequence (Note 1) Addr Read (Note 6) 1 Reset (Note 7) 1 Manufacturer ID 4 Device ID (Note 9) 4 SecSi™ Sector Factory Protect 4 (Note 10) Sector Group Protect Verify 4 (Note 12) Enter SecSi Sector ...
Page 35
WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 10 and the following subsections describe the function of these bits. DQ7 and DQ6 each ...
Page 36
Suspend mode. Toggle Bit I may be read at any ad- dress, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase ...
Page 37
Reading Toggle Bits DQ6/DQ2 Refer to Figure 9 for the following discussion. When- ever the system initially begins reading toggle bit sta- tus, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is ...
Page 38
Status Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Program-Suspended Program Program- Sector Suspend Suspend Non-Program Mode Read Suspended Sector Erase-Suspended Erase- Sector Suspend Erase Non-Erase Suspended Read Suspend Sector Mode Erase-Suspend-Program (Embedded Program) Busy (Note 3) Write-to- Buffer Abort ...
Page 39
ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . ...
Page 40
FLASH DC CHARACTERISTICS CMOS Compatible Parameter Parameter Description Symbol (Notes) I Input Load Current ( ACC Input Load Current LIT I Reset Leakage Current LR I Output Leakage Current LO V Active Read Current CC I CC1 (2, ...
Page 41
TEST CONDITIONS Device Under Test C L 6.2 kΩ Note: Diodes are IN3064 or equivalent Figure 11. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM Don’t Care, Any Change Permitted 3.0 V 1.5 V Input 0.0 V Note < ...
Page 42
AC CHARACTERISTICS V Power-up CC Parameter Description t V Setup Time VCS CC t RESET# Low Hold Time RSTH V CC RESET# 40 Test Setup Min Min t VCS t RSTH Figure 13. V Power-up Diagram CC Am49LV128BM Speed Unit ...
Page 43
AC CHARACTERISTICS Flash Read-Only Operations Parameter JEDEC Std. Description t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV CE t Page Access Time PACC ...
Page 44
AC CHARACTERISTICS A22-A2 A1-A0 Data Bus CE# OE# 42 Same Page PACC PACC t ACC Qa Qb Figure 15. Page Read Timings Am49LV128BM PACC Qc Qd June 17, 2004 ...
Page 45
AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std. RESET# Pin Low (During Embedded Algorithms) t Ready to Read Mode (See Note) RESET# Pin Low (NOT During Embedded t Ready Algorithms) to Read Mode (See Note) t RESET# Pulse Width RP ...
Page 46
AC CHARACTERISTICS Erase and Program Operations Parameter JEDEC Std. Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL AS Address Setup Time to OE# low during toggle bit t ASO polling t t ...
Page 47
AC CHARACTERISTICS Program Command Sequence (last two cycles Addresses 555h CE Data VCS Notes program address program data Illustration shows device ...
Page 48
AC CHARACTERISTICS Erase Command Sequence (last two cycles Addresses 2AAh CE Data t VCS V CC Notes sector address (for Sector Erase Valid Address for ...
Page 49
AC CHARACTERISTICS t RC Addresses VA t ACC OE# t OEH WE# DQ7 DQ0–DQ6 Note Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array ...
Page 50
AC CHARACTERISTICS Addresses CE# t OEH WE# OE Valid Data DQ6/DQ2 (first read) Note Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data ...
Page 51
AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std Description t V Rise and Fall Time (See Note) VIDR ID RESET# Setup Time for Temporary Sector t RSP Unprotect Note: Not 100% tested RESET ...
Page 52
AC CHARACTERISTICS RESET# SA, A6, A1, A0 Sector Group Protect or Unprotect Data 60h 1 µs CE# WE# OE# * For sector group protect For sector group ...
Page 53
AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations Parameter JEDEC Std. Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Hold Time ELAX Data Setup ...
Page 54
AC CHARACTERISTICS 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# Notes: 1. Figure indicates last two bus cycles of a program or erase operation program ...
Page 55
ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Effective Write Buffer Program Per Word Time (Note 3) Program Time Word Effective Accelerated Word Program Time (Note 3) Accelerated Program Time Word Chip Program Time (Note 4) Notes: ...
Page 56
AM49LV128BM MCP WITH STANDARD SUPPLIER PSRAM BLOCK DIAGRAM A20 ADDRESS LATCH & to BUFFER A0 DQ16 to INPUT / DQ9 OUTPUT DQ8 BUFFER to DQ1 POWER CE2 CONTROL CE1 MEMORY ROW ...
Page 57
FUNCTION TRUTH TABLE Mode CE2 Standby (Deselect) Output Disable (Note 1) Output Disable (No Read) Read (Upper Byte) Read (Lower Byte) Read (Word) No Write Write (Upper Byte) Write (Lower Byte) Write (Word) Power Down (Note 2) Note: 1. Should ...
Page 58
POWER DOWN Power Down The Power Down is to enter low power idle state when CE2 stays Low. The pSRAM has two power down modes, Deep Sleep and 8M Partial. These can be pro- grammed by series of read/write operation. ...
Page 59
RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage High Level Input Voltage Low Level Input Voltage Ambient Temperature Notes: 1. Maximum DC voltage on input and I/O pins are ns. 2. Minimum DC voltage on input or I/O pins ...
Page 60
PSRAM DC CHARACTERISTICS Parameter Symbol Input Leakage I LI Current Output Leakage I LO Current Output High V OH Voltage Level Output Low V OL Voltage Level I DDPS V Power Down DD Current I DDP8 I DDS V Standby ...
Page 61
PSRAM AC CHARACTERISTICS Read Operation Parameter Read Cycle Time (Notes 1, 2) CE1# Access Time (Note 3) OE# Access Time (Note 3) Address Access Time (Notes 3,5) LB#/UB# Access Time (Note 3) Page Address Access Time (Notes 3,6) Page Read ...
Page 62
PSRAM AC CHARACTERISTICS Write Operation Parameter Write Cycle Time (Notes 1, 2) Address Setup Time (Note 3) CE1# Write Pulse Width (Note 3) WE# Write Pulse Width (Note 3) LB#/UB# Write Pulse Width (Note 3) LB#/UB# Byte Mask Setup Time ...
Page 63
AC CHARACTERISTICS Power Down Parameters Parameter CE2 Low Setup Time for Power Down Entry CE2 Low Hold Time after Power Down Entry CE1# High Hold Time following CE2 High after Power Down Exit (SLEEP mode only) (Note 1) CE1# High ...
Page 64
AC CHARACTERISTICS AC Test Conditions Symbol Description V Input High Level IH V Input Low Level IL V Input Timing Measurement Level REF t Input Transition Time 0 Figure 26. AC Measurement Output Load ...
Page 65
TIMING DIAGRAMS ADDRESS t ASC CE1# OE UB# DQ (Output) Note: CE2 and WE# must be High for entire read cycle. Figure 27. Read TIming #1 (Basic Timing) June 17, 2004 t RC ADDRESS VALID ...
Page 66
ADDRESS ADDRESS VALID CE1# Low t ASO OE UB# DQ (Output) Note: CE2 and WE# must be High for entire read cycle. Figure 28. Read Timing #2 (OE# and Address Access ...
Page 67
TIMING DIAGRAMS t AX ADDRESS t AA CE1#,OE# Low LB# UB# DQ0-DQ7 (Output) DQ8-DQ15 (Output) Note: CE2 and WE# must be High for entire read cycle. Figure 29. Read Timing #3 (LB#/UB# Byte Access) ADDRESS (A20-A3) ADDRESS ADDRESS VALID (A2-A0) ...
Page 68
TIMING DIAGRAMS ADDRESS ADDRESS VALID (A20-A3 ADDRESS ADDRESS VALID (A2-A0 CE1# Low t t ASO OE OE LB# / UB# t OLZ t BLZ DQ (Output) Note: CE2 and WE# must be High for ...
Page 69
TIMING DIAGRAMS ADDRESS t AS CE1 WE UB# t OHCL OE# DQ (Input) Note: CE2 must be High for Write Cycle. Figure 32. Write Timing #1 (Basic Timing) ADDRESS t OHAH CE1# Low t AS WE# ...
Page 70
TIMING DIAGRAMS ADDRESS CE1# Low WE LB UB# DQ0-DQ8 (Input) DQ8-DQ15 (Input) Note: CE2 must be High for Write Cycle. Figure 34. Write Timing #3-1 (WE#/LB#/UB# Byte Write Control ADDRESS VALID t WR ...
Page 71
ADDRESS CE1# Low WE LB UB# DQ0-DQ7 (Input) DQ8-DQ15 (Input) Note: CE2 must be High for Write Cycle. Figure 35. Write Timing #3-2 (WE#/LB#/UB# Byte Write Control) June 17, 2004 t WC ADDRESS VALID t WR ...
Page 72
TIMING DIAGRAMS ADDRESS CE1# Low WE LB UB# DQ0-DQ7 (Input) DQ8-DQ15 (Input) Note: CE2 must be High for Write Cycle. Figure 36. Write Timing #3-3 (WE#/LB#/UB# Byte Write Control) ADDRESS CE1# Low WE LB# ...
Page 73
TIMING DIAGRAMS ADDRESS t CHAH t AS CE1 WE# UB#,LB# t OHCL OE# t CHZ READ DATA OUTPUT Note: Write address is valid from either CE1# or WE# of last falling edge. Figure 38. Read/Write ...
Page 74
TIMING DIAGRAMS ADDRESS t OHAH CE1# Low t AS WE# t OES UB#,LB# OE# t OHZ READ DATA OUTPUT Note: CE1# can be tied to Low for WE# and OE# controlled operation. Figure 40. Read/Write Timing #2 ...
Page 75
TIMING DIAGRAMS CE1# CE2 Note: The t specifies after V reaches specified minimum level. C2LH DD CE1# CE2 Note: The t specifies after V reaches specified minimum level and applicable to both CE1# ...
Page 76
TIMING DIAGRAMS CE1# CE2 t CSP DQ Power Down Entry Note: This Power Down mode can be also used as a reset timing if Power-up timing above could not be satisfied and Power- Down program was not performed prior to ...
Page 77
TIMING DIAGRAMS MSB* MSB* ADDRESS t CP CE1# OE# WE# LB#,UB# 3 RDa DQ* Cycle #1 Cycle #2 Notes: 1. The all address inputs must be High from Cycle #1 to #5. 2. After t following Cycle ...
Page 78
AM49LV128BM MCP WITH SECOND PSRAM SUPPLIER PSRAM BLOCK DIAGRAM Note: ZZ# = CE2pS on MCP pin-out. FUNCTION TRUTH TABLE Mode CE# ZZ# Standby (Note 2) H Standby (Note 2) X Write L Read L Active L Deep Sleep X Note: ...
Page 79
OPERATING CHARACTERISTICS (OVER SPECIFIED TEMPERATURE RANGE) Item Supply Voltage Supply Voltage for I/O Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Read/Write Operating Supply Current @1 µs Cycle Time (Note ...
Page 80
OUTPUT LOAD CIRCUIT 78 Am49LV128BM June 17, 2004 ...
Page 81
TIMING Item Read Cycle Time Address Access Time Page Mode Read Cycle Time Page Mode Access Time Chip Enable to Valid Output Output Enable to Valid Output Byte Select to Valid Output Chip Enable to Low-Z Output Output Enable to ...
Page 82
TIMING OF READ CYCLE (CE Am49LV128BM June 17, 2004 ...
Page 83
TIMING WAVEFORM OF READ CYCLE (WE#=V Address CE# OE# LB#,UB# Data Out June 17, 2004 ) IH Am49LV128BM 81 ...
Page 84
TIMING WAVEFORM OF PAGE MODE READ CYCLE (WE Am49LV128BM June 17, 2004 ...
Page 85
TIMING WAVEFORM OF WRITE CYCLE (WE# CONTROL) June 17, 2004 Am49LV128BM 83 ...
Page 86
TIMING WAVEFORM OF WRITE CYCLE (CE# CONTROL) 84 Am49LV128BM June 17, 2004 ...
Page 87
TIMING WAVEFORM FOR SUCCESSIVE WE# WRITE CYCLES June 17, 2004 Am49LV128BM 85 ...
Page 88
TIMING WAVEFORM OF PAGE MODE WRITE CYCLE POWER SAVINGS MODES The PSRAM has three power savings modes: Reduced Memory Size Partial Array Refresh Deep Sleep Mode The operation of the power saving modes is controlled by setting the Variable Address ...
Page 89
This device is referred to as Deep Sleep Inactive, or DSI device. In either device, once the SRAM enters Deep Sleep Mode, the VAR contents are destroyed and the default register set- tings are reset. June ...
Page 90
VARIABLE ADDRESS REGISTER 88 Am49LV128BM June 17, 2004 ...
Page 91
VARIABLE ADDRESS REGISTER (VAR) UPDATE TIMINGS June 17, 2004 Am49LV128BM 89 ...
Page 92
DEEP SLEEP MODE - ENTRY/EXIT TIMINGS VAR UPDATE AND DEEP SLEEP TIMINGS Item PAR and RMS ZZ# low to WE# low Chip (CE#, UB#/LB#) deselect to ZZ# low Deep Sleep Mode Deep Sleep Recovery 90 Symbol Min Max Unit t ...
Page 93
ADDRESS PATTERNS FOR PAR ( Active Section One-quarter of die 000000h - 07FFFFh 512Kb One-half of die Full Die 1 1 ...
Page 94
ADDRESS PATTERNS FOR RMS ( Active Section One-quarter of die One-half of die Full die One-quarter of die 1 1 ...
Page 95
LOW POWER ICC CHARACTERISTICS FOR PSRAM Item Symbol PAR Mode Standby I PAR Current RMS Mode Standby I RMSSB Current Deep Sleep Current I ZZ June 17, 2004 Test Array Partition 1/4 Array 0V ...
Page 96
PHYSICAL DIMENSIONS TLD064–64-Ball Fine-pitch Ball Grid Array D 0.15 C (2X) INDEX MARK PIN A1 CORNER 10 TOP VIEW SIDE VIEW 6 b 64X 0. 0. PACKAGE TLD 064 JEDEC N/A ...
Page 97
REVISION SUMMARY Revision A (January 22, 2004) Initial release. Revision A+1 (January 29, 2004) Connection Diagrams Corrected signal designation on ball H8. AC Characteristics (Flash) Read-only Operations: Added Figure 14. pSRAM AC Characteristics Figure 32, Write Timing #1 (Basic Timing): ...
Page 98
Deleted “Full Die” from table. “Address Patterns for PAR ( 1)” on page 91 Added “Full Die” to table. “Timing” on page 79 Changed “Chip Disable to High-Z Output - Max” Changed “Output Disable ...