FDC37N869TQFP SMSC Corporation, FDC37N869TQFP Datasheet
FDC37N869TQFP
Related parts for FDC37N869TQFP
FDC37N869TQFP Summary of contents
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... Incorporates ChiProtect Circuitry for Protection Against Damage Due to Printer Power-On - 192 Base I/O Address, 15 IRQ and 4 DMA Options § Game Port Select Logic - 48 Base I/O Addresses § General Purpose Address Decoder - 16-Byte Block Decode ORDERING INFORMATION Order Number: FDC37N869TQFP 100 Pin TQFP Package FDC37N869 11/09/2000 ...
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STANDARD MICROSYSTEMS CORPORATION (SMSC) 80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123 Standard Microsystems is a registered trademark of Standard Microsystems Corporation, and SMSC, ChiProtect, SuperCell and Multi-Mode are trademarks of Standard Microsystems Corporation. Product ...
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The SMSC FDC37N869 is a 5v/3.3v PC 99-compliant Super I/O Controller with Infrared support. The FDC37N869 utilizes SMSC’s proven SuperCell technology and is optimized for motherboard applications. The FDC37N869 incorporates SMSC’s true CMOS 765B floppy disk controller, advanced digital data ...
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GENERAL DESCRIPTION ...................................................................................................................3 PIN CONFIGURATION ........................................................................................................................8 PIN DESCRIPTION .............................................................................................................................9 BUFFER TYPE PER PIN.................................................................................................................. .................................................................................................................... 15 UFFER YPE UMMARY O D .............................................................................................................................. 15 UTPUT RIVERS FUNCTIONAL DESCRIPTION............................................................................................................ ............................................................................................................. 17 OST ROCESSOR NTERFACE FLOPPY DISK ...
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Configure.................................................................................................................................. 54 Version ..................................................................................................................................... 55 Relative Seek ............................................................................................................................. 55 Perpendicular Mode.................................................................................................................. 56 LOCK........................................................................................................................................ 57 ENHANCED DUMPREG ............................................................................................................. 57 COMPATIBILITY ............................................................................................................................ ARALLEL ORT LOPPY ISK ONTROLLER SERIAL PORT (UART) ...................................................................................................................... ...................................................................................................................... 59 ...
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Description ............................................................................................................................... 82 Register Definitions................................................................................................................... 83 OPERATION.............................................................................................................................. 89 AUTO POWER MANAGEMENT ......................................................................................................... 93 FDC P M ............................................................................................................... 93 OWER ANAGEMENT DSR From Powerdown.............................................................................................................. 93 Wake Up From Auto Powerdown .............................................................................................. 93 Register Behavior...................................................................................................................... 94 Pin Behavior ............................................................................................................................. 94 UART P ...
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CR17....................................................................................................................................... 113 CR18 - CR1D ........................................................................................................................... 114 CR1E ...................................................................................................................................... 114 CR1F....................................................................................................................................... 114 CR20....................................................................................................................................... 115 CR21....................................................................................................................................... 115 CR23....................................................................................................................................... 115 CR24....................................................................................................................................... 116 CR25....................................................................................................................................... 116 CR26....................................................................................................................................... 116 CR27....................................................................................................................................... 117 CR28....................................................................................................................................... 117 CR29....................................................................................................................................... 118 CR2A ...................................................................................................................................... 118 CR2B ...................................................................................................................................... 118 CR2C ...................................................................................................................................... 118 CR2D ...
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RXD1 76 TXD1 77 nDSR1 78 nRTS1 79 nCTS1 80 nDTR1 81 nRI1 82 nDCD1 83 nRI2 84 nDCD2 85 RXD2 86 TXD2 87 nDSR2 88 nRTS2 89 nCTS2 90 nDTR2 91 nADRX/nCLKRUN 92 VSS 93 nDACK_C 94 A10 95 ...
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TQFP PIN # NAME SYMBOL 46-49 Data Bus 0- D0-D7 51- nI/O Read nIOR 43 nI/O Write nIOW 44 Address AEN Enable 26-32 Address A0-A15 39-41, Bus 95,35, 36,1, 3,25 19,50, DMA DRQ_A 97,17 Request DRQ_B A, B, ...
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TQFP PIN # NAME SYMBOL 8 nWrite nWGATE Gate 7 nWrite nWDATA Data 9 nHead nHDSEL Select 5 Direction nDIR Control 6 nStep Pulse nSTEP 15 Disk nDSKCHG Change 2 nDrive nDS0 Select 0 100 nMotor On 0 nMTR0 99 ...
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TQFP PIN # NAME SYMBOL 77 Transmit TXD1 Data 1 79,89 nRequest to nRTS1 Send nRTS2 (System (SYSOPT) Option) 81,91 nData nDTR1 Terminal Ready nDTR2 80,90 nClear to nCTS1 Send nCTS2 78,88 nData Set nDSR1 Ready nDSR2 83,85 nData nDCD1 ...
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TQFP PIN # NAME SYMBOL 82,84 nRing nRI1 Indicator nRI2 TQFP PIN # NAME SYMBOL 71 nPrinter nSLCT Select Input/FDC nStep Pulse 3 (Note ) nSTEP 72 nInitiate nINIT Output/ FDC nDirection Control 3 (Note ) nDIR 74 nAutofeed nAUTOFD ...
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TQFP PIN # NAME SYMBOL 60 nAcknowl- nACK edge/FDC nDrive Select 1 nDS1 58 Paper End/ PE FDC nWrite Data nWRDATA 57 Printer SLCT Selected Status/ FDC nWrite Gate nWGATE 73 nError/FDC nERROR nHead Select nHDSEL 69 Port Data PD0 ...
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TQFP PIN # NAME SYMBOL 18 14.318 MHz CLK14 Input Clock 23 IR Receive 2 IRRX2 24 IR Transmit 2 IRTX2 5 (Note ) 92 Address X/ nADRX/ PCI Clock nCLKRU Controller Mode/ IR IRMODE/ Receive 3 ...
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Buffer Type Summary Table 2 below describes the buffer types shown in Table 1. All values are specified at V Table 2 - FDC37N869 Buffer Type Summary (See Note) BUFFER TYPE IO12 Input/Output. 12mA sink; 6mA source O12 Output. 12mA ...
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Vcc (2) nCS nIOR nIOW AEN A0-A15 D0-D7 HOST CPU DRQ_A-D INTERFACE nDACK_A-D TC SIRQ CLK33 nADRX/nCLKRUN RESET IRQIN IOCHRDY 14.318 CLOCK SMSC DS – FDC37N869 PWRGD/nGAMECS Vss (4) POWER MANAGEMENT DATA BUS ADDRESS BUS CONFIGURATION REGISTERS CONTROL BUS WDATA ...
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Super I/O Registers Table 3 shows the addresses of the various device blocks of the Super I/O immediately after power up. The base addresses must be set in the configuration registers before accessing these devices. The base addresses of the ...
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Interface Modes The Interface modes are determined by the MFM and IDENT configuration bits in Configuration Register 3 (see section CR03 on page 106). PC/AT Interface Mode When both IDENT and MFM are high the PC/AT register set is enabled, ...
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PS/2 Interface Mode 7 INT PENDING RESET 0 CONDITION Direction, Bit 0 Active high status indicating the direction of head movement. A logic “1” indicating inward direction, a logic “0” outward. nWRITE PROTECT, Bit 1 Active low status of the ...
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PS/2 Model 30 Interface Mode 7 INT PENDING RESET 0 CONDITION nDIRECTION, Bit 0 Active low status indicating the direction of head movement. A logic “0” indicating inward direction a logic “1” outward. Write Protect, Bit 1 Active high status ...
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STATUS REGISTER B (SRB) Status Register B (Base Address + 1) is read-only and monitors the state of several disk interface pins in PS/2 interface mode (Table 7) and Model 30 interface mode (Table 8). SRB can be accessed at ...
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PS/2 Model 30 Interface Mode 7 6 nDRV2 nDS1 RESET N/A 1 CONDITION nDRIVE SELECT 2, Bit 0 Active low status of the DS2 disk interface output. nDRIVE SELECT 3, Bit 1 Active low status of the DS3 disk interface ...
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DIGITAL OUTPUT REGISTER (DOR) The Digital Output register (Base Address + 2) controls the drive select and motor enables of the disk interface outputs (Table 9 and Table 10). The DOR also contains the DMA logic enable and a software ...
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Table 11 - Internal 2 Drive Decode: Drives 0 and 1 DIGITAL OUTPUT REGISTER Bit 7 Bit 6 Bit 5 Bit 4 Bit1 ...
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Enhanced Floppy Mode 2 (OS2) The configuration of the TDR in the Enhanced Floppy Mode 2 (OS/2 mode) is shown in Table 14. DB7 DB6 TDR Reserved Reserved, Bits Bits 6 and 7 are RESERVED. Reserved bits ...
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Command Busy, Bit 4 This bit is set to a “1” when a command is in progress. This bit will go active after the command byte has been accepted and goes inactive at the end of the results phase. If ...
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Low Power, Bit 6 A logic “1” written to this bit will put the floppy controller into Manual Low Power mode. The floppy controller clock and data separator circuits will be turned off. The controller will come out of manual ...
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DRIVE RATE DATA RATE SELECT SELECT (CR0B) (DSR) DRT1 DRT0 SEL1 ...
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DATA REGISTER (FIFO) The Data Register (Base Address + 5) is used to transfer all command parameter information, disk data and result status between the host processor and the floppy disk controller. The Data Register is Read/Write. Data transfers are ...
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PS/2 Interface Mode 7 DSK CHG RESET N/A CONDITION nHIGH DENS, Bit 0 This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and 300 Kbps are selected. Data Rate ...
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DSK CHG, Bit 7 The DSK CHG bit monitors the pin of the same name and reflects the opposite value seen on the pin. The DSK CHG bit also depends upon the Force Disk Change bits in the Force FDD ...
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Status Register Encoding During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the command just executed. BIT NO. SYMBOL NAME 7,6 IC Interrupt Code 5 SE Seek End 4 EC Equipment ...
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BIT NO. SYMBOL NAME Control Mark 5 DD Data Error in Data Field 4 WC Wrong Cylinder Bad Cylinder 0 MD Missing Data Address Mark BIT NO. SYMBOL NAME Write ...
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RESET Pin (Hardware Reset) The RESET pin is a global reset and clears all registers except those programmed by the Specify command. The DOR reset bit is enabled and must be cleared by the host to exit the reset state. ...
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A high value of threshold (i.e. 12) is used with a “sluggish” system by affording a long latency period after a service request, but results in more frequent service requests. Non-DMA Mode ...
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RQM and DIO must both equal “1” before the result bytes may be read. After all the result bytes have been read, the RQM and DIO bits switch to “1” and “0” respectively, and the CB bit is cleared, indicating ...
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SYMBOL NAME Time LOCK MFM MFM/FM Mode Selector MT Multi-Track Selector N Sector Size Code NCN New Cylinder Number ND Non-DMA Mode Flag OW Overwrite PCN Present Cylinder Number POLL Polling Disable PRETRK Precompensatio n Start Track Number R Sector ...
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SYMBOL NAME SK Skip Flag SRT Step Rate Interval The time interval between step pulses issued by the FDC. ST0 Status 0 ST1 Status 1 ST2 Status 2 ST3 Status 3 WGATE Write Gate Instruction Set PHASE R/W D7 Command ...
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PHASE R/W D7 Command Execution Result PHASE R/W D7 Command Execution ...
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PHASE R/W D7 Command Execution Result PHASE R/W D7 Command Execution ...
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PHASE R PHASE R/W D7 Command Execution Result PHASE R/W D7 Command W 0 Result R 1 SMSC DS ...
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PHASE R/W D7 Command Execution for W Each Sector Repeat Result PHASE R/W D7 Command Execution SMSC DS ...
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PHASE R/W D7 Command W 0 Result R R DATA BUS PHASE R/W D7 Command SRT - - - HLT - - - - - - PHASE ...
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PHASE R/W D7 Command PHASE R/W D7 Command W 0 Execution Result LOCK SMSC DS – FDC37N869 RELATIVE SEEK DATA BUS ...
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PHASE R/W D7 Command Execution Result PHASE R/W D7 Command SMSC DS – FDC37N869 READ ID DATA BUS MFM 0 ...
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PHASE R/W D7 Command W Result R PHASE R/W D7 Command W LOCK Result returned if the last command that was issued was the Format command. EOT is returned if the last command was a Read or ...
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The amount of data which can be handled with a single command to the FDC depends upon MT (multi-track) and N (number of bytes/sector). The Multi-Track function (MT) allows the FDC to read data from both sides of the diskette. ...
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Read Deleted Data This command is the same as the Read Data command, only it operates on sectors that contain a Deleted Data Address Mark at the beginning of a Data Field. Table 37 describes the effect of the SK ...
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FINAL SECTOR TRANSFERRED TO MT HEAD Less than EOT 0 0 Equal to EOT Less than EOT 1 Equal to EOT Less than EOT 1 0 Equal to EOT Less than EOT 1 Equal to EOT NC: No Change, the ...
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Write Deleted Data This command is almost the same as the Write Data command except that a Deleted Data Address Mark is written at the beginning of the Data Field instead of the normal Data Address Mark. This command is ...
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Format A Track The Format command allows an entire track to be formatted. After a pulse from the IDX pin is detected, the FDC starts writing data on the disk including gaps, address marks, ID fields, and data fields per ...
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FORMAT FM 5.25” Drives MFM 3.5” FM Drives MFM GPL1 = suggested GPL values in Read and Write commands to avoid splice point between data field and ID field of contiguous sections. GPL2 = suggested GPL value in Format A ...
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During the command phase of the recalibrate operation, the FDC is in the BUSY state, but during the execution phase NON-BUSY state. At this time, another Recalibrate command may be issued, and in ...
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The Seek, Relative Seek, and Recalibrate commands have no result phase. The Sense Interrupt Status command must be issued immediately after these commands to terminate them and to provide verification of the head position (PCN). The H (Head Address) bit ...
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POLL - Disable polling of the drives. Defaults to “0”, polling enabled. When enabled, a single interrupt is generated after a reset. No polling is performed while the drive head is loaded and the head unload delay has not expired. ...
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Perpendicular Mode The Perpendicular Mode command should be issued prior to executing Read/Write/Format commands that access a disk drive with perpendicular recording capability. With this command, the length of the Gap2 field and VCO enable timing can be altered to ...
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Software and hardware resets have the following effect on the PERPENDICULAR MODE COMMAND: 1. “Software” resets (via the DOR or DSR registers) will only clear GAP and WGATE bits to “0”. D0-D3 are unaffected and retain their previous value. 2. ...
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IRQ assigned to the parallel port: not active, this is hi-Z or Low depending on settings. The following parallel port pins are read as follows by a read of the parallel port register: 1. Data Register (read) = last ...
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Note : The Parallel Port Control register reads as “Cable Not Connected” when the PP FDC is enabled; i.e., STROBE = AUTOFD = SLC = 0 and nINIT = 1 SERIAL PORT (UART) The FDC37N869 incorporates two full function ...
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Serial Port interrupt out of the FDC37N869. All other system functions operate in their normal manner, including the Line Status and MODEM Status Registers. The contents of the Interrupt Enable Register are described below. ERDAI, Bit 0 The ...
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Reserved, Bits Bits are RESERVED. Reserved bits cannot be written and return 0 when read. FIFOs Enabled, Bits The FIFOs Enabled bits are set when the FIFO CONTROL Register bit 0 ...
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FIFO CONTROL REGISTER (FCR) The FIFO Control register (Address Offset = 2H, DLAB = X, WRITE) appears at the same location as the IIR. This register is used to enable and clear the FIFOs and set the RCVR FIFO trigger ...
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LINE CONTROL REGISTER (LCR) The Line Control register (Address Offset = 3H, DLAB = 0, READ/WRITE) contains the formatting information for the serial line. Word Length Select, Bits The Word Length Select bits specify the number of ...
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DLAB, Bit 7 The Divisor Latch Access Bit must be set high (logic “1”) to access the Divisor Latches of the Baud Rate Generator during read or write operations. It must be set low (logic “0”) to access the Receiver ...
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LINE STATUS REGISTER (LSR) Address Offset = 5H, DLAB = X, READ/WRITE Data Ready, Bit 0 Data Ready (DR) is set to a logic “1” whenever a complete received data character has been transferred into the Receiver Buffer Register or ...
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Transmitter Empty, Bit 6 The Transmitter Empty (TEMT) bit is set to a logic “1” whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty reset to logic “0” whenever either the THR or ...
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SCRATCHPAD REGISTER (SCR) The Scratchpad register (Address Offset =7H, DLAB =X, READ/WRITE) has no effect on the operation of the Serial Port intended as a scratchpad register to be used by the programmer to hold data temporarily. PROGRAMMABLE ...
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The Affects of RESET on the UART Registers The RESET Function (Table 54) details the affects of RESET on each of the Serial Port registers. REGISTER/SIGNAL Interrupt Enable Register Interrupt Identification Reg. FIFO Control Line Control Reg. MODEM Control Reg. ...
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When the XMIT FIFO and transmitter interrupts are enabled (FCR bit 0 = “1”, IER bit 1 = “1”), XMIT interrupts occur as follows: 1. The transmitter holding register interrupt (02H) occurs when the XMIT FIFO is empty ...
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REGISTER ADDRESS* REGISTER NAME ADDR = 1 Divisor Latch (MS) DLAB = 1 *DLAB is Bit 7 of the Line Control Register (ADDR = 3). Note 1: Bit 0 is the least significant bit the first bit serially ...
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TX AND RX FIFO OPERATION The Tx portion of the UART transmits data through TXD as soon as the CPU loads a byte into the Tx FIFO. The UART will prevent loads to the Tx FIFO if it currently holds ...
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A one is signaled by the absence of an infrared pulse during the bit time. Please refer to section AC TIMING for the parameters of these pulses and the IrDA waveforms. IrDA FIR (v1.2) ...
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IrCC Block RAW COM TV ASK OUT MUX IrDA FIR AUX COM G.P. Data Fast Bit FIGURE 3 - INFRARED INTERFACE BLOCK DIAGRAM SMSC DS – FDC37N869 TX1 0 RX1 1 1 TX2 1 RX2 TX3 RX3 ...
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PARALLEL PORT The FDC37N869 incorporates an IBM XT/AT compatible parallel port. The FDC37N869 supports the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the FDC37N869 ...
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HOST CONNECTOR PIN NUMBER 1 75 2-9 69-66, 64- (1) = Compatible Mode (3) = High Speed Mode Note: For the cable interconnection required ...
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BIT 4 SLCT - PRINTER SELECTED STATUS The level on the SLCT input is read by the CPU as bit 4 of the Printer Status Register. A logic “1” means the printer is on line; a logic “0” means it ...
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Bits 6 and 7 during a read are a low level, and cannot be written. EPP ADDRESS PORT ADDRESS OFFSET = 03H The EPP Address Port is located at an offset of ‘03H’ from the base address. The address register ...
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Software Constraints Before an EPP cycle is executed, the software must ensure that the control register bit PCD is a logic “0” (i.e. a 04H or 05H should be written to the Control port). If the user leaves PCD as ...
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A) The chip latches the data from the PData bus for the SData bus, deasserts DATASTB or nADDRSTRB, this marks the beginning of the termination phase. B) The chip drives the valid data onto the SData bus and asserts ...
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When the host deasserts nI0R the chip deasserts nDATASTB or nADDRSTRB. 8. Peripheral tri-states the PData bus. 9. Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle. EPP SIGNAL EPP NAME nWRITE nWrite PD<0:7> Address/Data ...
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EXTENDED CAPABILITIES PARALLEL PORT ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater detail in the remainder of this section. High performance half-duplex forward and reverse channel Interlocked handshake, for ...
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ISA IMPLEMENTATION STANDARD This specification describes the standard ISA interface to the Extended Capabilities Port (ECP). All ISA devices supporting ECP must meet the requirements contained in this section or the port will not be supported by Microsoft. For a ...
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NAME TYPE nINIT O Sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. The peripheral is only allowed to drive the bi-directional data bus while in ...
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DATA and ecpAFifo PORT ADDRESS OFFSET = 00H Modes 000 and 001 (Data Port) The Data Port is located at an offset of ‘00H’ from the base address. The data register is cleared at initialization by RESET. During a WRITE ...
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BIT 1 AUTOFD - AUTOFEED This bit is inverted and output onto the nAUTOFD output. A logic 1 causes the printer to generate a line feed after each line is printed. A logic 0 means no autofeed. BIT 2 nINIT ...
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Data in the tFIFO will not be transmitted to the to the parallel port lines using a hardware protocol handshake. However, data in the tFIFO may be displayed on the parallel port data lines. The tFIFO will not stall when ...
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Table 66 - DMA SOFTWARE SELECT ENCODING BITS 5:3 IRQ Software Select The IRQ Software Select bits indicate the IRQ channel number that has been allocated to the Parallel Port. The IRQ encoding is shown in Table 67. The IRQ ...
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BIT 2 serviceIntr Read/Write 1: Disables DMA and all of the service interrupts. 0: Enables one of the following 3 cases of interrupts. Once one of the 3 service interrupts has occurred serviceIntr bit shall be set to a “1” ...
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OPERATION Mode Switching/Software Control Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ...
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The most significant bit of the command indicates whether run-length count (for compression channel address. When in the reverse direction, normal data is transferred when PeriphAck is high and an 8 bit command is transferred ...
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When serviceIntr is 0, dmaEn is 0, direction is “1” and there are readIntrThreshold or more bytes in the FIFO. Also, an interrupt is generated when serviceIntr is cleared to “0” whenever there are readIntr Threshold or more bytes ...
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If PDRQ goes inactive due to the FIFO going ...
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AUTO POWER MANAGEMENT Power management is provided for the following FDC37N869 logical devices: Floppy Disk, UART1, UART2 and the Parallel Port. For each logical device two types of power management are provided; direct powerdown and auto powerdown. Direct powerdown is ...
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Register Behavior Table 71 reiterates the available FDC PC/AT and PS/2, including Model 30 mode, registers. In order to maintain software transparency, access to all the registers must be maintained regardless of the power state. As Table 70 shows, two ...
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Table 71 - State of System Pins in Auto Powerdown SYSTEM PINS FDD Interface Pins All pins in the FDD interface that can be connected directly to the floppy disk drive itself are either DISABLED or TRISTATED. Pins used for ...
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UART Power Management Direct UART power management is controlled by the UART1 and UART2 Power Down bits in Configuration Register 2. Refer to section CR02 on page 106 for more information. UART Auto Power Management is enabled by the UART ...
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IRQSER Cycle Modes There are two modes of operation for IRQSER cycles: Quiet (Active) Mode and Continuous (Idle) Mode. In Quiet Mode any device may initiate an IRQSER cycle. In Continuous Mode only the host controller can initiate an IRQSER ...
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A Start Frame may not be initiated while the IRQSER is Active. The IRQSER is Idle between Stop and Start Frames. The IRQSER is Active between Start and Stop Frames. Quiet Mode operation allows the IRQSER to be idle when ...
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IRQSER PERIOD The IRQSER IRQ/Data Frame will supports IRQ2 from a logical device. Previously, IRQSER Period 3 was reserved for use by the System Management Interrupt (nSMI). When using Period 3 for IRQ2 the user should mask ...
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ADD PCI nCLKRUN SUPPORT Overview The FDC37N869 supports the PCI nCLKRUN signal. nCLKRUN is used to indicate the PCI clock status as well as to request that a stopped clock be started. See Figure 6 for an example of a ...
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FDC37N869 FIGURE 6 - nCLKRUN SYSTEM IMPLEMENTATION EXAMPLE SIRQ_EN 1,2 ANY IRQ CHANGE nCLKRUN CLK33 FIGURE 7 - CLOCK START ILLUSTRATION Note 1: The signal “ANY IRQ CHANGE” is the same as “CHANGE” in Table 72. Note 2: The FDC37N869 ...
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PORT NAME CONFIG PORT INDEX PORT DATA PORT 1 Note : The INDEX and DATA ports are active only when the FDC37N869 is in the configuration state. 2 Note : The INDEX PORT is only readable in the configuration state. ...
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MOV AL,01H OUT DX,AL ;Point to CR1 MOV DX,3F1H MOV AL,9FH OUT DX,AL ;Update CR1 ; ; Repeat for all CRx registers ; ;-----------------------------. ; EXIT CONFIGURATION STATE | ;-----------------------------‘ MOV DX,3F0H MOV AX,AAH OUT DX,AL Configuration Select Register (CSR) ...
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DEFAULT INDEX DB7 - CR15 - CR16 03H CR17 00H CR18 - CR1D 80H CR1E 00H CR1F FDD3-DTx 3CH CR20 00H CR21 00H CR22 Reserved 00H CR23 00H CR24 00H CR25 00H CR26 00H CR27 00H CR28 Serial Port 1 ...
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BIT NO. BIT NAME 0,1 Reserved 2 Parallel Port 1 Power 3 Parallel Port Mode 4 Reserved 5,6 Reserved 7 Lock CRx 1 Note : Power Down bits d isable the respective logical device and associated pins, however the power ...
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CR02 CR02 can only be accessed in the configuration state and after the CSR has been initialized to 02H. The default value of this register after power up is 88H (Table 79). BIT NO. BIT NAME 0:2 Reserved 3 UART1 ...
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CR04 CR04 can only be accessed in the configuration state and after the CSR has been initialized to 04H. The default value after power up is 00H (Table 81). Table 81 - CR04: Parallel and Serial Extended Setup Register BIT ...
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CR05 CR05 can only be accessed in the configuration state and after the CSR has been initialized to 05H. The default value after power up is 00H (Table 82). Table 82 - CR05: Floppy Disk Setup Register BIT BIT NO. ...
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CR07 CR07 can only be accessed in the configuration state and after the CSR has been initialized to 07H. The default value of this register after power up is 00H (Table 85). CR07 controls auto power management and the floppy ...
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Table 87 - CR09: ADRx Upper Address Decoder and Configuration D7 D6 ADRx CONFIGURATION CONTROL CONFIGURATION CR0A CR0A can only be accessed in the configuration state and after the CSR has been initialized to 0AH. The default value of this ...
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CR0C CR0C can only be accessed in the configuration state and after the CSR has been initialized to 0CH. The default value of this register after power up is 02H (Table 92). CR0C controls the operating mode of the UART. ...
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CR10 CR10 can only be accessed in the configuration state and after the CSR has been initialized to 10H. The default value of this register after power up is 00H (Table 94). CR10 is a test control register and all ...
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Table 96 - Configuration Ports Base Address Registers INDEX R/W HARD RESET 2 0x12 R/W SYSOP=0: 0xF0 SYSOP=1: 0x70 1 0x13 R/W SYSOP= SYSOP=1: 0x03 1 Note : Writing CR13 changes the Configuration Ports base address. 2 ...
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Force Disk Change, Bits Setting either of the Force Disk Change bits active (1) forces the FDD nDSKCHG input active when the appropriate drive has been selected. FORCE DSKCHG1 and FORCE DSKCHG0 can be written to a ...
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FDD3 D7 D6 DT0 DT1 DRIVE TYPE DRVDEN0 DT0 DT1 0 0 DENSEL 0 1 DRATE1 1 0 nDENSEL 1 1 DRATE0 CR20 CR20 can only be accessed in the configuration state and after the CSR has been initialized to ...
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Table 107 - CR23: Parallel Port Base Address Register DB7 DB6 ADR9 ADR8 ADR7 Table 108 - Parallel Port Addressing Options EPP ENABLED Yes CR24 CR24 can only be accessed in the configuration state and after the CSR has been ...
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CR27 CR27 can only be accessed in the configuration state and after the CSR has been initialized to 27H. The default value of this register after power up is 00H (Table 112). CR27 is used to select the IRQ for ...
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CR29 CR29 can only be accessed in the configuration state and after the CSR has been initialized to 29H. The default value of this register after power up is 00H (Table 114). CR29 controls the HPMODE bit and is used ...
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CR2D CR2D can only be accessed in the configuration state and after the CSR has been initialized to 2DH. The default value of this register after power up is 03H (Table 117). CR2D is used to set the IR Half ...
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OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS Operating Temperature Range................................................................................................................................ 0 Storage Temperature Range ................................................................................................................................ -55 Lead Temperature Range (soldering, 10 seconds)......................................................................................................+325 Positive Voltage on any pin, with respect to Ground......................................................................................................... +5.5V Negative Voltage on any pin, with respect to Ground ........................................................................................................ ...
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Table 120 – DC Electrical Characteristics (T PARAMETER I Type Input Buffer Low Input Level High Input Level IS Type Input Buffer Low Input Level High Input Level Schmitt Trigger Hysteresis I Input Buffer CLK Low Input Level High Input ...
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Table 120 – DC Electrical Characteristics (T PARAMETER OD14 Type Buffer Low Output Level Output Leakage OP14 Type Buffer Low Output Level High Output Level Output Leakage IOP14 Type Buffer Low Output Level High Output Level Output Leakage O4 Type ...
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Table 121 - DC Electrical Characteristics (T PARAMETER I Type Input Buffer Low Input Level High Input Level IS Type Input Buffer Low Input Level High Input Level Schmitt Trigger Hysteresis I Input Buffer CLK Low Input Level High Input ...
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Table 121 - DC Electrical Characteristics (T PARAMETER O6 Type Buffer Low Output Level High Output Level Output Leakage OD14 Type Buffer Low Output Level Output Leakage OP14 Type Buffer Low Output Level High Output Level Output Leakage IOP14 Type ...
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Note 1: Output leakage is measured with the current pins in high impedance as defined by the PWRGD pin. Note 2: Output leakage is measured with the low driving output off, either for a high level output or a high ...
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Host Timing AX, AEN, nIOCS16 nIOR DATA (D0-D7) PD0-PD7, nERR, PE, SLCT, nACK, BUSY FINTR nIOR/nIOW PINTR PINTR is the interrupt assigned to the Parallel Port FINTR is the interrupt assigned to the Floppy Disk Parameter t1 A0-A9, AEN, nIOCS16 ...
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AX, AEN, nIOCS16 t1 nIOW DATA (D0-D7) FINTR PINTR PINTR is the interrupt assigned to the Parallel Port FINTR is the interrupt assigned to the Floppy Disk t1 A0-A9, AEN, nIOCS16 Set Up to nIOW Low t2 nIOW Width t3 ...
Page 128
AEN FDRQ, PDRQ FDACKX PDACKX t14 nIOR or nIOW DATA (DO-D7) TC FDRQ refers to the DRQ assigned to the Floppy Disk PDRQ refers to the DRQ assigned to the Parallel Port FDACKX refers to the nDACK assigned to the ...
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X1K nRESET Parameter Clock CycleTime for 14.318MHz t1 Clock High Time/Low Time for t2 14.318MHz Clock Cycle Time for 32kHz t1 Clock High Time/Low Time for 32kHz t2 Clock Rise Time/Fall Time (not shown) t4 nRESET Low Time The nRESET ...
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FDD Timing nDIR nDS0-3 nINDEX nRDATA nWDATA nIOW t 9 nDS0-1, nMTR0-1 (AT Mode timing only) Parameter t1 nDIR Set Up to nSTEP Low t2 nSTEP Active Time Low t3 nDIR Hold Time After ...
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Serial Port Timing nIOW nRTSx, nDTRx IRQx nCTSx, nDSRx, nDCDx IRQx nIOW IRQx nIOR nRIx Parameter t1 nRTSx, nDTRx Delay from nIOW t2 IRQx Active Delay from nCTSx, nDSRx, nDCDx t3 IRQx Inactive Delay from nIOR (Leading Edge) t4 IRQx ...
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DATA IRRX nIRRX Parameter t1 Pulse Width at 115kbaud t1 Pulse Width at 57.6kbaud t1 Pulse Width at 38.4kbaud t1 Pulse Width at 19.2kbaud t1 Pulse Width at 9.6kbaud t1 Pulse Width at 4.8kbaud t1 ...
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DATA IRTX nIRTX Parameter t1 Pulse Width at 115kbaud t1 Pulse Width at 57.6kbaud t1 Pulse Width at 38.4kbaud t1 Pulse Width at 19.2kbaud t1 Pulse Width at 9.6kbaud t1 Pulse Width at 4.8kbaud t1 ...
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DATA IRRX nIRRX t3 t4 MIRRX t5 t6 nMIRRX Parameter t1 Modulated Output Bit Time t2 Off Bit Time t3 Modulated Output "On" t4 Modulated Output "Off" t5 Modulated Output "On" t6 Modulated Output "On" Notes: ...
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DATA IRTX nIRTX t3 t4 MIRTX t5 t6 nMIRTX Parameter t1 Modulated Output Bit Time t2 Off Bit Time t3 Modulated Output "On" t4 Modulated Output "Off" t5 Modulated Output "On" t6 Modulated Output "On" Notes: ...
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Parallel Port Timing PD0- PD7 nIOW nINIT, nSTROBE. nAUTOFD, SLCTIN PINTR (SPP) nACK PINTR (ECP or EPP Enabled) nFAULT (ECP) nERROR (ECP) PINTR Parameter t1 nINIT, nSTROBE, nAUTOFD Delay from nIOW Inactive t2 PINTR Delay from nACK, nFAULT t3 PINTR ...
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Parallel Port EPP Timing AX SD<7:0> t17 t8 nIOW t10 IOCHRDY t13 t20 nWRITE t1 PD<7:0> t16 t3 nDATAST t14 nADDRSTB nWAIT Parameter t1 nIOW Asserted to PDATA Valid t2 nWAIT Asserted to nWRITE Change t3 nWRITE to Command Asserted ...
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AX t19 IOR SD<7:0> t8 IOCHRDY t9 t21 nWRITE t2 t25 PD<7:0> t28 t14 DATASTB ADDRSTB nWAIT Timing parameter table for the EPP Data or Address Read Cycle is found on next page. FIGURE 20 - EPP 1.9 DATA OR ...
Page 139
Parameter t1 PDATA Hi-Z to Command Asserted t2 nIOR Asserted to PDATA Hi-Z t3 nWAIT Deasserted to Command Deasserted t4 Command Deasserted to PDATA Hi-Z t5 Command Asserted to PDATA Valid t6 PDATA Hi-Z to nWAIT Deasserted t7 PDATA Valid ...
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AX SD<7:0> t17 t8 nIOW IOCHRDY t13 nWRITE PD<7:0> nDATAST nADDRSTB nWAIT Parameter t1 nIOW Asserted to PDATA Valid t2 Command Dessserted to nWRITE Change t3 nWRITE to Command t4 nIOW Deasserted to Command Deasserted t5 Command Deasserted to PDATA ...
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AX t19 nIOR SD<7:0> t8 IOCHRDY nWRITE PD<7:0> t23 nDATASTB nADDRSTB nWAIT Parameter nIOR Deasserted to Command Deasserted t2 nWAIT Asserted to IOCHRDY Deasserted t3 Command Deasserted to PDATA Hi-Z t4 Command Asserted to PDATA Valid t5 nIOR Asserted to ...
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Parallel Port ECP Timing Parallel Port FIFO (Mode 101) The standard parallel port is run at or near the peak 500 Kbps allowed in the forward direction using DMA. The state machine does not examine nAck and begins the next ...
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PDATA nSTROBE BUSY t1 DATA Valid to nSTROBE Active t2 nSTROBE Active Pulse Width t3 DATA Hold from nSTROBE Inactive t4 nSTROBE Active to BUSY Active t5 BUSY Inactive to nSTROBE Active t6 BUSY Inactive to PDATE Invalid NOTE: 1. ...
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PDATA<7:0> nSTROBE BUSY Parameter t1 nAUTOFD Valid to nSTROBE Asserted t2 PDATA Valid to nSTROBE Asserted t3 BUSY Deasserted to nAUTOFD Changed t4 nBUSY Deasserted to PDATA Changed t5 nSTROBE Asserted to BUSY Asserted t6 nSTROBE Deasserted to Busy ...
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PDATA<7:0> nACK nAUTOFD t1 PDATA Valid to nACK Asserted t2 nAUTOFD Asserted to PDATA Changed t3 nACK Asserted to nAUTOFD Deasserted t4 nACK Deasserted to nAUTOFD Asserted t5 nAUTOFD Asserted to nACK Asserted t6 nAUTOFD Deasserted to nACK Deasserted NOTES: ...
Page 146
Package Outlines 0. -C- Notes: 1 Coplanarity is 0.100mm maximum. 2 Tolerance on the position of the leads is 0.13mm maximum. 3 Package body dimensions D1 and E1 do not include the ...
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PAGE(S) SECTION/FIGURE/ENTRY 93 FDC Power Management SMSC DS – FDC37N869 FDC37N869 REVISIONS CORRECTION Note added under this section – see italicized text. Page 147 DATE REVISED 11/09/00 Rev. 11/09/2000 ...