USB97C100QFP SMSC Corporation, USB97C100QFP Datasheet

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USB97C100QFP

Manufacturer Part Number
USB97C100QFP
Description
Manufacturer
SMSC Corporation
Datasheet

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USB97C100QFP
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SMSC DS – USB97C100
High Performance USB Peripheral Controller
Engine
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Complete USB Specification 1.1 Compatibility
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High Speed (12Mbps) Capability
MMU and SRAM Buffer Allow Buffer Optimization
and Maximum Utilization of USB Bandwidth
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Integrated USB Transceiver
Serial Interface Engine (SIE)
8051 Microcontroller (MCU)
Patented Memory Management Unit (MMU)
4 Channel 8237 DMA Controller
(ISADMA)
4K Byte On Board USB Packet Buffer
Quasi-ISA Peripheral Interface
USB Bus Snooping Capabilities
GPIOs
Isochronous, Bulk, Interrupt, and Control
Data Independently Configurable per
Endpoint
Dynamic Hardware Allocation of -Packet
Buffer for Virtual Endpoints
Multiple Virtual Endpoints (up to 16 TX, 16
RX Simultaneously)
Multiple Alternate Address Filters
Dynamic Endpoint Buffer Length
Allocation (0-1280 Byte Packets)
128 Byte Page Size
10 Pages Maximum per Packet
Up to 16 Deep Receive Packet Queue
Up to 5 Deep Transmit Packet Queue, per
Endpoint
Hardware Generated Packet Header
Records Each Packet Status Automatically
Simultaneous Arbitration Between MCU,
SIE, and ISA DMA Accesses
Multi-Endpoint USB Peripheral Controller
Order Number: USB97C100QFP
ORDERING INFORMATION
128 Pin QFP Package
FEATURES
Extended Power Management
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DMA Capability with ISA Memory
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External MCU Memory Interface
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Quasi-ISA Interface Allows Interface to New and
"Legacy" Peripheral Devices
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5V or 3.3v Operation
On Board Crystal Driver Circuit
128 Pin QFP Package
Standard 8051 "Stop Clock" Modes
Additional USB and ISA Suspend
Resume Events
Internal 8MHz Ring Oscillator for Immediate
Low Power Code Execution
24, 16, 12, 8, 4, and 2 MHz PLL Taps For on
the Fly MCU and DMA Clock Switching
Independent Clock/Power Management for
SIE, MMU, DMA and MCU
Four Independent Channels
Transfer Between Internal and External
Memory
Transfer Between I/O and Buffer Memory
External Bus Master Capable
1M Byte Code and Data Storage via 16K
Windows
Flash, SRAM, or EPROM
Downloadable via USB, Serial Port, or ISA
Peripheral
1M ISA Memory Space via 4K MCU Window
64K ISA I/O Space via 256 Byte MCU
Window
4 External Interrupt Inputs
4 DMA Channels
Variable Cycle Timing
8 Bit Data Path
ADVANCE INFORMATION
USB97C100
Rev. 01/03/2001

Related parts for USB97C100QFP

USB97C100QFP Summary of contents

Page 1

... ISA I/O Space via 256 Byte MCU Window - 4 External Interrupt Inputs - 4 DMA Channels - Variable Cycle Timing - 8 Bit Data Path 5V or 3.3v Operation On Board Crystal Driver Circuit 128 Pin QFP Package ORDERING INFORMATION Order Number: USB97C100QFP 128 Pin QFP Package USB97C100 ADVANCE INFORMATION Rev. 01/03/2001 ...

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The USB97C100 is a flexible, general purpose USB peripheral interface and controller ideally suited for multiple endpoint applications. The USB97C100 provides an ISA-like bus interface, which will allow virtually any PC peripheral to be placed at the end of a ...

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FEATURES ................................................................................................................................................................... 1 GENERAL DESCRIPTION............................................................................................................................................ 2 PIN CONFIGURATION ................................................................................................................................................. 4 DESCRIPTION OF PIN FUNCTIONS ........................................................................................................................... 5 BUFFER TYPE DESCRIPTIONS.................................................................................................................................. 7 FUNCTIONAL DESCRIPTION...................................................................................................................................... 9 Serial Interface Engine (SIE)......................................................................................................................................... 9 Micro Controller Unit (MCU) .......................................................................................................................................... 9 SIEDMA......................................................................................................................................................................... 9 Memory Management Unit (MMU) ...

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SA10 1 SA9 2 3 SA8 SA7 4 SA6 5 6 SA5 SA4 7 GND 8 SA3 9 SA2 10 SA1 11 12 SA0 13 SA13 14 SA14 15 SA15 SA16 16 17 SA17 18 SA18 19 SA19 20 GND ...

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DESCRIPTION OF PIN FUNCTIONS QFP PIN NUMBER SYMBOL 100 READY Channel is ready when high. ISA memory or slave devices use this signal to lengthen a bus cycle from the default time. Extending the length of the bus cycle can ...

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QFP PIN NUMBER SYMBOL 102 nMASTER External Bus master, active low This signal forces the USB97C100 to immediately tri-state its external bus, even if internal transactions are not complete. All shared ISA signals are tri-stated, except 8237 nDACKs, which can ...

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QFP PIN NUMBER SYMBOL 27 PWRGD Active high input. This signal is used to indicate to that chip that a good power level has been reached. When inactive/low, all pins are Tri- stated except TST_OUT and a POR is generated. ...

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USB97C100 BLOCK DIAGRAM End Point Control SIE DMA General Queue Purpose IO GPIO GPIO[0:7] FD[7:0] FA[19:0] nFRD nFWR nFCE Flash Interface IRQ[3:0] SMSC DS – USB97C100 Serial Interface Engine Rx/TX Arbiter 8051 8237 SD[7:0], nIOW, DRQ[3:0], SA[19:0] nIOR, nDACK[3:0], nMEMW, ...

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FUNCTIONAL DESCRIPTION The USB97C100 incorporates a USB Serial Interface Engine (SIE), 8051 Microcontroller Unit (MCU), Serial Interface Engine DMA (SIEDMA), a programmable 8237 ISA bus DMA controller (ISADMA), 4K bytes of SRAM for data stream buffering, and a patented MMU ...

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Applications The USB97C100 enables entirely new I/O applications, as well as new form factors for existing Legacy I/O applications. PC98 compliance encourages the elimination ofDMA, IRQ and addressing conflicts via total on-board ISA elimination. With the USB97C100, the ISA bus ...

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USB EXPANSION USB SMSC DS – USB97C100 TYPICAL MONITOR APPLICATION 37C67X USB HUB SIO (opt.) 97C100 Commanche ISA CODEC USB TYPICAL FLOPPY DRIVE APPLICATION 37C78 97C100 FDC Commanche Page 11 FLOPPY PS/2 SERIAL/FIR PARALLEL Rev. 01/03/2001 ...

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TYPICAL SIGNAL CONNECTIONS FDC LPT 37C669FR UART IR SMSC DS – USB97C100 SRAM SD[7..0] SA[10..0] FDC IRQ[3..0] nDACK[3..0] DRQ[3..0] TC nIOR nIOW 24MHz Page 12 USB UPSTREAM USB97C100 FLASH Rev. 01/03/2001 ...

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MCU Memory Map The 64K memory map is as follows from the 8051's viewpoint: Code Space 8051 ADDRESS 0xC000-0xFFFF Movable 16k page 0x8000-0xBFFF Fixed 16k page 0x7000-0x7FFF Movable 16k FLASH page 16k pages in 0x6000-0x6FFF External FLASH ...

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MCU Block Register Summary ADDRESS NAME 7F00 ISR_0 7F01 IMR_0 7F02 ISR_1 7F03 IMR_1 7F06 DEV_REV 7F07 DEV_ID 7F18 GPIOA_DIR 7F19 GPIOA_OUT 7F1A GPIOA_IN 7F1B UTIL_CONFIG 7F27 CLOCK_SEL 7F29 MEM_BANK 7F2A WU_SRC_1 7F2B WU_MSK_1 7F2C WU_SRC_2 7F2D WU_MSK_2 7F10 GP1Data ...

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MMU Block Register Summary ADDRESS NAME 0x6000 MMU_DATA 7F50 PRL 7F51 PRH 7F52 MMUTX_SEL 7F53 MMUCR 7F54 ARR 7F55 PNR 7F56 PAGS_FREE 7F57 TX_MGMT 7F58 RXFIFO 7F59 POP_TX 7F60 TXSTAT_A 7F61 TXSTAT_B 7F62 TXSTAT_C 7F63 TXSTAT_D 7F64 MMU_TESTx 7F65 MMU_TESTx ...

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SIE Block Register Summary ADDRESS NAME 7F80 EP_CTRL0 7F81 EP_CTRL1 7F82 EP_CTRL2 7F83 EP_CTRL3 7F84 EP_CTRL4 7F85 EP_CTRL5 7F86 EP_CTRL6 7F87 EP_CTRL7 7F88 EP_CTRL8 7F89 EP_CTRL9 7F8A EP_CTRL10 7F8B EP_CTRL11 7F8C EP_CTRL12 7F8D EP_CTRL13 7F8E EP_CTRL14 7F8F EP_CTRL15 7F90 FRAMEL ...

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MCU REGISTER DESCRIPTION MCU Runtime Registers ISR_0 (0x7F00 - RESET=0x00) BIT NAME 7 IRQ3 6 IRQ2 5 IRQ1 4 IRQ0 3 RX_PKT 2 TX_EMPTY 1 TX_PKT 0 ISADMA These bits are automatically cleared each time this register is read. Therefore, ...

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IMR_0 (0x7F01- RESET=0xFF) BIT NAME 7 IRQ3 6 IRQ2 5 IRQ1 4 IRQ0 3 RX_PKT 2 TX_EMPTY 1 TX_PKT 0 ISADMA ISR_1 (0x7F02- RESET=0x00) BIT NAME [7:5] Reserved 4 EOT 3 SOF 2 ALLOC 1 RX_OVRN 0 PWR_MNG Notes: These ...

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IMR_1 (0x7F03- RESET=0xFF) BIT NAME [7:5] Reserved 4 EOT 3 SOF 2 ALLOC 1 RX_OVRN 0 PWR_MNG DEV_REV (0x7F06- RESET=0xXX) BIT [7:0] Rev. DEV_ID (0x7F07- RESET=0x25) BIT [7:0] BCD '25' HEX 0x25 GP_FIFO1 (0x7F10- RESET=0xXX) BIT NAME [7:0] GP_FIFO1 GP_FIFO2 ...

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GP_FIFO4 (0x7F16 - RESET=0xXX) BIT NAME [7:0] GP_FIFO4 FIFO Status Registers GPFIFO1_STS (0x7F11 – RESET=0x01) BIT NAME [7:2] Reserved 1 GPFIFO1_FULL 0 GPFIFO1_EMPTY GPFIFO2_STS (0x7F13 – RESET=0x01) BIT NAME [7:2] Reserved 1 GPFIFO2_FULL 0 GPFIFO2_EMPTY GPFIFO3_STS (0x7F15 – RESET=0x01) BIT ...

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RESET=0x00) BIT GPIO1/TXD 0 GPIO0/RXD Note: The Timer inputs T[1:0] can be configured as outputs and left unconnected so that software can write to the bits to trigger the timer. Otherwise, the ...

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UTIL_CONFIG (0x7F1B- RESET=0x00) BIT NAME [7:4] Reserved 3 GPIO3/T1 2 GPIO2/T0 1 GPIO1/TXD 0 GPIO0/RXD Notes: In Counter mode, the 8051 must sample T[1: '1' in one instruction cycle, and then '0' in the next. So for 12MHz, ...

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GPIO Direction Bit (0x7F18[7:4]) 8051 "T0 timer P3.4" 8051 "T1 timer P3.5" 0 RXD "Uart P3.0" 0X7F1B[0] GPIO1 data out (0x7F19[1]) TXD "Uart P3.1" 0X7F1B[1] SMSC DS – USB97C100 GPIO out data (0x7F19[7:4]) GPIO in data (0x7F1A[7:4]) GPIO2 ...

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MCU Power Management Registers Table 27 - MCU/ISADMA Clock Source Select CLOCK_SEL (0x7F27 - RESET=0x40) BIT NAME 7 SLEEP 6 ROSC_EN 5 MCUCLK_SRC [4:3] MCU_CLK[1:0] 2 ISADMACLK_EXT [1:0] ISADMACLK[1:0] Notes: The 8051 may program itself to run off of an ...

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MEM_BANK (0x7F29 - RESET=0x01) BIT NAME R/W [7:6] Reserved R [5:0] A[19:14] R/W WU_SRC_1 (0x7F2A - RESET=0x00) BIT NAME R/W [7:3] Reserved R 2 USB_Reset R 1 Resume R 0 Reserved '0' R Notes: Only low to high transitions for ...

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WU_SRC_2 (0x7F2C - RESET=0x00) BIT NAME [7:4] '0' 3 IRQ3 2 IRQ2 1 IRQ1 0 IRQ0 Notes: Any transition from high to low, or low to high on the associated input sets these bits. These bits are cleared each time ...

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MCU ISA Interface Registers BUS_REQ (0x7F70 – RESET=0x00) BIT NAME R/W 7 INH_TC3 R/W 6 INH_TC2 R/W 5 INH_TC1 R/W 4 INH_TC0 R/W 3 RESET_8237 R/W 2 AEN 1 HLDA R/W 0 HREQ Note: HLDA Example: When the 8051 is ...

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BUS_STAT (0x7F73 - RESET=0xXX) BIT NAME 7 CH3RQ 6 CH2RQ 5 CH1RQ 4 CH0RQ 3 CH3TC 2 CH2TC 1 CH1TC 0 CH0TC Notes: Each bit in this register reflects the current value of the corresponding bit in the 8237 CH_STAT ...

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BUS_MASK (0x7F74 - RESET=0xFF) BIT NAME 7 CH3RQ_MASK 6 CH2RQ_MASK 5 CH1RQ_MASK 4 CH0RQ_MASK 3 CH3TC_MASK 2 CH2TC_MASK 1 CH1TC_MASK 0 CH0TC_MASK IOBASE (0x7F71 - RESET=0x00) BIT NAME [7:0] SA[15:8] Table 37 - ISA Memory Window Base Register MEMBASE (0x7F72 ...

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REGISTER DESCRIPTION Memory Map 8237 MEMORY ADDRESS 0xFC00-0xFFFF 0xF800-0xFBFF 0xF400-0xF7FF 0xF000-0xF3FF 0xEC00-0xEFFF 0xE800-0xEBFF 0xE400-0xE7FF 0xE000-0xE3FF 0xDC00-0xDFFF 0xD800-0xDBFF 0xD400-0xD7FF 0xD000-0xD3FF 0xCC00-0xCFFF 0xC800-0xCBFF 0xC400-0xC7FF 0xC000-0xC3FF 0xBC00-0xBFFF 0xB800-0xBBFF 0xB400-0xB7FF 0xB000-0xB3FF 0xAC00-0xAFFF 0xA800-0xABFF 0xA400-0xA7FF 0xA000-0xA3FF 0x9C00-0x9FFF 0x9800-0x9BFF 0x9400-0x97FF 0x9000-0x93FF 0x8C00-0x8FFF 0x8800-0x8BFF 0x8400-0x87FF ...

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Runtime Registers The DMA controller has a block of 16 R/W registers which normally occupy I/O locations 0x00-0x0F on the ISA bus. When they are located at 0x0000-0x000F on the ISA bus, the 8051 can access them by programming the ...

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Table 40 - 8237 Address Programming Guide 8237 INTERNAL ADDRESS PROGRAMMING GUIDE BIT NAME 15 INT_EXT [14:10] PN[4:0]/SA[14:10] [9:0] PTR[9:0]/SA[9:0] Note: SA[19..15] are driven low when the 8237 is accessing external ISA memory. PTR10 is driven low when the 8237 ...

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CH1_CNT (ISA 0x0003) BIT NAME [7:0] CH1_CNTL [7:0] CH1_CNTH Note: The CLEAR_FF register should be written to before writing this register to guarantee which byte (high or low) is being written. See Address Programming Table for 16 bit Address definitions. ...

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CH_STAT (ISA 0x0008) BIT NAME 7 CH3RQ 6 CH2RQ 5 CH1RQ 4 CH0RQ 3 CH3TC 2 CH2TC 1 CH1TC 0 CH0TC Notes: These bits are also visible outside of I/O space in the BUS_STAT register. These bits are cleared when ...

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Table 51 - 8237 Write Single Request Register CH_REQ (ISA 0x0009) BIT NAME [7:3] Reserved 2 SET_CLR [1:0] SEL[1:0] CH_MASK (ISA 0x000A) BIT NAME [7:3] Reserved 2 SET_CLR [1:0] SEL[1:0] DMA_MODE (ISA 0x000B) BIT NAME [7:6] MODE[1:0] 5 INC_DEC 4 ...

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RD_TEMP (ISA 0x000D) BIT NAME [7:0] TEMP_BYTE MSTR_CLR: (ISA 0x000D) BIT NAME [7:0] SW_RESET CLR_MASK: (ISA 0x000E) BIT NAME [7:0] CLR_ALL ALL_MASK (ISA 0x000F) BIT NAME [7:4] Reserved 3 CH3_MASK 2 CH2_MASK 1 CH1_MASK 0 CH0_MASK SMSC DS – USB97C100 ...

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MEMORY MANAGEMENT UNIT (MMU) REGISTER DESCRIPTION MMU Interface Registers MMU_DATA (0x6000) BIT NAME [7:0] [D7:D0] Notes: The Read FIFO may take at most 1.218µs after the PNH is written to present valid data. The Write FIFO may take at most ...

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PRH (0x7F51) BIT NAME 7 RCV 6 AUTO_INCR 5 READ [4:3] Reserved [2:0] A[10:8] Note: This register must be written after PRL for its value to take effect. MMUTX_SEL (0x7F52) BIT NAME [7:4] Reserved [3:0] EP[3:0] Note: This register must ...

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Remove Packet from top of RX Queue : To be issued after MCU has completed processing the 011 packet number at the RXFIFO. Remove and Release Top of RXFIFO : Same as (011), but also frees all memory used by ...

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MMU Free Pages Register MMU Free Pages bits, and a global NAK_ALLRX (this can only NACK OUT and Bulk packets) control bit for the firmware to view the real time status of the 32 page allocation bits. This allows the ...

Page 41

Table 68 - Receive Packet Number FIFO Register RXFIFO (0x7F58) BIT NAME 7 RXFIFO_EMPT Y 6 RXFIFO_FULL 5 Reserved [4:0] P[4:0] A "complete" reception requires that the 8 byte status header is correctly written into the packet buffer, with the ...

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TXSTAT_A (0x7F60 - RESET=0x55) BIT NAME 7 EP3TX_EMPTY 6 EP3TX_FULL 5 EP2TX_EMPTY 4 EP2TX_FULL 3 EP1TX_EMPTY 2 EP1TX_FULL 1 EP0TX_EMPTY 0 EP0TX_FULL STAT_B (0x7F61 - RESET=0x55) BIT NAME 7 EP7TX_EMPTY 6 EP7TX_FULL 5 EP6TX_EMPTY 4 EP6TX_FULL 3 EP5TX_EMPTY 2 EP5TX_FULL ...

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STAT_B (0x7F61 - RESET=0x55) BIT NAME 1 EP4TX_EMPTY 0 EP4TX_FULL TXSTAT_C (0x7F62 - RESET=0x55) BIT NAME 7 EP11TX_EMPTY 6 EP11TX_FULL 5 EP10TX_EMPTY 4 EP10TX_FULL 3 EP9TX_EMPTY 2 EP9TX_FULL 1 EP8TX_EMPTY 0 EP8TX_FULL SMSC DS – USB97C100 TRANSMIT FIFO STATUS REGISTER ...

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TXSTAT_D (0x7F63 - RESET=0x55) BIT NAME 7 EP15TX_EMPTY 6 EP15TX_FULL 5 EP14TX_EMPTY 4 EP14TX_FULL 3 EP13TX_EMPTY 2 EP13TX_FULL 1 EP12TX_EMPTY 0 EP12TX_FULL TX_MGMT (0x7F67 - RESET=0x00) BIT NAME [7:1] Reserved 0 MEM_DALL SMSC DS – USB97C100 Table 73 - Transmit ...

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SERIAL INTERFACE ENGINE (SIE) REGISTER DESCRIPTION Packet Header Definition The following header contains information to determine endpoint, status, length of the received packet, and the payload “received data”. OFFSET MSB 7 < Payload Data Byte n ...

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SIE Interface Registers The architecture of the USB97C100 is such that there are no data FIFO's associated with individual endpoints. The MMU does not differentiate packets by endpoint number. The firmware must read the endpoint number from the packet header ...

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If the firmware needs to STALL an endpoint, it should first be taken off-line by setting RX_CONT1=0, and then RX_CON0=1. This allows firmware to manage TX endpoint(s) and hold queued data until the firmware is ready, even if the host ...

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ALT_ADDR1 (0x7F99 - RESET=0x00) BIT NAME 7 EN_ALTADDR1 6 ALT6 5 ALT5 4 ALT4 3 ALT3 2 ALT2 1 ALT1 0 ALT0 Notes: Endpoint numbers used for ALT_ADDRx are the compliment of the actual Endpoint number received. For example, any ...

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SIE_STAT (0x7F93 - RESET=0xXX) BIT NAME 7 ERR 6 TIMEOUT 5 SETUP_TOKEN 4 SOF_TOKEN 3 PRE_TOKEN 2 ACK 1 USB_RESET 0 EOT Note: This read only register reflects the status signals from the SIE state machine. This register can be ...

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SIE_CONFIG (0x7F98 - RESET=0x40) BIT NAME 7 FSEN 6 RST_SIE 5 RST_FRAME 4 EN_EXTFRAME 3 SIE_SUSPEND 2 SIE_RESUME 1 USB_RESUME 0 USB_RESET SMSC DS – USB97C100 Table 85 - SIE Configuration Register SIE CONFIGURATION REGISTER R/W DESCRIPTION R/W This bit ...

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MAXIMUM GUARANTEED RATINGS Operating Temperature Range ...........................................................................................................................0 Storage Temperature Range ........................................................................................................................... -55 Lead Temperature Range (soldering, 10 seconds).....................................................................................................+325 Positive Voltage on any pin, with respect to Ground .................................................................................................V Negative Voltage on any pin, with respect to Ground .................................................................................................... -0.3V Maximum ...

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PARAMETER I/O8 Type Buffer Low Output Level High Output Level Output Leakage I/O16 Type Buffer Low Output Level High Output Level Output Leakage I/O24 Type Buffer Low Output Level High Output Level Output Leakage IO-U Note 2 Supply Current Unconfigured ...

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CAPACITANCE T PARAMETER Clock Input Capacitance Input Capacitance Output Capacitance USB PARAMETERS The following tables and diagrams were obtained from the USB specification USB DC PARAMETERS 1.0 0.8 0.6 0.4 0.2 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ...

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PARAMETER Capacitance Transceiver Capacitance Terminals Bus Pull-up Resistor on Root Port Bus Pull-down Resistor on Downstream Port Note 1: All voltages are measured from the local ground potential, unless otherwise specified. Note 2: All timing use a capacitive load (CL) ...

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T PERIOD Crossover Differential Data Lines FIGURE 8 - DIFFERENTIAL TO EOP TRANSITION SKEW AND EOP WIDTH T PERIOD Differential Data Lines Table 87 - Full Speed (12Mbps) Source Electrical Characteristics PARAMETER DRIVER CHARACTERISTICS: Transition Time: Rise ...

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PARAMETER Differential to EOP transition Skew Receiver Data Jitter Tolerance To next Transition For Paired Transitions Differential Data Jitter To next Transition For Paired Transitions EOP Width at receiver Must reject as EOP Must Accept CABLE IMPEDANCE AND TIMING: Cable ...

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NAME DESCRIPTION t1 SA[x] and AEN Valid to nIOW Asserted t2 nIOW Asserted to nIOW Deasserted t3 nIOW Deasserted to SA[x] Invalid t4 SD[x] Valid to nIOW Deasserted t5 SD[x] Hold from nIOW Deasserted t6 nIOW Deasserted to nIOW Asserted ...

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CLOCKI NAME DESCRIPTION t1 Clock Cycle Time for 24 MHz t2 Clock High Time/Low Time for 14.318 MHz Clock Rise Time/Fall Time (not shown SA[19:0] AEN nDACK nMEMRD/nIOR or nMEMWR/nIOW DATA SD[7:0] TC FIGURE 13 ...

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SA[19:0] AEN nDACK nMEMRD /nIOR or nMEMWR/ nIOW DATA SD[7:0] TC FIGURE 14 - DMA TIMING (BURST TRANSFER MODE) Table 92 - DMA Timing (Burst Transfer Mode) Parameters NAME t1 SA[19:0] Address Setup time to nMEMRD/nIOR or nMEMWR/nIOW Asserted t2 ...

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FALE t10 FA] nRD FD FIGURE 15 - 8051 FLASH PROGRAM FETCH TIMING Table 93 - 8051 Flash Program Fetch Timing Parameters PARAMETER t1 FA Valid to nRD asserted t2 nRD active pulse width t3 nRD deasserted to FA ...

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FALE t10 SA[19:0] nMEMRD SD[7:0] FIGURE 16 - 8051 FLASH MEMORY READ TIMING Table 94 - 8051 Flash Memory Read Timing Parameters PARAMETER t1 SA[19:0] Valid to nMEMRD asserted t2 nMEMRD active pulse width t3 nMEMRD deasserted to SA[19:0] Invalid ...

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FALE t10 SA[19:0] nMEMWR SD[7:0] FIGURE 17 - 8051 FLASH MEMORY WRITE TIMING Table 95 - 8051 Flash Memory Read Timing Parameters PARAMETER t1 SA[19:0] Valid to nMEMWR asserted t2 nMEMWR active pulse width t3 nMEMWR deasserted to SA[19:0] Invalid ...

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DETAIL "A" -C- Notes: 1) Coplanarity is 0. 3.2 mils maximum. 2) Tolerance on the position of the leads is 0.080 mm maximum. 3) Package body dimensions D1 and ...

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PAGE SECTION/FIGURE/ENTRY 1 FEATURES 52 DC ELECTRICAL CHARACTERISTICS 5 PIN DESCRIPTION - READY 1 FEATURES 6 PIN DESCRIPTION/Power Signals 51 DC ELECTRICAL CHARACTERISTICS 53 CAPACITANCE SMSC DS – USB97C100 USB97C100 REVISIONS CORRECTION “Complete USB Specification 1.0 Compatibility” changed to 1.1 ...

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