GS881Z36AT-133 GSI Technology, GS881Z36AT-133 Datasheet

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GS881Z36AT-133

Manufacturer Part Number
GS881Z36AT-133
Description
133MHz 8.5ns 256K x 36 8Mb pupelined and flow through sync NBT SRAM
Manufacturer
GSI Technology
Datasheet

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Part Number:
GS881Z36AT-133IT
Manufacturer:
GSI
Quantity:
20 000
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• User-configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
• Fully pin-compatible with both pipelined and flow through
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip write parity checking; even or odd selectable
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
Functional Description
The GS881Z18/36AT is a 9Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Rev: 1.03 11/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
read-write-read bus utilization
NtRAM™, NoBL™ and ZBT™ SRAMs
Through
Pipeline
3-1-1-1
2-1-1-1
3.3 V
2.5 V
3.3 V
2.5 V
Flow
9Mb Pipelined and Flow Through
Synchronous NBT SRAM
Curr (x18)
Curr (x36)
Curr (x18)
Curr (x36)
Curr (x18)
Curr (x36)
Curr (x18)
Curr (x36)
tCycle
tCycle
t
t
KQ
KQ
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
280
330
275
320
175
200
175
200
2.5
4.0
5.5
5.5
1/31
255
300
250
295
165
190
165
190
2.7
4.4
6.0
6.0
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS881Z18/36AT may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS881Z18/36AT is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 100-pin TQFP package.
230
270
230
265
160
180
160
180
3.0
5.0
6.5
6.5
200
230
195
225
150
170
150
170
3.4
6.0
7.0
7.0
GS881Z18/36AT-250/225/200/166/150/133
185
215
180
210
145
165
145
165
3.8
6.7
7.5
7.5
165
190
165
185
135
150
135
150
4.0
7.5
8.5
8.5
mA
mA
mA
mA
mA
mA
mA
mA
ns
ns
ns
ns
© 2001, GSI Technology
250 MHz–133 MHz
2.5 V or 3.3 V V
2.5 V or 3.3 V I/O
DD

Related parts for GS881Z36AT-133

GS881Z36AT-133 Summary of contents

Page 1

... Curr (x36) 200 190 180 170 165 Curr (x18) 175 165 160 150 145 Curr (x36) 200 190 180 170 165 1/31 250 MHz–133 MHz 3.3 V I/O 4.0 ns 7.5 ns 165 mA 190 mA 165 mA 185 mA 8.5 ns 8.5 ns 135 mA 150 mA 135 mA 150 mA © 2001, GSI Technology DD ...

Page 2

... DDQ DQP DDQ DDQ DDQ © 2001, GSI Technology ...

Page 3

... DQP Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS881Z18/36AT-250/225/200/166/150/133 GS881Z36AT Pinout (Package T) 256K x 36 Top View 3/31 DQP ...

Page 4

... Byte D Data Input and Output pins Power down control; active high Pipeline/Flow Through Mode Control; active low Linear Burst Order; active low. Core power supply Ground Output driver power supply 4/31 ; active low A9 ; active low B9 ; active low C9 ; active low D9 © 2001, GSI Technology ...

Page 5

... GS881Z18/36A NBT SRAM Functional Block Diagram Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS881Z18/36AT-250/225/200/166/150/133 Amps Sense Drivers Write 5/31 © 2001, GSI Technology ...

Page 6

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS881Z18/36AT-250/225/200/166/150/133 & determine which bytes will be written. All or none may be activated. A write cycle D 6/ and E ). Deassertion of any one of the Enable © 2001, GSI Technology ...

Page 7

... High-Z 1,2,3, High High High High High High © 2001, GSI Technology Notes 1,10 2 1,2,10 3 1,3, ...

Page 8

... and D represent input command codes as indicated in the Synchronous Truth Table. n+1 n+2 ƒ ƒ Next State Pipelined and Flow Through Read/Write Control State Diagram 8/31 New Write Burst Write B D n+3 ƒ ƒ © 2001, GSI Technology ...

Page 9

... Transition and D represent input command codes as indicated in the Truth Tables. Next State (n+2) n n+1 n+2 ƒ ƒ Intermediate Current State State Pipeline Mode Data I/O State Diagram 9/31 Intermediate R B Data Out W (Q Valid) D n+3 ƒ ƒ Next State © 2001, GSI Technology ...

Page 10

... Pipeline and Flow through Read Write Control State Diagram 10/ Data Out W (Q Valid) D Notes: 1. The Hold command (CKE Low) is not shown because it prevents any state change and D represent input command codes as indicated in the Truth Tables. n+2 n+3 ƒ ƒ © 2001, GSI Technology ...

Page 11

... The burst counter wraps to initial state on the 5th clock. 11/31 Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby High Drive (Low Impedance) Low Drive (High Impedance) A[1:0] A[1:0] A[1:0] A[1: BPR 1999.05.18 © 2001, GSI Technology ...

Page 12

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS881Z18/36AT-250/225/200/166/150/133 Sleep Mode Timing Diagram tKH tKH tKL tKL tZZS tZZH 12/31 2. The duration of SB tZZR on pipelined parts and V on flow DDQ © 2001, GSI Technology DDQ ...

Page 13

... V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn 13/31 Value –0.5 to 4.6 –0.5 to 4.6 –0 +0.5 (≤ 4.6 V max.) DDQ –0 +0.5 (≤ 4.6 V max.) DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Typ. Max. Unit 3.3 3.6 V 2.5 2.7 V 3.3 3.6 V 2.5 2.7 V © 2001, GSI Technology Unit Notes ...

Page 14

... T 25 – not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn 14/31 Max. Unit Notes 0.3 V 1,3 DDQ 0.8 V 1,3 Max. Unit Notes 0.3 0.3 V 1,3 DDQ 0.3*V V 1,3 DD Max. Unit Notes ° ° © 2001, GSI Technology ...

Page 15

... V DD 50% V Symbol Test conditions I/O OUT Conditions V – DDQ Fig. 1 Output Load 1 DQ 50Ω V DDQ/2 * Distributed Test Jig Capacitance 15/31 50% tKC Typ. Max. Unit 30pF © 2001, GSI Technology ...

Page 16

... OH3 OH DDQ 16/31 Min – ≥ V – ≤ V –1 uA 100 uA IH ≥ V –100 uA IL ≤ V – – 2.375 V 1 3.135 V 2.4 V — © 2001, GSI Technology Max — — 0.4 V ...

Page 17

... Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS881Z18/36AT-250/225/200/166/150/133 17/31 © 2001, GSI Technology ...

Page 18

... GSI Technology -133 Unit Min Max 7.5 — ns 4.0 ns — 1.5 — ns 1.5 ns — 1.5 — ns 0.5 ns — 8.5 — ns 8.5 ns — 3.0 — ns 3.0 ns — ...

Page 19

... Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS881Z18/36AT-250/225/200/166/150/133 Pipeline Mode Timing Suspend Read C Write D writeno-op tKH tKH tKC tKC tKL tKL D(A) Q(B) Q(C) 19/31 Read E Deselect E tLZ tHZ tKQ tKQX D(D) Q(E) © 2001, GSI Technology ...

Page 20

... Flow Through Mode Timing Write B+1 Read C Cont tKL tKL tKH tKH tKC tKC C D tKQ tLZ D(B) D(B+1) Q(C) tOHZ 20/31 Read D Write E Read F Write tKQ tKQX tHZ tLZ Q(D) D(E) Q(F) tOLZ tOE . The JTAG output DD . TDO should be left unconnected. SS © 2001, GSI Technology tKQX D(G) ...

Page 21

... Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS881Z18/36AT-250/225/200/166/150/133 Description 21/31 © 2001, GSI Technology ...

Page 22

... JTAG TAP Block Diagram · · · · · · Boundary Scan Register 0 Bypass Register Instruction Register ID Code Register · · · · Control Signals Test Access Port (TAP) Controller 22/31 · · TDO © 2001, GSI Technology ...

Page 23

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS881Z18/36AT-250/225/200/166/150/133 Not Used Configuration 23/31 GSI Technology I/O JEDEC Vendor ID Code © 2001, GSI Technology ...

Page 24

... JTAG Tap Controller State Diagram 1 1 Select Capture DR 0 Shift Exit1 DR 0 Pause Exit2 Update 24/31 1 Select Capture IR 0 Shift Exit1 IR 0 Pause Exit2 Update © 2001, GSI Technology ...

Page 25

... Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS881Z18/36AT-250/225/200/166/150/133 25/31 © 2001, GSI Technology ...

Page 26

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS881Z18/36AT-250/225/200/166/150/133 Conditions V – DDQ V /2 DDQ Description 26/31 JTAG Port AC Test Load * 50Ω 30pF V /2 DDQ * Distributed Test Jig Capacitance Notes © 2001, GSI Technology ...

Page 27

... Max. Unit Notes V +0.3 2.0 V DD3 0.8 V –0 DD2 0 –0.3 DD –300 1 uA 100 uA –1 – 1.7 V — — 0 – 100 mV V — DDQ — 100 mV V tTKL tTKL © 2001, GSI Technology ...

Page 28

... For information regarding the Boundary Scan Chain obtain BSDL files for this part, please contact our Applications Engineering Department at: apps@gsitechnology.com. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS881Z18/36AT-250/225/200/166/150/133 Min Max Unit 50 — ns — — ns — — ns — 28/31 © 2001, GSI Technology ...

Page 29

... All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS881Z18/36AT-250/225/200/166/150/133 θ 0.10 0.15 1.40 1.45 0.30 0.40 0.20 — e 22.0 22.1 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — 0.10 — 7° 29/ © 2001, GSI Technology ...

Page 30

... GS881Z36AT-166I 256K x 36 GS881Z36AT-150I 256K x 36 GS881Z36AT-133I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS881Z36A-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user ...

Page 31

... Updated AC Test Conditions table and removed Output Load 2 diagram • Removed Preliminary banner Content • Removed pin locations from pin description table • Removed BSR table • Updated format Format/Content • Updated mechanical drawings • Updated timing diagrams 31/31 © 2001, GSI Technology ...

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