GS8160E32T-133 GSI Technology, GS8160E32T-133 Datasheet

GS8160E32T-133

Manufacturer Part Number

GS8160E32T-133

Description

8.5ns 133MHz 512K x 32 synchronous burst SRAM

Manufacturer

GSI Technology

Datasheet

1.GS8160E32T-133.pdf (25 pages)

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100-Pin TQFP

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipeline

• Dual Cycle Deselect (DCD) operation

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

Functional Description

Applications

The GS8160E18/32/36T is an 18,874,368-bit (16,777,216-bit for x32

version) high performance synchronous SRAM with a 2-bit burst

address counter. Although of a type originally developed for Level 2

Cache applications supporting high performance CPUs, the device

now finds application in synchronous SRAM applications, ranging

from DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst control

inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW)

are synchronous and are controlled by a positive-edge-triggered clock

input (CK). Output enable (G) and power down control (ZZ) are

asynchronous inputs. Burst cycles can be initiated with either ADSP

or ADSC inputs. In Burst mode, subsequent burst addresses are

generated internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or interleave order

Rev: 2.13 11/2004

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

operation

Through

Pipeline

3-1-1-1

2-1-1-1

3.3 V

2.5 V

Flow

3.3 V

2.5 V

18Mb Sync Burst SRAMs

Curr (x32/x36)

Curr (x18)

tCycle

1M x 18, 512K x 36

Parameter Synopsis

1/25

-250 -225 -200 -166 -150 -133 Unit

280

330

275

320

175

200

175

200

2.5

4.0

5.5

255

300

250

295

165

190

165

190

2.7

4.4

6.0

with the Linear Burst Order (LBO) input. The Burst function need not

be used. New addresses can be loaded on every cycle with no

degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the user

via the FT mode pin (Pin 14). Holding the FT mode pin low places the

RAM in Flow Through mode, causing output data to bypass the Data

Output Register. Holding FT high places the RAM in Pipeline mode,

activating the rising-edge-triggered Data Output Register.

DCD Pipelined Reads

The GS8160E18/32/36T is a DCD (Dual Cycle Deselect) pipelined

synchronous SRAM. SCD (Single Cycle Deselect) versions are also

available. DCD SRAMs pipeline disable commands to the same

degree as read commands. DCD RAMs hold the deselect command

for one full cycle and then begin turning off their outputs just after the

second rising edge of clock.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable (BW)

input combined with one or more individual byte write signals (Bx).

In addition, Global Write (GW) is available for writing all bytes at one

time, regardless of the Byte Write control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High) of

the ZZ signal, or by stopping the clock (CK). Memory data is retained

during Sleep mode.

Core and Interface Voltages

The GS8160E18/32/36T operates on a 2.5 V or 3.3 V power supply.

All input are 3.3 V and 2.5 V compatible. Separate output power

circuits and are 3.3 V and 2.5 V compatible.

230

270

230

265

160

180

160

180

DDQ

3.0

5.0

6.5

GS8160E18/32/36T-250/225/200/166/150/133

) pins are used to decouple output noise from the internal

200

230

195

225

150

170

150

170

3.4

6.0

7.0

185

215

180

210

145

165

145

165

3.8

6.7

7.5

165

190

165

185

135

150

135

150

4.0

7.5

8.5

250 MHz–133 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Related parts for GS8160E32T-133

GS8160E32T-133 Summary of contents

Page 1

... Curr (x18) 175 165 160 150 Curr (x32/x36) 200 190 180 170 1/25 250 MHz–133 MHz 3.3 V I/O 3.8 4.0 ns 6.7 7.5 ns 185 165 mA 215 190 mA 180 165 mA 210 185 mA 7.5 8.5 ns 7.5 8.5 ns 145 135 mA 165 150 mA 145 135 mA 165 150 mA © 1999, GSI Technology DD ...

Page 2

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Page 5

... Output Enable; active low Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply 5/25 © 1999, GSI Technology ...

Page 6

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160E18/32/36T-250/225/200/166/150/133 GS8160E18/32/36 Block Diagram Counter Load Register D Q Register D Q Register D Q Register D Q Register D Q Register D Q Register 6/25 A Memory Array DQx1–DQx9 © 1999, GSI Technology ...

Page 7

... Note: The burst counter wraps to initial state on the 5th clock. 7/25 Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby A[1:0] A[1:0] A[1:0] A[1: BPR 1999.05.18 © 1999, GSI Technology ...

Page 8

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Page 10

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160E18/32/36T-250/225/200/166/150/133 Simplified State Diagram X Deselect First Write Burst Write CR CW 10/ First Read Burst Read BW, and GW © 1999, GSI Technology ...

Page 11

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160E18/32/36T-250/225/200/166/150/133 Simplified State Diagram with G X Deselect First Write Burst Write 11/ First Read Burst Read CR © 1999, GSI Technology ...

Page 12

... V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn 12/25 Value –0.5 to 4.6 –0.5 to 4.6 –0 +0.5 (≤ 4.6 V max.) DDQ –0 +0.5 (≤ 4.6 V max.) DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Typ. Max. Unit 3.3 3.6 V 2.5 2.7 V 3.3 3.6 V 2.5 2.7 V © 1999, GSI Technology Unit Notes ...

Page 13

... T 25 – not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn 13/25 Max. Unit Notes 0.3 V 1,3 DDQ 0.8 V 1,3 Max. Unit Notes 0.3 0.3 V 1,3 DDQ 0.3*V V 1,3 DD Max. Unit Notes ° ° © 1999, GSI Technology ...

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... Rev: 2.13 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160E18/32/36T-250/225/200/166/150/133 16/25 © 1999, GSI Technology ...

Page 17

... GSI Technology -133 Unit Min Max 7.5 — ns 4.0 ns — 1.5 — ns 1.5 ns — 1.5 — ns 0.5 ns — 8.5 — ns 8.5 ns — 3.0 — ns 3.0 ns — ...

Page 18

... Pipeline Mode Timing Deselect Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont tKL tKL tKH tKH tKC tKC ADSC initiated read and E3 only sampled with ADSC tS tKQ tOHZ tH tLZ Q(A) D(B) 18/25 Deselect Deselect Deselected with E1 tHZ Q(C) Q(C+1) Q(C+2) Q(C+3) © 1999, GSI Technology tKQX ...

Page 19

... Flow Through Mode Timing Deselect Write B Read C Read C+1 Read C+2 Read C+3 Read C tKL tKL tKC tKC Fixed High tS tH ADSC initiated read masks ADSP E1 masks ADSP tH tS tOHZ tLZ Q(A) D(B) Q(C) 19/25 Deselect tH Deselected with E1 tKQX tHZ Q(C+1) Q(C+2) Q(C+3) Q(C) © 1999, GSI Technology ...

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... All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 2.13 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160E18/32/36T-250/225/200/166/150/133 θ 0.10 0.15 1.40 1.45 0.30 0.40 0.20 — e 22.0 22.1 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — 0.10 — 7° 21/ © 1999, GSI Technology ...

Page 22

... GS8160E18T-150 GS8160E18T-133 512K x 32 GS8160E32T-250 512K x 32 GS8160E32T-225 512K x 32 GS8160E32T-200 512K x 32 GS8160E32T-166 512K x 32 GS8160E32T-150 512K x 32 GS8160E32T-133 512K x 36 GS8160E36T-250 512K x 36 GS8160E36T-225 512K x 36 GS8160E36T-200 512K x 36 GS8160E36T-166 512K x 36 GS8160E36T-150 512K x 36 GS8160E36T-133 GS8160E18T-250I ...

Page 23

... Ordering Information for GSI Synchronous Burst RAMs 1 Org Part Number 512K x 32 GS8160E32T-200I 512K x 32 GS8160E32T-166I 512K x 32 GS8160E32T-150I 512K x 32 GS8160E32T-133I 512K x 36 GS8160E36T-250I 512K x 36 GS8160E36T-225I 512K x 36 GS8160E36T-200I 512K x 36 GS8160E36T-166I 512K x 36 GS8160E36T-150I 512K x 36 GS8160E36T-133I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “ ...

Page 24

... Added 3.3 V references to entire document • Updated Operating Conditions table • Added Pin 56 to Pin Description table Content • Updated Operating Currents table and added note • Updated Application Tips paragraph • Updated table on page 1; added power numbers 24/25 Page;Revisions;Reason © 1999, GSI Technology ...

Page 25

... Updated Mb references from 16Mb to 18Mb • Updated AC Test Conditions table and removed Output Load 2 diagram • Removed pin locations from pin description table Content • Removed Preliminary banner • Updated format Format/Content • Updated timing diagrams 25/25 Page;Revisions;Reason © 1999, GSI Technology ...

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