GS8160Z18T-133 GSI Technology, GS8160Z18T-133 Datasheet
GS8160Z18T-133
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GS8160Z18T-133 Summary of contents
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Pipelined and Flow Through 100-Pin TQFP Commercial Temp Industrial Temp Features • NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization; Fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs • 2.5 ...
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... GS8160Z18T Pinout 100 DDQ DDQ DDQ V 21 ...
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GS8160Z36T Pinout 100 DDQ ...
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TQFP Pin Descriptions Symbol Type – ...
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GS8160Z18/36 NBT SRAM Functional Block Diagram Rev: 2.13a 9/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 Amps Sense Drivers Write 5/26 © 1998, Giga Semiconductor, Inc. ...
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Functional Details Clocking Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in ...
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Synchronous Truth Table Operation Type Address Deselect Cycle, Power Down D Deselect Cycle, Power Down D Deselect Cycle, Power Down D Deselect Cycle, Continue D Read Cycle, Begin Burst R Read Cycle, Continue Burst B NOP/Read, Begin Burst R Dummy ...
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Pipeline and Flow Through Read Write Control State Diagram New Read R R Burst Read B Key Input Command Code ƒ Transition Current State (n) Next State (n+1) n Clock (CK) Command Current State Current State and Next State Definition ...
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Pipeline Mode Data I/O State Diagram Intermediate B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Intermediate State (N+1) Clock (CK) Command Current State and Next State Definition for Rev: 2.13a 9/2002 Specifications cited ...
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Flow Through Mode Data I/O State Diagram B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Clock (CK) Command Current State and Next State Definition for: Rev: 2.13a 9/2002 Specifications cited are subject to ...
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Burst Cycles Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address ...
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Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, ...
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Absolute Maximum Ratings (All voltages reference Symbol V Voltage Voltage in V DDQ V Voltage on Clock Input Pin CK V I/O V Voltage on Other Input Pins IN I Input Current ...
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Power Supply Voltage Ranges Parameter 3.3 V Supply Voltage 2.5 V Supply Voltage 3 I/O Supply Voltage DDQ 2 I/O Supply Voltage DDQ Notes: 1. The part numbers of Industrial Temperature Range versions end the character ...
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Recommended Operating Temperatures Parameter Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions) Note: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case ...
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AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. ...
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Rev: 2.13a 9/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS18/36-250/225/200/166/150/133 17/26 © 1998, Giga Semiconductor, Inc. ...
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AC Electrical Characteristics Parameter Symbol Clock Cycle Time Clock to Output Valid Clock to Output Invalid tKQX Pipeline Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Clock to Output Invalid tKQX Flow ...
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Pipeline Mode Read/Write Cycle Timing CKE ADV – – Write Write COMMAND D(A2) D(A1) ...
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Pipeline Mode No-Op, Stall and Deselect Timing CKE ADV – Write D(A1) COMMAND *Note High (False ...
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Flow Through Mode Read/Write Cycle Timing CKE ADV – D(A1 Write COMMAND D(A1) *Note High ...
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Flow Through Mode No-Op, Stall and Deselect Timing CKE ADV – Write COMMAND D(A1) *Note High (False ...
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TQFP Package Drawing Symbol Description Min. Nom. Max A1 Standoff 0.05 A2 Body Thickness 1.35 b Lead Width 0.20 c Lead Thickness 0.09 D Terminal Dimension 21.9 D1 Package Body 19.9 E Terminal Dimension 15.9 E1 Package Body 13.9 e ...
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... GS8160Z36T-150 512K x 36 GS8160Z36T-133 GS8160Z18T-250I GS8160Z18T-225I GS8160Z18T-200I GS8160Z18T-166I GS8160Z18T-150I GS8160Z18T-133I 512K x 36 GS8160Z36T-250I 512K x 36 GS8160Z36T-225I 512K x 36 GS8160Z36T-200I 512K x 36 GS8160Z36T-166I 512K x 36 GS8160Z36T-150I 512K x 36 GS8160Z36T-133I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816Z36-166IT. ...
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Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; Types of Changes New Format or Content GS18/36 1.00 9/1999A;GS18/ 362.0012/1999B GS18/362.00 12/1999BGS18/ 362.01 1/2000C GS18/362.0 1/2000DGS18/ 362.03 2/2000E GS18/362.03 2/2000E; 8160Z18_r2_04 8160Z18_r2_04; 8160Z18_r2_05 8160Z18_r2_05; 8160Z18_r2_06 8160Z18_r2_06; 8160Z18_r2_07 8160Z18_r2_07; 8160Z18_r2_08 8160Z18_r2_08; ...
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Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; Types of Changes New Format or Content 8160Z18_r2_10; 8160Z18_r2_11 8160Z18_r2_11; 8160Z18_r2_12 8160Z18_r2_12; 8160Z18_r2_13 Rev: 2.13a 9/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36T-250/225/200/166/150/133 Page;Revisions;Reason ...