GS74116TP-10I GSI Technology, GS74116TP-10I Datasheet

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GS74116TP-10I

Manufacturer Part Number
GS74116TP-10I
Description
10ns 256K x 16 4Mb asynchronous SRAM
Manufacturer
GSI Technology
Datasheet
SOJ, TSOP, FP-BGA
Commercial Temp
Industrial Temp
Features
• Fast access time: 8, 10, 12, 15ns
• CMOS low power operation: 170/145/130/110 mA at min.cycle time.
• Single 3.3V ± 0.3V power supply
• All inputs and outputs are TTL compatible
• Byte control
• Fully static operation
• Industrial Temperature Option: -40° to 85°C
• Package line up
Description
The GS74116 is a high speed CMOS static RAM organized as
262,144-words by 16-bits. Static design eliminates the need for exter-
nal clocks or timing strobes. Operating on a single 3.3V power supply
and all inputs and outputs are TTL compatible. The GS74116 is avail-
able in a 7.2x11.65 mm Fine Pitch BGA package, 400 mil SOJ and
400 mil TSOP Type-II packages.
Pin Descriptions
Rev: 2.02 3/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
J: 400mil, 44 pin SOJ package
TP: 400mil, 44 pin TSOP Type II package
U: 7.20mm x 11.65mm Fine Pitch Ball Grid Array package
DQ
Symbol
A
0
1
WE
V
V
CE
UB
OE
NC
to A
to DQ
LB
DD
SS
17
16
Lower byte enable input
Upper byte enable input
4Mb Asynchronous SRAM
Output enable input
+3.3V power supply
Write enable input
Chip enable input
Data input/output
(DQ9 to DQ16)
Address input
(DQ1 to DQ8)
Description
No connect
Ground
256K x 16
1/14
SOJ 256K x 16 Pin Configuration
Fine Pitch BGA 256K x 16 Bump Configuration
DQ6
DQ7
DQ
DQ
DQ
DQ
DQ
DQ
V
V
A
WE
A
A
A
A
CE
DD
A
A
A
A
A
SS
12
15
14
13
16
4
3
2
1
0
1
2
3
4
5
8
A
B
C
D
E
F
G
H
7.2x11.65mm 0.75mm Bump Pitch
DQ
DQ
DQ
V
V
DQ
NC
LB
1
DD
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
16
14
11
9
DQ
DQ
DQ
DQ
A
OE
NC
UB
2
12
15
13
12
10
Top view
Top View
44 pin
SOJ
A
A
A
NC
A
A
A
A
3
17
10
13
0
3
5
8
© 1999, Giga Semiconductor, Inc.
A
A
A
A
A
A
A
A
4
16
11
14
1
4
6
7
9
Center V
GS74116TP/J/U
DQ
DQ
DQ
DQ
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
WE
A
27
26
25
24
23
CE
A
8, 10, 12, 15ns
5
15
2
2
4
5
7
DQ
DQ
V
DQ
DQ
V
NC
NC
DD
6
SS
A
A
A
OE
UB
LB
DQ
DQ
DQ
DQ
V
V
DQ
DQ
DQ
DQ
NC
A
A
A
A
A
3.3V V
DD
1
3
6
8
5
6
7
SS
DD
8
9
10
11
17
16
15
14
13
12
11
10
9
& V
DD
SS
N

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GS74116TP-10I Summary of contents

Page 1

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 256K x 16 SOJ 256K x 16 Pin Configuration DQ6 DQ7 DQ Fine Pitch BGA 256K x 16 Bump Configuration Description Address input (DQ1 to DQ8) (DQ9 to DQ16) Ground No connect 1/14 GS74116TP/J/U 8, 10, 12, 15ns Center ...

Page 2

... A14 Row Memory Array Decoder Address Input Buffer Column Decoder I/O Buffer Control DQ 1 2/14 GS74116TP/J ...

Page 3

... High High Z Symbol Rating V -0.5 to +4 4.6V max OUT ( 4.6V max.) PD 0.7 T -55 to 150 STG 3/14 GS74116TP/J Current Not Selected ISB , ISB 1 2 Read High Z Read Write I DD Not Write, High Z Write High Z High Z Unit ...

Page 4

... Max V = =0V 7 OUT Test Conditions Min -1uA IN DD Output High Z -1uA OUT 4mA 2 4mA LO 4/14 GS74116TP/J/U Max Unit 3 Unit pF pF Max 1uA 1uA 0.4V © 1999, Giga Semiconductor, Inc. N ...

Page 5

... IH 70mA 65mA 60mA 0.2V DD 30mA Conditions V =2. =0.4V IL tr=1V/ns tf=1V/ns 1.4V 1.4V Fig. 1& 5/14 GS74116TP/J/U -40 to 85°C 15ns 10ns 12ns 15ns 110mA 155mA 140mA 120mA 55mA 75mA 70mA 65mA 40mA Output Load VT=1.4V Output Load 2 3.3V 589 DQ 1 434 5pF © 1999, Giga Semiconductor, Inc. ...

Page 6

... --- --- --- 0 t OLZ * 0 --- 0 t BLZ * --- 4 --- --- 3.5 --- t OHZ * --- 3.5 --- t BHZ , UB and Previous Data 6/14 GS74116TP/J/U -10 -12 -15 Max Min Max Min Max --- 12 --- 15 --- 10 --- 12 --- 15 10 --- 12 --- 15 4 --- 5 --- 6 4 --- 5 --- 6 --- 3 --- 3 --- --- 3 --- 3 --- --- 0 --- 0 --- --- 0 --- 0 --- ...

Page 7

... Min tWC 8 --- 10 tAW 5.5 --- 7 tCW 5.5 --- 7 tBW 5.5 --- 7 tDW 4 --- 5 tDH 0 --- 0 tWP 5.5 --- 7 tAS 0 --- 0 tWR 0 --- 0 tWR1 0 --- --- 3 tWLZ * --- 3.5 --- tWHZ 7/14 GS74116TP/J/U tHZ tBHZ tOHZ Data valid -12 -15 Max Min Max Min Max --- 12 --- 15 --- --- 8 --- 10 --- --- 8 --- 10 --- --- 8 --- 10 --- --- 6 --- 7 --- --- 0 --- 0 --- --- 8 --- 10 --- --- 0 --- 0 --- ...

Page 8

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. tWC tAW tCW tBW tAS tWP tDW Data valid tWHZ High impedance tWC tAW tAS tCW tBW tWP tDW tDH Data valid High impedance 8/14 GS74116TP/J/U tWR tDH tWLZ tWR1 © 1999, Giga Semiconductor, Inc. N ...

Page 9

... Write Cycle 3: UB, LB control Address Data In Data Out Rev: 2.02 3/2000 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. tWC tAW tAS tCW tBW tWP tDW tDH Data valid High impedance 9/14 GS74116TP/J/U tWR1 © 1999, Giga Semiconductor, Inc. N ...

Page 10

... Detail Note: 1. Dimension D& not include interlead flash 2. Dimension B1 does not include dambar protrusion / intrusion 10/14 GS74116TP/J/U Dimension in inch Dimension in mm min nom max min nom - - 0.148 - - 0.025 - - 0.635 - 0.105 0.110 0.115 2.667 2.794 - 0.018 ...

Page 11

... Detail A Note: 1. Dimension D& not include interlead flash 2. Dimension B does not include dambar protrusion / intrusion 3. Controlling dimension: mm 11/14 GS74116TP/J/U Dimension in inch Dimension in mm min nom max min nom max - - 0.047 - - 1.20 0.002 - - 0.05 - 0.037 0.039 0.041 0.95 1.00 1.05 0.01 0.014 0.018 ...

Page 12

... Index Rev: 2.02 3/2000 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com Top View Side View aaa Bottom View 12/14 GS74116TP/J/U Symbol Unit 1.10 0.10 · A1 0.22 0.05 b 0.35 c 0.36(TYP) D 11.65 0.10 D1 5.25 E 7.20 0.10 E1 3.75 e ...

Page 13

... GS74116TP-8 400 mil TSOP-II GS74116TP-10 400 mil TSOP-II GS74116TP-12 400 mil TSOP-II GS74116TP-15 400 mil TSOP-II GS74116TP-8I 400 mil TSOP-II GS74116TP-10I 400 mil TSOP-II GS74116TP-12I 400 mil TSOP-II GS74116TP-15I 400 mil TSOP-II GS74116J-8 400 mil SOJ GS74116J-10 400 mil SOJ GS74116J-12 ...

Page 14

... Format/Typos None 1. Added Fine Pitch BGA package to datasheet. Content 2. 10/Added Dimension “D” to SOJ package diagram/Was missing 3. 11/Added Dimension “D” to TSOP package diagram/Was missing 1. GSI Logo Format/Content 2. 1. Changed Pin A17 from 3E to 3D. Content 14/14 GS74116TP/J/U © 1999, Giga Semiconductor, Inc. N ...

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