GS84032AT-100 GSI Technology, GS84032AT-100 Datasheet

GS84032AT-100

Manufacturer Part Number

GS84032AT-100

Description

100MHz 12ns 128K x 32 4Mb sync burst SRAM

Manufacturer

GSI Technology

Datasheet

1.GS84032AT-100.pdf (31 pages)

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TQFP, BGA

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipelined

• Single Cycle Deselect (SCD) operation

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipelined mode

• Byte Write (BW) and/or Global Write (GW) operation

• Common data inputs and data outputs

• Clock control, registered, address, data, and control

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC standard 100-lead TQFP or 119-Bump BGA package

Functional Description

Applications

The GS84018/32/36A is a 4,718,592-bit (4,194,304-bit for

x32 version) high performance synchronous SRAM with a 2-

bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications ranging from DSP main store

to networking chip set support. The GS84018/32/36A is

available in a JEDEC standard 100-lead TQFP or 119-Bump

BGA package.

Controls

Addresses, data I/Os, chip enables (E

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

Rev: 1.12 7/2002

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

operation

Through

Pipeline

3-1-1-1

2-1-1-1

Flow

tCycle

185 mA

115 mA

5.5 ns

3.0 ns

9.1 ns

–180

8 ns

256K x 18, 128K x 32, 128K x 36

170 mA

105 mA

6.0 ns

3.5 ns

8.5 ns

10 ns

–166

, E

4Mb Sync Burst SRAMs

, E

155 mA

100 mA

6.6 ns

3.8 ns

10 ns

12 ns

–150

), address burst

105 mA

80 mA

4.5 ns

10 ns

12 ns

15 ns

–100

1/31

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin/bump (pin 14 in the TQFP and

bump 5R in the BGA). Holding the FT mode pin/bump low

places the RAM in Flow Through mode, causing output data to

bypass the Data Output Register. Holding FT high places the

RAM in Pipelined mode, activating the rising-edge-triggered

Data Output Register.

SCD Pipelined Reads

The GS84018/32/36A is an SCD (Single Cycle Deselect)

pipelined synchronous SRAM. DCD (Dual Cycle Deselect)

versions are also available. SCD SRAMs pipeline deselect

commands one stage less than read commands. SCD RAMs

begin turning off their outputs immediately after the deselect

command has been captured in the input registers.

Byte Write and Global Write

Byte write operation is performed by using byte write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS84018/32/36A operates on a 3.3 V power supply and

all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate

output power (V

from the internal circuit.

GS84018/32/36AT/B-180/166/150/100

DDQ

) pins are used to de-couple output noise

3.3 V and 2.5 V I/O

180 MHz–100 MHz

Preliminary

3.3 V V

Related parts for GS84032AT-100

GS84032AT-100 Summary of contents

Page 1

TQFP, BGA Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipelined operation • Single Cycle Deselect (SCD) operation • 3.3 V +10%/–5% core power supply • ...

Page 2

GS84018A 100-Pin TQFP Pinout 100 DDQ ...

Page 3

GS84032A 100-Pin TQFP Pinout 100 DDQ ...

Page 4

GS84036A 100-Pin TQFP Pinout 100 DDQ ...

Page 5

TQFP Pin Description Pin Location 37, 36 35, 34, 33, 32, 100, 99, 82, 81,44, 45, 46, 47, 48, 49 52, 53, 56, 57, 58, 59, 62, 63 68, 69, 72, 73, 74, 75, 78 ...

Page 6

GS84018A Pad Out Rev: 1.12 7/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com 119-Bump BGA—Top View 1 ...

Page 7

GS84032A Pad Out Rev: 1.12 7/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com 119-Bump BGA—Top View 1 ...

Page 8

GS84036A Pad Out Rev: 1.12 7/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com 119-Bump BGA—Top View 1 ...

Page 9

BGA Pin Description Pin Location N4, P4 A2, A3, A5, A6, B3, B5, C2, C3, C5, C6, R2, R6, T3 T2, T6 T2, T6 K7, K6, L7, L6, M6, N7, N6 H7, H6, G7, G6, F6, ...

Page 10

GS84018/32/36A Block Diagram Register A0– LBO ADV CK ADSC ADSP Power Down ZZ Control Note: Only x36 version ...

Mode Pin Functions Mode Name Burst Order Control Output Register Control Power Down Control Note: There are pull-up devices on LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected ...

Page 12

Synchronous Truth Table Address Operation Used Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst External Read Cycle, Continue Burst Read Cycle, Continue ...

Page 13

Simplified State Diagram Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low. 2. The upper portion of the diagram assumes active use of only the Enable (E and that ADSP is ...

Page 14

Simplified State Diagram with G Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use Use of “Dummy Reads” (Read Cycles with G High) may be used to make ...

Page 15

Absolute Maximum Ratings (All voltages reference Symbol Description V Voltage on V Pins Voltage in V Pins DDQ DDQ V Voltage on Clock Input Pin CK V Voltage on I/O Pins I/O V ...

Page 16

Undershoot Measurement and Timing 50% V -2.0V SS 20% tKC Capacitance 3 Parameter Control Input Capacitance Input Capacitance Output Capacitance ...

Page 17

AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. ...

Page 18

Operating Currents Parameter Test Conditions Device Selected; Operating All other inputs Current Output open Standby ZZ V – DD Current 0.2 V Device Deselected; Deselect All other inputs Current Rev: ...

Page 19

AC Electrical Characteristics Parameter Clock Cycle Time Clock to Output Valid Pipeline Clock to Output Invalid Clock to Output in Low-Z Clock Cycle Time Clock to Output Valid Flow Through Clock to Output Invalid Clock to Output in Low-Z Clock ...

Page 20

Write Cycle Timing Single Write ADSP ADSC ADV –An 0 WR1 – Hi-Z DQ –DQ A ...

Page 21

Flow Through Read Cycle Timing Single Read ADSP ADSC ADV –An RD1 – tOLZ DQ ...

Page 22

Flow Through Read-Write Cycle Timing Single Read ADSP ADSC ADV tS tH A0–An RD1 – tOE G tKQ Hi-Z DQ ...

Page 23

Pipelined SCD Read Cycle Timing Single Read ADSP ADSC ADV –A RD1 – Hi-Z DQ –DQ A ...

Page 24

Pipelined SCD Read-Write Cycle Timing Single Read ADSP ADSC ADV tS tH A0–An RD1 – Hi-Z DQ –DQ A ...

Page 25

Sleep Mode Timing Diagram ADSP ADSC ZZ Application Tips Single and Dual Cycle Deselect SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers ...

Page 26

GS84018/32/36A Output Driver Characteristics 60 Pull Down Drivers -20 -40 Pull Up Drivers -60 -80 -0.5 0 0.5 3. Rev: 1.12 7/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com ...

Page 27

TQFP Package Drawing Symbol Description Min. Nom. Max A1 Standoff 0.05 A2 Body Thickness 1.35 b Lead Width 0.20 c Lead Thickness 0.09 D Terminal Dimension 21.9 D1 Package Body 19.9 E Terminal Dimension 15.9 E1 Package Body 13.9 e ...

Page 28

Package Dimensions—119-Pin BGA A Pin 1 Corner P N Top View Side View Rev: 1.12 7/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com GS84018/32/36AT/B-180/166/150/100 Bottom View Package Dimensions—119-Pin BGA ...

Page 29

... GS84018AT-166I 256K x 18 GS84018AT-150I 256K x 18 GS84018AT-100I 128K x 32 GS84032AT-180I 128K x 32 GS84032AT-166I 128K x 32 GS84032AT-150I 128K x 32 GS84032AT-100I 128K x 36 GS84036AT-180I 128K x 36 GS84036AT-166I 128K x 36 GS84036AT-150I 128K x 36 GS84036AT-100I 256K x 18 GS84018AB-180 256K x 18 GS84018AB-166 256K x 18 ...

Page 30

... GS84036AB-100I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS84032AT-8T. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. ...

Page 31

Revision History Types of Changes Rev. Code: Old; Format or Content New GS84018/32/36 Rev 1.02c 5/1999; GS84018/32/36A 1.00First Release 8/1999D GS84018/32/36A1.00 8/ 1999;GS84018/32/36A1.01 9/ 1999E GS84018/32/36A1.01 9/ 1999E;GS84018/32/36A1.02 GS84018/32/36A1.0210-11/ 1999;GS84018/32/36A1.032/ 2000G GS84018/32/36A1.032/2000G; 84018A_r1_04 84018A_r1_04; 84018A_r1_05 84018A_r1_05; 84018A_r1_06 84018A_r1_06; 84018A_r1_07 84018A_r1_07; ...

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