SST27SF020-70-3C-WH Silicon Storage Technology, Inc, SST27SF020-70-3C-WH Datasheet

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SST27SF020-70-3C-WH

Manufacturer Part Number
SST27SF020-70-3C-WH
Description
Many-time programmable flash
Manufacturer
Silicon Storage Technology, Inc
Datasheet

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SST27SF020-70-3C-WHE
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11 277
FEATURES:
• Organized as 32K x8 / 64K x8 / 128K x8 / 256K x8
• 4.5-5.5V Read Operation
• Superior Reliability
• Low Power Consumption
• Fast Read Access Time
PRODUCT DESCRIPTION
The SST27SF256/512/010/020 are a 32K x8 / 64K x8 /
128K x8 / 256K x8 CMOS, Many-Time Programmable
(MTP) low cost flash, manufactured with SST’s proprietary,
high performance SuperFlash technology. The split-gate
cell design and thick oxide tunneling injector attain better
reliability and manufacturability compared with alternate
approaches. These MTP devices can be electrically erased
and programmed at least 1000 times using an external pro-
grammer with a 12 volt power supply. They have to be
erased prior to programming. These devices conform to
JEDEC standard pinouts for byte-wide memories.
Featuring
SST27SF256/512/010/020 provide a Byte-Program time of
20 µs. Designed, manufactured, and tested for a wide
spectrum of applications, these devices are offered with an
endurance of at least 1000 cycles. Data retention is rated at
greater than 100 years.
The SST27SF256/512/010/020 are suited for applications
that require infrequent writes and low power nonvolatile
storage. These devices will improve flexibility, efficiency,
and performance while matching the low cost in nonvolatile
applications that currently use UV-EPROMs, OTPs, and
mask ROMs.
To meet surface mount and conventional through hole
requirements, the SST27SF256/512 are offered in 32-pin
PLCC, 32-pin TSOP , and 28-pin PDIP packages. The
SST27SF010/020 are offered in 32-pin PDIP , 32-pin PLCC
and 32-pin TSOP packages. See Figures 1, 2, and 3 for
pinouts.
©2001 Silicon Storage Technology, Inc.
S71152-02-000 5/01
1
– Endurance: At least 1000 Cycles
– Greater than 100 years Data Retention
– Active Current: 20 mA (typical)
– Standby Current: 10 µA (typical)
– 70 ns
– 90 ns
SST27SF256 / 512 / 010 / 0205.0V-Read 256Kb / 512Kb / 1Mb / 2Mb (x8) MTP flash memories
high
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit (x8)
performance
Many-Time Programmable Flash
502
Byte-Program,
the
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
• Fast Byte-Program Operation
• Electrical Erase Using Programmer
• TTL I/O Compatibility
• JEDEC Standard Byte-wide EPROM Pinouts
• Packages Available
Device Operation
The SST27SF256/512/010/020 are a low cost flash solu-
tion that can be used to replace existing UV-EPROM, OTP ,
and mask ROM sockets. These devices are functionally
(read and program) and pin compatible with industry stan-
dard EPROM products. In addition to EPROM functionality,
these devices also support electrical erase operation via an
external programmer. They do not require a UV source to
erase, and therefore the packages do not have a window.
Read
The Read operation of the SST27SF256/512/010/020 is
controlled by CE# and OE#. Both CE# and OE# have to be
low for the system to obtain data from the outputs. Once
the address is stable, the address access time is equal to
the delay from CE# to output (T
output after a delay of T
assuming that CE# pin has been low and the addresses
have been stable for at least T
is high, the chip is deselected and a typical standby current
of 10 µA is consumed. OE# is the output control and is
used to gate data from the output pins. The data bus is in
high impedance state when either CE# or OE# is high.
Byte-Program Operation
The SST27SF256/512/010/020 are programmed by using
an external programmer. The programming mode for
SST27SF256/010/020 is activated by asserting 12V (±5%)
– Byte-Program Time: 20 µs (typical)
– Chip Program Time:
– Does not require UV source
– Chip-Erase Time: 100 ms (typical)
– 32-pin PLCC
– 32-pin TSOP (8mm x 14mm)
– 28-pin PDIP for SST27SF256/512
– 32-pin PDIP for SST27SF010/020
0.7 seconds (typical) for SST27SF256
1.4 seconds (typical) for SST27SF512
2.8 seconds (typical) for SST27SF010
5.6 seconds (typical) for SST27SF020
These specifications are subject to change without notice.
MTP is a trademark of Silicon Storage Technology, Inc.
OE
from the falling edge of OE#,
CE
CE
- T
). Data is available at the
OE
. When the CE# pin
Data Sheet

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SST27SF020-70-3C-WH Summary of contents

Page 1

... Kbit / 512 Kbit / 1 Mbit / 2 Mbit (x8) Many-Time Programmable Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 SST27SF256 / 512 / 010 / 0205.0V-Read 256Kb / 512Kb / 1Mb / 2Mb (x8) MTP flash memories FEATURES: • Organized as 32K x8 / 64K x8 / 128K x8 / 256K x8 • 4.5-5.5V Read Operation • Superior Reliability – Endurance: At least 1000 Cycles – ...

Page 2

... The Product Identification mode identifies the devices as pin the SST27SF256, SST27SF512, SST27SF010 and SST27SF020 and manufacturer as SST. This mode may be accessed by the hardware method. To activate this mode for SST27SF256/010/020, the programming equip- ment must force (5V±10 SST27SF512, the programming equipment must force V (12V± ...

Page 3

... Control Logic UNCTIONAL LOCK IAGRAM OF THE Address Buffer CE# OE PGM for SST27SF020 for SST27SF010 ©2001 Silicon Storage Technology, Inc. SST27SF256 X-Decoder SST27SF512 X-Decoder SST27SF010/020 X-Decoder Control Logic 3 SuperFlash Memory Y-Decoder I/O Buffers 502 ILL B1 ...

Page 4

... DQ0 DQ0 DQ0 FIGURE SSIGNMENTS FOR ©2001 Silicon Storage Technology, Inc. 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 SST27SF256 32-pin PLCC ...

Page 5

... Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet SST27SF020 SST27SF010 SST27SF512 SST27SF256 A11 A11 A11 A11 A13 A13 A13 A13 A14 A14 A14 A14 A17 PGM# PGM ...

Page 6

... A = Most significant address for SST27SF256, A for SST27SF512 ©2001 Silicon Storage Technology, Inc. 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 for SST27SF010, and Data Sheet for SST27SF020 S71152-02-000 5/01 T2.3 502 502 ...

Page 7

... IH Standby Chip-Erase Program/Erase Inhibit Product Identification Device ID = A5H for SST27SF010 and A6H for SST27SF020 Most significant address for SST27SF010 and Note 12V±5 12V±5% PPH H ©2001 Silicon Storage Technology, Inc. ...

Page 8

... Output Low Voltage OL V Output High Voltage OH I Supervoltage Current for A H ©2001 Silicon Storage Technology, Inc. 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 AC C ONDITIONS OF Input Rise/Fall Time . . . . . . . . . . . Output Load . . . . . . . . . . . . . . . . . C 12V±5% Output Load ...

Page 9

... Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet TABLE ROGRAM RASE V =5.0V±10 Symbol Parameter I V Erase or Program Current Erase or Program Current Input Leakage Current LI I Output Leakage Current ...

Page 10

... Output Hold from Address Change OH 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2001 Silicon Storage Technology, Inc. 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 OWER ...

Page 11

... Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet TABLE 14 ROGRAM RASE YCLE Symbol Parameter T Address Setup Time AS T Address Hold Time Pulse Rise Time PRT Setup Time VPS Hold Time ...

Page 12

... V PPH ART FIGURE HIP RASE IMING ©2001 Silicon Storage Technology, Inc. 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 OLZ T OH DATA VALID T CLZ D SST27SF256/512/010/020 IAGRAM FOR T EW ...

Page 13

... Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet ADDRESS (EXCEPT CE# DQ 7-0 V PPH OE#/ PRT V PPH ART FIGURE EAD YCLE IMING ADDRESS (EXCEPT CE# OE 7-0 V PPH ...

Page 14

... V PPH V DD OE#/ FIGURE YTE ROGRAM IMING ©2001 Silicon Storage Technology, Inc. 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 ADDRESS VALID DATA VALID T VPS T PRT D SST27SF256 IAGRAM FOR ADDRESS VALID T AH ...

Page 15

... Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet ADDRESS CE# OE 7-0 HIGH-Z V PPH PGM# FIGURE 10 YTE ROGRAM IMING ©2001 Silicon Storage Technology, Inc. ADDRESS VALID DATA VALID T VPS ...

Page 16

... FIGURE 12 EST OAD XAMPLE ©2001 Silicon Storage Technology, Inc. 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 V HT REFERENCE POINTS V LT (0.4 V) for a logic “0”. Measurement reference points for ILT (0.8 V). Input rise and fall times (10% LT ...

Page 17

... Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet FIGURE 13 HIP RASE LGORITHM FOR ©2001 Silicon Storage Technology, Inc. Start PPH Erase 100ms pulse (CE ...

Page 18

... FIGURE 14 HIP RASE LGORITHM FOR ©2001 Silicon Storage Technology, Inc. 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Start OE#/ PPH Erase 100ms pulse (CE OE#/ Wait for OE#/V PP and ...

Page 19

... Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet FIGURE 15 HIP RASE LGORITHM FOR ©2001 Silicon Storage Technology, Inc. Start PPH CE OE Erase 100ms pulse (PGM PGM ...

Page 20

... See Figure 13 FIGURE 16 YTE ROGRAM LGORITHM FOR ©2001 Silicon Storage Technology, Inc. 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Start Erase PPH Address = First Location Program 20µs pulse (CE Last Address ...

Page 21

... Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet Increment Address No * See Figure 14 FIGURE 17 YTE ROGRAM LGORITHM FOR ©2001 Silicon Storage Technology, Inc. Start Erase* OE#/ PPH Address = First Location Program 20µs pulse (CE ...

Page 22

... See Figure 15 FIGURE 18 YTE ROGRAM LGORITHM FOR ©2001 Silicon Storage Technology, Inc. 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Start Erase PPH (PGM Last Address? Yes Read Device Compare all bytes to original data ...

Page 23

... Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet Device Speed Suffix1 SST27SFxxx - XXX - XX ©2001 Silicon Storage Technology, Inc. Suffix2 - XX Package Modifier pins pins Numeric = Die modifier Package Type N = PLCC W = TSOP (die up) (8mm x 14mm) ...

Page 24

... SST27SF010-70-3C-NH SST27SF010-70-3C-WH SST27SF010-90-3C-NH SST27SF010-90-3C-WH Valid combinations for SST27SF020 SST27SF020-70-3C-NH SST27SF020-70-3C-WH SST27SF020-90-3C-NH SST27SF020-90-3C-WH Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2001 Silicon Storage Technology, Inc. ...

Page 25

... Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 Data Sheet PACKAGING DIAGRAMS TOP VIEW .485 .495 .447 Optional .453 Pin #1 Identifier .042 .048 .042 .048 .585 .547 .595 .553 .050 BSC. Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. ...

Page 26

... ACKAGE ODE Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 ©2001 Silicon Storage Technology, Inc. 256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 1.445 1.455 .170 .200 .120 ...

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