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B69030 Summary of contents
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Dual HiQVideo Accelerator with 4MB Embedded Memory Databook Revision 1.3 November 1999 `efmp ...
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... Copyright Notice Copyright 1999 Intel Corporation Chips and Technologies, Inc. has been integrated into the Platform Components Group (PCG) of Intel Corporation. ALL RIGHTS RESERVED. This manual is copyrighted by Intel Corporation. You may not reproduce, transmit, transcribe, store in a retrieval system, or translate into any language or computer language, in any form or by any means - electronic, mechanical, magnetic, optical, chemical, manual, or otherwise - any part of this publication without the express written permission of Intel Corporation ...
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Dual HiQVideo 4MB Embedded Memory Embedded SDRAM memory • embedded memory • 83 MHz SDRAM operation Dual Independent Display • Different or same display image CRT/TV and Flat Panel • Independent display timing and resolution for CRT/TV ...
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... VPE Software Utilities • DebugVGA • Auto testing of all video modes • ChipsVGA • ChipsEXT Software Documentation • BIOS OEM Reference Guide • Display Driver User’s Guide • Utilities User’s Guide • Release Notes for BIOS, Drivers, and ...
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Revision History Revision Date 0.5 8/14/98 0.6 10/1/98 1.0 03/22/99 1.1 07/16/99 1.2 11/15/99 1.3 11/24/99 `efmp 69030 Databook By Comments BB/bjb First Draft - Official Release Under NDA. BB/bjb Removed appendices - update Chapter 2. BB/dam Incorporated Engineering ...
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... M69030 Pin Diagram, Top View .................................................................................................. 2-3 M69030 Pin Diagram, Bottom View ............................................................................................ 2-4 B69030 and M69030 PCI/AGP Bus Interface ............................................................................. 2-5 B69030 and M69030 Configuration Pins and ROM Interface ..................................................... 2-8 B69030 and M69030 Flat Panel Display Interface ...................................................................... 2-9 B69030 and M69030 CRT Interface .......................................................................................... 2-12 B69030 and M69030 Video Interface ........................................................................................ 2-13 B69030 and M69030 Miscellaneous Pins ...
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Chapter 5 I/O and Memory Address Maps Introduction .................................................................................................................................. 5-1 VGA-Compatible Address Map ................................................................................................... 5-1 Address Maps for Going Beyond VGA ........................................................................................ 5-2 Lower Memory Map ..................................................................................................................... 5-2 I/O and Sub-Addressed Register Map ........................................................................................ 5-2 Sub-Indexing Indices and Data ...
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Chapter 9 CRT Controller Registers Introduction .................................................................................................................................. 9-1 CRX CRT Controller Index Register ....................................................................... 9-2 CR00 Horizontal Total Register ................................................................................ 9-3 CR01 Horizontal Display Enable End Register ........................................................ 9-3 CR02 Horizontal Blanking Start Register ................................................................. 9-4 CR03 Horizontal Blanking End ...
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Chapter 10 Sequencer Registers Introduction ................................................................................................................................ 10-1 SRX Sequencer Index Register ............................................................................ 10-2 SR00 Reset Register ............................................................................................. 10-2 SR01 Clocking Mode Register ............................................................................... 10-3 SR02 Plane Mask Register .................................................................................... 10-4 SR03 Character Map Select Register .................................................................... 10-5 SR04 Memory ...
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Chapter 14 Extension Registers Introduction ................................................................................................................................ 14-1 XRX Extension Register Index Register ...............................................................14-3 XR00 Vendor ID Low Register ............................................................................... 14-3 XR01 Vendor ID High Register .............................................................................. 14-4 XR02 Device ID Low Register ................................................................................ 14-4 XR03 Device ID High Register ............................................................................... ...
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Chapter 14 Extension Registers (Continued) XRC7 Dot Clock 1 Divisor Select Register ........................................................... 14-46 XRC8 Dot Clock 2 VCO M-Divisor Register ......................................................... 14-48 XRC9 Dot Clock 2 VCO N-Divisor Register .......................................................... 14-48 XRCB Dot Clock 2 Divisor Select Register ...
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Chapter 15 Flat Panel Registers (Continued) FR35 FP Vertical Overflow 1 Register ................................................................. 15-34 FR36 FP Vertical Overflow 2 Register ................................................................. 15-35 FR37 FP VSync (FLM) Disable Register .............................................................15-35 FR40 Horizontal Compensation Register ............................................................ 15-36 FR41 Horizontal Stretching Register ...................................................................15-38 ...
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Chapter 16 Multimedia Registers (Continued) MR2B/AB Playback Window X-LEFT High Register ................................................... 16-23 MR2C/AC Playback Window X-RIGHT Low Register ................................................. 16-24 MR2D/AD Playback Window X-RIGHT High Register ................................................ 16-24 MR2E/AE Playback Window Y-TOP Low Register ..................................................... 16-25 MR2F/AF Playback ...
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Appendix A Display Modes Introduction ................................................................................................................................. A-1 Appendix B Clock Generation Introduction ................................................................................................................................. B-1 Clock Synthesizer ....................................................................................................................... B-1 Dot Clock (DCLK) ....................................................................................................................... B-1 Memory Clock (MCLK) ............................................................................................................... B-1 PLL Parameters ......................................................................................................................... B-2 Programming the Clock Synthesizer .......................................................................................... B-3 DCLK Programming ...
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Appendix E BitBLT Operation Introduction ..................................................................................................................................E-1 Color Depth Configuration and Color Expansion ........................................................................E-2 Graphics Data Size Limitations ...................................................................................................E-3 Bit-Wise Operations ....................................................................................................................E-3 Per-Pixel Write Masking ..............................................................................................................E-7 When the Source and Destination Locations Overlap .................................................................E-8 Contiguous vs. Discontiguous Graphics Data ...........................................................................E-12 ...
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List of Figures Figure 1-1: Dual-Pipe Simultaneous Mode ..................................................................................... 1-1 Figure 1-2: Independent Images .................................................................................................... 1-2 Figure 1-3: Virtual Desktop ............................................................................................................. 1-2 Figure 3-1: AC Test Timing ............................................................................................................ 3-3 Figure 3-2: Reference Clock Timing ............................................................................................... 3-4 Figure 3-3: Reset Timing ...
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... List of Tables Table 2-1: Pin Diagram, B69030 Ball Grid Array (Top View) ....................................................... 2-1 Table 2-2: Pin Diagram, B69030 Ball Grid Array (Bottom View).................................................. 2-2 Table 2-3: Pin Diagram, M69030 Mini Ball Grid Array (Top View) ............................................... 2-3 Table 2-4: Pin Diagram, M69030 Mini Ball Grid Array (Bottom View).......................................... 2-4 Table 3-1: Absolute Maximum Conditions ................................................................................... 3-1 Table 3-2: Normal Operating Conditions ...
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List of Tables (Continued) Table 7-1: PCI Configuration Registers ....................................................................................... 7-1 Table 8-1: General Control and Status Registers ........................................................................ 8-1 Table 9-1: CRT Controller Registers............................................................................................ 9-1 Table 10-1: Sequencer Registers .............................................................................................. 10-1 Table 11-1: Graphics Controller Registers ................................................................................. 11-1 ...
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Chapter 1 Introduction / Overview The 69030 graphics accelerator is the newest product in the family of portable graphic accelerators that embeds 4 megabytes of high performance Synchronous Dynamic Random Access Memory (SDRAM) technology for the graphics frame buffer. Based ...
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Dual-Pipe Mosaic Mode • Independent Images - Two completely different images on each display - Each display can be configured at its optimum resolution/timing Panel 8x6x24 @ 60 Hz • Virtual Desktop - Single desktop spans across two displays ...
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... Capture of input data may also be double buffered for smoothing and to prevent image tearing resulting from the display of an unfinished captured frame or field picture. To `efmp 69030 Databook Introduction / Overview TM = technology. Based on the CHIPS 1-3 Revision 1.3 11/24/99 ...
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VPE kernal transport mode and video capture/playback auto flipping the 69030 graphics accelerator provides a hardware interrupt pin, which can be programmed to activate at either display vertical sync or video capture vertical sync signal. To better ...
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... Chapter 2 Pin Descriptions Introduction Chapter 2 describes the pin configuration for the B69030 and M69030 Dual HiQVideo Accelerators. B69030 Pin Diagram, Top View Table 2-1: Pin Diagram, B69030 Ball Grid Array (Top View CFG4 CFG2 N/C N/C N/C N/C N/C 19 CFG6 CFG5 CFG1 N/C N/C N/C N/C N/C CFG7 ...
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... B69030 Pin Diagram, Bottom View Table 2-2: Pin Diagram, B69030 Ball Grid Array (Bottom View RSVD VP10 VP6 VP1 N/C N/C N/C 19 VP14 VP11 VP9 VP5 VP2 N/C N/C VCLK VP15 VP13 VP8 VP4 VP0 N P33 HREF PCLK VP12 VP7 VP3 MEMGND MEMVCC ...
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M69030 Pin Diagram, Top View Table 2-3: Pin Diagram, M69030 Mini Ball Grid Array (Top View N/C N/C N/C N/C N/C 16 N/C N/C N/C N/C N/C 15 TMD0 N/C N/C MEM MEM 14 GND ...
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M69030 Pin Diagram, Bottom View Table 2-4: Pin Diagram, M69030 Mini Ball Grid Array (Bottom View RMA16 RMA17 VP2 N/C VP3 15 VP1 VP8 VP5 VP0 VP6 14 VP9 VP12 VP10 VP4 VP13 ...
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... B69030 and M69030 PCI/AGP Bus Interface BGA mBGA Pin Name Type Active Powered Pin Pin C1 E4 RESET BUSCLK PAR I FRAME IRDY TRDY# S/ STOP# S/TS Note: S/TS stands for “Sustained Tri-state”. These signals are driven by only one device at a time, are driven high for one clock before released, and are not driven for at least one cycle after being released by the previous device ...
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... B69030 and M69030 PCI/AGP Bus Interface (continued) BGA mBGA Pin Name Type Active Powered Pin Pin L4 J5 DEVSEL# S/ PERR# S/ SERR INT# OD Note: S/TS stands for “Sustained Tri-state”. These signals are driven by only one device at a time, are driven high for one clock before released, and are not driven for at least one cycle after being released by the previous device ...
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... B69030 and M69030 PCI/AGP Bus Interface (continued) BGA mBGA Pin Type Active Pin Pin Name U2 P1 AD0 I AD1 I AD2 I AD3 I AD4 I AD5 I AD6 I AD7 I AD8 I AD9 I AD10 I AD11 I AD12 ...
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... B69030 and M69030 Configuration Pins and ROM Interface BGA mBGA Pin Name Type Active Powered Pin Pin D18 A13 CFG0 In C19 E12 CFG1 In B20 F12 CFG2 In C18 A12 CFG3 In A20 B13 CFG4 In B19 C12 CFG5 In A19 D12 CFG6 In B18 F11 CFG7 ...
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... B69030 and M69030 Flat Panel Display Interface BGA mBGA Pin Name Type Pin Pin Out Out Out Out Out Out Out Out Out Out W9 R7 P10 Out Y9 M8 P11 Out V10 ...
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... B69030 and M69030 Flat Panel Display Interface (continued) BGA mBGA Pin Name Pin Pin Y5 T4 SHFCLK W5 L7 FLM (CL1)(DE) (BLANK#) OUT (DE) (BLANK ENAVDD W4 T3 ENAVEE (ENABKL ENABKL Notes: To accommodate a wide variety of panel types, the graphics controller has been designed to output its data in any of a number of formats ...
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... B69030 and M69030 Flat Panel Display Interface (continued) Mono Mono Mono Color TFT Pin 9/12/16 8-bit 8-bit 16 bit Name bit P0 D0 UD3 UD7 UD2 UD6 UD1 UD5 UD0 UD4 LD3 UD3 LD2 UD2 LD1 UD1 ...
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... B69030 and M69030 CRT Interface BGA mBGA Pin Name Pin Pin U3 K7 HSYNC (CSYNC VSYNC Y3 K6 RED V4 P4 GREEN W3 T2 BLUE W2 T1 RSET V3 R2 DDC DATA (GPIO2 DDC CLK (GPIO3) `efmp 69030 Databook Pin Descriptions Type Active Powered ...
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... B69030 and M69030 Video Interface BGA mBGA Pin Name Type Active Powered Pin Pin V16 T12 VREF W17 M13 HREF Y18 R13 VCLK V17 N12 PCLK (DCLKOUT) Out R18 N15 VP0 U20 T15 VP1 T19 P16 VP2 R17 M16 VP3 T18 ...
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... B69030 and M69030 Miscellaneous Pins BGA mBGA Pin Name Type Active Powered Pin Pin E4 C3 STNDBY REFCLK (MCLKIN DCLKIN B1 E5 MCLKIN V1 N3 GPIO0 (ACTI GPIO1 (32KHz) U16 P13 Reserved D6 A5 Reserved (DCLKOUT2) D17 A14 TMD0 A12 B8 TMD1 `efmp ...
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... B69030 and M69030 Power and Ground Pins BGA mBGA Pin Name Pin Pin U5 R3 DACVCC Analog power for the internal RAMDAC DACGND Analog ground for the internal RAMDAC MCKVCC Analog power and ground pins for the A2 A2 MCKGND internal memory clock synthesizer (MCLK) ...
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... B69030 and M69030 Power and Ground Pins (continued CORVCC Digital power for the graphics controller internal logic (a.k.a., the “core” VCC). W12 D14 J10 MEMGND Embedded memory ground. G17 D14 P17 E14 F14 G15 H15 J15 M9 P3 RGND Internal reference GND, should be tied to GND. ...
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... B69030 and M69030 Reserved and No Connection Pins BGA mBGA Pin Name PIN PIN A1 B1 Reserved Y20 A10 C8 No Connection A11 C13 A18 D13 B11 E13 B17 F13 C11 B14 C16 C14 C20 A15 D10 B15 D11 C15 D19 ...
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... Chapter 3 Electrical Specifications Introduction Chapter 3 describes the Electrical Specifications for the B69030 and M69030 Dual HiQVideo Accelerator. Table 3-1: Absolute Maximum Conditions Symbol Parameter V Supply Voltage CC V Input Voltage I T Storage Temperature STG Note: Permanent device damage may occur if Absolute Maximum Rating are exceeded. ...
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Table 3-4: DC Characteristics. Symbol Parameter Power Dissipation Input Leakage Current IL I Output Leakage Current OZ V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage ...
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Table 3-6: AC Test Conditions: Symbol Parameter V Supply Voltage CC V All AC parameters TEST V Input low voltage (10 Input high voltage (90 Maximum input rise time (3.3/5V) ...
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Table 3-7: AC Timing Characteristics - Reference Clock Symbol Parameter F Reference Frequency REF T Reference Clock Period REF T /T Reference Clock Duty Cycle HI REF Reference Clock Input Figure 3-2: Reference Clock Timing Table 3-8: AC Timing ...
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Initial Power-Up Reset IPR 14.318 MHz STNDBY# RESET# Configuration Inputs CFG0-15 Table 3-10: AC Timing Characteristics - PCI Bus Frame (CLK=33MHz) Symbol Parameter T FRAME# Setup to CLK FRS T C/BE#[3:0] (Bus CMD) Setup to CLK CMS ...
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CLK 1 T Hi-Z FRS FRAME CMS Hi-Z C/BE#[3:0] Command T T ADS Read Hi-Z Address AD[31: ADS Write Hi-Z Address AD[31:0] Hi-Z Bus TRDY# Turnaround Hi-Z Bus IRDY# Turnaround Hi-Z Bus DEVSEL# Turnaround Table ...
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EPROMs. Timing specifications and performance of BIOS ROM memory accesses are non-critical since PCI BIOS ROM data is always shadowed into high-speed system memory prior to execution of BIOS code. 7 CLK CLK ...
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VCLK VP0 -VP15 HREF VREF SHFCLK T DOVD DE, P[23..0] T COVD LP, FLM Table 3-15: AC Timing Characteristics - A.G. Timing Parameters Symbol Parameter Output Timing T AD[0] (Data) Valid from CLK DAD T TRDY# High ...
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Table 3-15: AC Timing Characteristics - A.G. Timing Parameters (Continued) T DEVSEL# Active from CLK DZL T DEVSEL# Inactive from CLK DLH T DEVSEL# High before High Z DHZ T STOP# High Z to High from CLK SZH ...
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... Chapter 4 Mechanical Specifications Introduction Figure 4-1 and 4-2 illustrates the Mechanical Specifications of the B69030 and M69030 Dual HiQVideo Accelerator respectively. Top View 27 ± 0.1 mm (1.063 ± 0.004" Bottom View 27 ± 0.1 mm (1.063 ± 0.004" ...
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BSC 1.00 +/- 0.10mm Figure 4-2: 256 Ball - Mini Ball Grid Array `efmp 69030 Databook Mechanical Specifications 17.00 +/- .20mm ...
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Chapter 5 I/O and Memory Address Maps Introduction An extensive set of registers normally controls the graphics system. These registers are a combination of registers defined by IBM when the Video Graphics Array (VGA) was first introduced, and others that ...
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Address Maps for Going Beyond VGA This graphics controller improves upon VGA by providing additional features that are used through numerous additional registers. Many of these additional registers are simply added to the sub-indexing schemes already defined in the ...
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Table 5-2: I/O and Sub-Addressed Register Map (Continued) 3C1 400781 & C00781 3C2 400784 & C00784 3C3 3C4 400788 & C00788 3C5 400789 & C00789 3C6 40078C & C0078C 3C7 40078D & C0078D 3C8 400790 & C00790 3C9 400791 & ...
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Sub-Indexing Indices and Data Ports Table 5-3: Sub-Indexing Indices and Data Ports Index Port Data Port Addresses Addresses I/O 3B4/3D4 I/O 3B5/3D5 Mem 0x400768/7A8 Mem 0x400769/7A9 I/O 3C4 I/O 3C5 Mem 0x400788 Mem 0x400789 I/O 3CE I/O 3CF Mem ...
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Register Shadowing Schemes for Dual-Pipe To answer the need to create two pixel pipelines that are both compatible with the VGA standard, a scheme involving a combination of “sharing” and “shadowing” of registers accessed via the I/O space is used. ...
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Table 5-4: I/O Space Register Shadowing Shadowed for Pipeline A FCR bits 7-6 and 3-2 of MSR bit 7 of ST00 ST01 CR00 to CR70 no equivalent here SR01 bit 0 of GR06 AR00 to AR14 DACMASK DACSTATE DACRX ...
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Table 5-4: I/O Space Register Shadowing (Continued) MR43-MR44 bits 7-6 and 4-0 of MR9E (playback engine 2) MR9F-MRC2 (playback engine 2) Memory Space Register Shadowing When the graphics controller is used in dual-pipe mosaic mode with newer operating systems, it ...
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MR02 to MR1A Video Data Capture Registers MR1E to MR42 Pipeline A Video Pri. Playback Playback Registers Engine 1 MR9E to MRC2 Pipeline A Sec. Playback Registers Pipeline A MR Register Shadow As shown, there is one set of ...
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Two-Way Sub-Indexed Register Indices Using the previously described I/O and memory space shadowing schemes possible to access the 8- bit registers (IOSS, MSS, FCR, MSR, ST00, ST01, ARxx, CRxx, FRxx, GRxx, MRxx, XRxx, and DAC registers) in three ...
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Upper Memory Map -- Dual-Pipe Mapping Table 5-5: Upper Memory Map -- Dual-Pipe Mapping Size 4MB 8MB 64KB 2KB Pipeline A 4MB 62KB 64KB 3968KB 4MB 8MB 64KB 2KB Pipeline B 4MB 62KB 64KB 3968KB Upper Memory Map -- ...
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Chapter 6 Register Summaries Introduction The Tables in Chapter 6 contain Register Summaries for the 69030 Dual HiQVideo Accelerator. Table 6-1: PCI Configuration Registers Configuration Name Space Offset 00 VENDID 02 DEVID 04 DEVCTL 06 DEVSTAT 08 REV 09 PRG ...
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Table 6-2: General Control & Status Registers Name IOSS I/O Space Shadowing Register MSS Memory Space Shadowing Register ST00 VGA Input Status Register 0 ST01 VGA Input Status Register 1 FCR VGA Feature Control Register MSR VGA Miscellaneous Output ...
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Table 6-3: CRT Controller Registers Name CR00 Horizontal Total Register CR01 Horizontal Display Enable End Register CR02 Horizontal Blanking Start Register CR03 Horizontal Blanking End Register CR04 Horizontal Sync Start Register CR05 Horizontal Sync End Register CR06 Vertical Total Register ...
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Table 6-4: Sequencer Register Name SR00 SR01 Clocking Mode Register SR02 Map Mask Register SR03 Character Map Select Register SR04 Memory Mode Register SR07 Horizontal Character Counter Reset Register Table 6-5: Graphics Controller Registers Name Register Function GR00 Set/Reset ...
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Table 6-7: Palette Registers Name PALMASK PALSTATE PALRX Palette Read Index Register PALWX Palette Write Index Register PALDATA Table 6-8: Extension Register Name Register Function XR00 Vendor ID Low Register XR01 Vendor ID High Register XR02 Device ID Low Register ...
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Table 6-8: Extension Register (Continued) XRA6 Cursor 1 Y-Position Low Register XRA7 Cursor 1 Y-Position High Register XRA8 Cursor 2 Control Register XRA9 Cursor 2 Vertical Extension Register XRAA Cursor 2 Base Address Low Register XRAB Cursor 2 Base ...
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Table 6-9: Flat Panel Registers Name FR00 Pipeline Feature Register FR01 PIpeline Enable & Timing Select Register FR02 Output Enable & Assignment Register FR03 Output Blanking Register FR04 Panel Power Sequencing Delay Register FR05 Miscellaneous Control Register FR06 Output Disable ...
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Table 6-10: Multimedia Registers Name Register Function MR00 Module Capability Register MR01 Secondary Capability Register MR02 Capture Control 1 Register MR03 Capture Control 2 Register MR04 Capture Control 3 Register MR05 Capture Control 4 Register MR06-08 Capture Memory Address ...
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Table 6-11: BitBLT Registers Name BR00 Source and Destination Offset Register BR01 Pattern/Source Expansion Background Color Register BR02 Pattern/Source Expansion Foreground Color Register BR03 Monochrome Source Control Register BR04 BitBLT Control Register BR05 Pattern Address Register BR06 Source Address Register ...
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Chapter 7 PCI Configuration Registers Introduction The Tables in Chapter 7 contain the PCI Configuration Registers for the 69030 Dual HiQVideo Accelerator. Table 7-1: PCI Configuration Registers Configuration Name Space Offset 00 VENDID 02 DEVID 04 DEVCTL 06 DEVSTAT 08 ...
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VENDID Vendor ID Register read-only at PCI configuration offset 00h byte or word accessible accessible only via PCI configuration cycles 15-0 Vendor ID This is the vendor ID assigned by the PCI Special ...
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DEVCTL Device Control Register read/write at PCI configuration offset 04h byte or word accessible accessible only via PCI configuration cycles Reserved (0000:00) 15-10 Reserved Each of these bits always return a value of 0 ...
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VGA Palette Snoop 0: Accesses to all VGA I/O locations including those for the palette will be claimed. All read and write accesses to the palette will be performed normally. This is the default after reset. 1: Accesses ...
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DEVSTAT Device Status Register read/write at PCI configuration offset 06h byte or word accessible accessible only via PCI configuration cycles Det Signal Rcvd Rcvd Signal DEVSEL# Parity System Master Target Target Error Error Abort ...
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DEVSEL# Timing These two bits specify the longest-possible amount of time that this graphics controller will take in decoding an address and asserting DEVSEL#. These two bits always return a value of 01, indicating a medium-length timing. 8 ...
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REV Revision ID Register read-only at PCI configuration offset 08h byte accessible accessible only via PCI configuration cycles Chip Manufacturing Code (xxxx) Note: This register is identical to the Revision ID Register (XR04). 7-4 Chip Manufacturing Code ...
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SUB Sub-Class Code Register read-only at PCI configuration offset 0Ah byte accessible accessible only via PCI configuration cycles 7-0 Sub-Class Code This register always returns a value of 00h to identify this PCI device as a ...
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HDR Header Type Register read-only at PCI configuration offset 0Eh byte accessible accessible only via PCI configuration cycles Single/Multi Function Dev (0) 7 Single/Multiple Function Device This bit always returns a value of 0 when read, indicating ...
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MBASE Memory Base Address Register read/write at PCI configuration offset 10h byte, word, or doubleword accessible accessible only via PCI configuration cycles Memory Space Base Address (0000:0000 ...
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SUBVENDID Subsystem Vendor ID Register read-only at PCI configuration offset 2Ch byte or word accessible accessible only via PCI configuration cycles 15-0 Subsystem Vendor ID These bits are intended to carry the vendor ID ...
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INTLINE Interrupt Line Register read/write at PCI configuration offset 3Ch byte accessible accessible only via PCI configuration cycles 7-0 Interrupt Line This register carries the level number of the interrupt line to which the interrupt output ...
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RBASE ROM Base Address Register read/write at PCI configuration offset 30h byte, word, or doubleword accessible accessible only via PCI configuration cycles ROM Space Base Address 31-18 ROM ...
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SUBVENDSET Subsystem Vendor ID Set Register read/write at PCI configuration offset 6Ch byte or word accessible accessible only via PCI configuration cycles 15-0 Subsystem Vendor ID Set These bits are used to program ...
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General Control and Status Registers Chapter 8 General Control and Status Registers Introduction Chapter 8 describes the General Control and Status Registers for the 69030 Dual HiQVideo Accelerator. These are direct-access registers. They are NOT read from or written to ...
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General Control and Status Registers ST00 Input Status Register 0 read-only at I/O Address 3C2h partially shared and partially shadowed between both pipelines A and B as shown PIpe A Vert A Ret Interrupt Reserved PIpe ...
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General Control and Status Registers ST01 Input Status Register 1 read-only at I/O Address 3BAh/3DAh shadowed between both pipelines A and VSYNC A Reserved Video Feedback 1,0 Output VSYNC B Reserved Video Feedback 1,0 Output 7 ...
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General Control and Status Registers FCR Feature Control Register write at I/O Address 3BAh/3DAh read at I/O Address 3CAh shadowed between both pipelines A and Reserved B Reserved 7-4 Reserved These bits return the ...
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General Control and Status Registers MSR Miscellaneous Output Register write at I/O Address 3C2h read at I/O Address 3CCh partially shared and partially shadowed between both pipelines A and B as shown PIpe A Sync Output Pol ...
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General Control and Status Registers 3-2 Clock Select These two bits select the dot clock. Bit Selected Clock 3 2 CLK0 -- default 25MHz 0 0 (for standard VGA modes with a horizontal resolution of 320 or 640 pixels. ...
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General Control and Status Registers IOSS I/O Space Shadowing Register read/write at I/O address 3CDh shared between both pipelines A and Reserved & (000) B Note: Regardless of the setting of ANY bit in THIS ...
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General Control and Status Registers 4 Sub-indexed Register Index Write Enable This bit defaults to the value of 0 after reset. For the FCR, MSR, MSS, ST00 and ST01 registers: Since these are direct-access and not sub-indexed registers, this ...
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General Control and Status Registers 2 I/O Space Register Read Select This bit defaults to the value of 0 after reset. For the FCR, MSR, MSS, ST00 and ST01 registers: 0: All of these direct-access registers that either belong to ...
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General Control and Status Registers 1-0 I/O Space Register Write Select and Read-Mode Control These bits default to the value of 0 after reset. For the FCR, MSR, MSS, ST00 and ST01 registers: Bit All ...
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General Control and Status Registers For the CR, FR, GR, MR, SR and XR sub-indexed register groups: Bit Note: Which pipeline’s indices for these sub-indexed register groups are used in ...
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General Control and Status Registers For the AR and DAC sub-indexed register groups: Bit Note: Write access to the indices for these two sub-indexed register groups must be enabled ...
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General Control and Status Registers MSS Memory Space Shadowing Register read/write at I/O address 3CBh shared by both pipelines A and Reserved & (0000) B 7-4 Reserved These bits always return the value of 0 ...
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Chapter 9 CRT Controller Registers Introduction The CRT controller registers are accessed by writing the index of the desired register into the CRT Controller Index Register at I/O address 3B4h or 3D4h (depending upon whether the graphics system is configured ...
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CRX CRT Controller Index Register read/write at I/O address 3B4h/3D4h This register is cleared to 00h by reset. shadowed for pipelines A and 7-0 CRT Controller Register Index These 8 bits are used ...
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CR00 Horizontal Total Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 00h shadowed for pipelines A and 7-0 Horizontal Total These bits provide either all 8 bits of an ...
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CR02 Horizontal Blanking Start Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 02h shadowed for pipelines A and 7-0 Horizontal Blanking Start This register is used to specify ...
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CR03 Horizontal Blanking End Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 03h shadowed for pipelines A and Display Enable Skew A Reserved Control Display Enable Skew B Reserved Control 7 ...
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CR04 Horizontal Sync Start Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 04h shadowed for pipelines A and 7-0 Horizontal Sync Start This register is used to specify ...
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CR05 Horizontal Sync End Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 05h shadowed for pipelines A and Hor Blnk A Horizontal Sync Delay End Bit 5 Hor Blnk B Horizontal ...
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CR06 Vertical Total Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 06h shadowed for pipelines A and 7-0 Vertical Total Bits These bits provide the 8 least significant ...
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CR07 Overflow Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 07h shadowed for pipelines A and Vert Sync Vert Disp En Vert Total A Start Bit 9 Bit 9 Bit 9 ...
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Vertical Total Bit 9 The vertical total is a 10-bit or 12-bit value that specifies the total number of scanlines. This includes the scanlines both inside and outside of the active display area. In standard VGA modes, where ...
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Vertical Blanking Start Bit 8 The vertical blanking start is a 10-bit or 12-bit value that specifies the beginning of the vertical blanking period relative to the beginning of the active display area. In standard VGA modes, where bit ...
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Vertical Display Enable End Bit 8 The vertical display enable end is a 10-bit or 12-bit value that specifies the number of the last scanline within the active display area. In standard VGA modes, where bit 0 of ...
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CR08 Preset Row Scan Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 08h shadowed for pipelines A and Reserved Left Hor Pixel Shift B Reserved Left Hor Pixel Shift 7 ...
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CR09 Maximum Scanline Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 09h shadowed for pipelines A and Double Line Cmp Vert Blnk A Scanning Bit 9 Start Bit 9 Double ...
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Vertical Blanking Start Bit 9 The vertical blanking start is a 10-bit or 12-bit value that specifies the beginning of the vertical blanking period relative to the beginning of the active display area. In standard VGA modes, where bit ...
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CR0A Text Cursor Start Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 0Ah shadowed for pipelines A and Text Cursor A Reserved Off Text Cursor B Reserved Off This cursor ...
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CR0B Text Cursor End Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 0Bh shadowed for pipelines A and Reserved Text Cursor Skew B Reserved Text Cursor Skew This cursor is ...
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CR0C Start Address High Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 0Ch shadowed for pipelines A and 7-0 Start Address Bits 15-8 This register provides bits 15 ...
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CR0D Start Address Low Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 0Dh shadowed for pipelines A and 7-0 Start Address Bits 7-0 This register provides the eight least ...
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CR0E Text Cursor Location High Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 0Eh shadowed for pipelines A and This cursor is the text cursor that is part ...
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CR10 Vertical Sync Start Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 10h shadowed for pipelines A and 7-0 Vertical Sync Start Bits 7-0 This register provides the 8 ...
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CR11 Vertical Sync End Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 11h shadowed for pipelines A and Protect Vert Int A Reserved Regs 0-7 Enable Protect Vert Int B ...
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CR12 Vertical Display Enable End Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 12h shadowed for pipelines A and 7-0 Vertical Display Enable End Bits 7-0 This register provides ...
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CR14 Underline Location Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 14h shadowed for pipelines A and Dword A Reserved Count By 4 Mode Dword B Reserved Count By 4 ...
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Count The memory address counter is incremented either every character clock or every other character clock, depending upon the setting of bit 3 of the CRT Mode Control Register. 1: The memory address counter is incremented ...
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CR15 Vertical Blanking Start Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 15h shadowed for pipelines A and 7-0 Vertical Blanking Start Bits 7-0 This register provides the ...
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CR17 CRT Mode Control read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 17h shadowed for pipelines A and CRT Ctrl Word or Address A Reset Byte Mode Wrap CRT Ctrl Word or ...
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Count The memory address counter is incremented either every character clock or every 4 character clocks, depending upon the setting of bit 5 of the Underline Location Register. 1: The memory address counter is incremented ...
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Bits Generated by the Memory Address Counter (MAOut0 to MAOut15) Byte Mode Word Mode CR14 bit 6=0 CR14 bit 6=0 CR17 bit 6=1 CR17 bit 6=0 CR17 bit 5=X CR17 bit 5=1 MAOut0 MAOut15 MAOut1 MAOut0 MAOut2 MAOut1 MAOut3 MAOut2 ...
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CR18 Line Compare Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 18h shadowed for pipelines A and 7-0 Line Compare Bits 7-0 This register provides the 8 least ...
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CR30 Extended Vertical Total Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 30h shadowed for pipelines A and Reserved B Reserved 7-4 Reserved These bits should always be written with ...
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CR31 Extended Vertical Display End Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 31h shadowed for pipelines A and Reserved B Reserved 7-4 Reserved These bits should always be ...
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CR32 Extended Vertical Sync Start Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 32h shadowed for pipelines A and Reserved B Reserved 7-4 Reserved These bits should always be written ...
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CR33 Extended Vertical Blanking Start Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 33h shadowed for pipelines A and Reserved B Reserved 7-4 Reserved These bits should always be ...
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CR38 Extended Horizontal Total Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 38h shadowed for pipelines A and 7-1 Reserved These bits should always be written with the value ...
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CR3C Extended Horizontal Blanking End Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 3Ch 7 6 Horizontal Blank End A Bits 7 and 6 (00) Horizontal Blank End B Bits 7 and 6 (00) ...
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CR40 Extended Start Address Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 40h shadowed for pipelines A and Pipe A Strt Reserved A Addr En (0) (000) Pipe B Strt Reserved ...
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CR41 Extended Span Register read/write at I/O address 3B5h/3D5h with 3B4h/3D4h set to index 41 shadowed for pipelines A and Reserved B Reserved 7-4 Reserved Whenever this register is written to, these bits should ...
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CR71 NTSC/PAL Video Output Control Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 71h shadowed only for pipeline NTSC/ PAL Pedestal Blanking B Sel Enable Delay Ctrl 7 NTSC/PAL Select ...
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CR72 NTSC/PAL Horizontal Serration 1 Start Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 72h shadowed only for pipeline 7-0 Horizontal Serration 1 Start These 8 bits specify ...
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CR74 NTSC/PAL Horizontal Pulse Width Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 74h shadowed only for pipeline Reserved Round Off 7-6 Reserved 5 NTSC/PAL Horizontal Pulse Width Round ...
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CR75 NTSC/PAL Filtering Burst Read Length Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 75h shadowed only for pipeline Reserved (Writable) B (xxxx) 7-4 Reserved These bits should always ...
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CR77 NTSC/PAL Filtering Control Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 77h shadowed only for pipeline Text Mode Reserved (Writable) B Line Halving (0) (000) 7 VGA Text Mode ...
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CR78 NTSC/PAL Vertical Reduction Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 78h shadowed only for pipeline Vertical Reserved Reserved B Redux En (0) (0) 7 Vertical Reduction Enable 0: ...
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CR79 NTSC/PAL Horizontal Total Fine Adjust Register read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 79h shadowed only for pipeline Reserved (Writable) B (0000:0) 7-3 Reserved 2-0 Horizontal Total Fine Adjust These ...
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Chapter 10 Sequencer Registers Introduction The Sequencer Registers are accessed by writing the index of the desired register into the VGA Sequencer Index Register (SRX) at I/O address 3C4, and then accessing the desired register through the data port for ...
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SRX Sequencer Index Register read/write at I/O address 3C4h This register is cleared to 00h by reset Reserved 7-3 Reserved 2-0 Sequencer Register Index These three bits are used to select any one of the sequencer ...
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SR01 Clocking Mode Register read/write at I/O address 3C5h with index at address 3C4h set to 01h shadowed for pipelines A and Reserved Screen Off B Reserved Screen Off 7-6 Reserved 5 Screen Off 0: ...
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SR02 Plane Mask Register read/write at I/O address 3C5h with index at address 3C4h set to 02h shared by both pipelines A and & Reserved B Note: This register is referred to in the ...
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SR03 Character Map Select Register read/write at I/O address 3C5h with index at address 3C4h set to 03h shared by both pipelines A and Char Map A & Reserved Select (bit 0) B Note: In ...
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Character Map Select Bits for Character Map B These three bits are used to select the character map (character generator tables used as the primary character set (font). Note that the numbering of the maps ...
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SR04 Memory Mode Register read/write at I/O address 3C5h with index at address 3C4h set to 04h shared by both pipelines A and & Reserved B 7-4 Reserved 3 Chain 4 Mode 0: The manner ...
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SR07 Horizontal Character Counter Reset Register read/write at I/O address 3C5h with index at address 3C4h set to index 07h shared by both pipelines A and & B Writing this register with any data ...
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Chapter 11 Graphics Controller Registers Introduction The Graphics Controller Registers are accessed by writing the index of the desired register into the VGA Graphics Controller Index Register (GRX) at I/O address 3CE, then accessing the desired register through the data ...
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GRX Graphics Controller Index Register read/write at I/O address 3CEh this register is cleared to 00h by reset Reserved 7-4 Reserved 3-0 Graphics Controller Register Index These four bits are used to select any one of ...
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GR01 Enable Set/Reset Register read/write at I/O address 3CFh with index at address 3CEh set to 01h shared by both pipelines A and & Reserved B 7-4 Reserved 3-0 Enable Set/Reset Plane 3 through Enable ...
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GR03 Data Rotate Register read/write at I/O address 3CFh with index at address 3CEh set to 03h shared by both pipelines A and & Reserved B 7-5 Reserved 4-3 Function Select These bits specify the ...
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GR04 Read Plane Select Register read/write at I/O address 3CFh with index at address 3CEh set to 04h shared by both pipelines A and & B 7-2 Reserved 1-0 Read Plane Select These two bits ...
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GR05 Graphics Mode Register read/write at I/O address 3CFh with index at address 3CEh set to 05h shared by both pipelines A and & Reserved Shift Register Control B 7 Reserved 6-5 Shift Register ...
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This alternating pattern is meant to accommodate the use of the Odd/Even mode of organizing the 4 memory planes, which is used by standard VGA modes 2h and 3h Four bits of data at a time from parallel ...
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Read Mode 0: During a CPU read from the frame buffer, the value returned to the CPU is data from the memory plane selected by bits 1 and 0 of the Read Plane Select Register (GR04). 1: During ...
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GR06 Miscellaneous Register read/write at I/O address 3CFh with index at address 3CEh set to 06h shared by both pipelines A and B (except bit 0, which is shadowed for pipelines A and & Reserved ...
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GR07 Color Don’t Care Register read/write at I/O address 3CFh with index at address 3CEh set to 07h shared by both pipelines A and & Reserved B 7-4 Reserved 3-0 Ignore Color Plane 3 ...
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Chapter 12 Attribute Controller Registers Introduction Unlike the other sets of indexed registers, the Attribute Controller Registers are not accessed through a scheme employing entirely separate index and data ports. I/O address 3C0h is used both as the read and ...
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ARX Attribute Controller Index Register read/write at I/O address 3C0h Video Reserved Enable Note: AR12 is referred to in the VGA standard as the Color Plane Enable Register. The words “plane,” “color plane,” “display memory plane,” ...
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AR10 Mode Control Register read at I/O address 3C1h, write at I/O address 3C0h with index at address 3C0h set to 10h shadowed for pipelines A and Palette Bits Pixel Pixel Width/ A P5, P4 Panning ...
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Enable Line Graphics Character Code 0: Every 9th pixel of a horizontal line (i.e., the last pixel of each horizontal line of each 9- pixel wide character box) is assigned the same attributes as the background of the ...
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AR11 Overscan Color Register read at I/O address 3C1h, write at I/O address 3C0h with index at address 3C0h set to 11h shadowed for pipelines A and 7-0 Overscan These 8 bits select the ...
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AR12 Memory Plane Enable Register read at I/O address 3C1h, write at I/O address 3C0h with index at address 3C0h set to 12h shadowed for pipelines A and Reserved Video Status Mux B Reserved ...
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AR13 Horizontal Pixel Panning Register read at I/O address 3C1h, write at I/O address 3C0h with index at address 3C0h set to 13h shadowed for pipelines A and Reserved B Reserved 7-4 Reserved 3-0 Horizontal ...
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AR14 Color Select Register read at I/O address 3C1h, write at I/O address 3C0h with index at address 3C0h set to 14h shadowed for pipelines A and Reserved B Reserved 7-4 Reserved 3-2 Palette ...
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Chapter 13 Palette Registers Introduction The original VGA graphics system and earlier compatible ones had a distinct IC called either the RAMDAC or the palette DAC. The RAMDAC was made up of two main components: a 256x24bit color lookup table ...
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Accessing Color Data Locations Within the Palette A complex sub-indexing scheme using separate read and write access indices and a data port is used to access both the standard and alternate palette locations within the palette where color data ...
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PALMASK Palette Data Mask Register read/write at I/O address 3C6h shadowed for pipelines A and 7-0 Pixel Data Mask In indexed-color mode, the 8 bits of this register are logically ANDed with the 8 ...
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PALRX Palette Read Index Register write-only at I/O address 3C7h shadowed for pipelines A and 7-0 Palette Read Index This 8-bit value is an index that selects 1 of the 256 standard locations ...
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PALDATA Palette Data Register read/write at I/O address 3C9h shadowed for pipelines A and 7-0 Palette Data Register This byte-wide data port provides read or write access to the three bytes of data carried ...
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Chapter 14 Extension Registers Introduction Chapter 14 describes the Extension Registers for the 69030 Dual HiQVideo Accelerator. Table 14-1: Extension Registers Name Register Function XR00 Vendor ID Low Register XR01 Vendor ID High Register XR02 Device ID Low Register XR03 ...
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Table 14-1: Extension Registers (Continued) XRAA Cursor 2 Base Address Low Register XRAB Cursor 2 Base Address High Register XRAC Cursor 2 X-Position Low Register XRAD Cursor 2 X-Position High Register XRAE Cursor 2 Y-Position Low Register XRAF Cursor ...
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... A & B 7-0 Vendor ID Bits 7-0 These 8 bits always carry the value 2Ch. This is the lower byte of CHIPS vendor ID for PCI devices. Both bytes of this ID are also readable from the Vendor ID register at offset 00h in the PCI configuration space. `efmp 69030 Databook Extension Registers ...
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... A & B 7-0 Vendor ID Bits 15-8 These 8 bits always carry the value 10h. This is the upper byte of CHIPS vendor ID for PCI devices. Both bytes of this ID are also readable from the Vendor ID register at offset 00h in the PCI configuration space. XR02 Device ID Low Register read-only at I/O address 3D7h with index at I/O address 3D6h set to 02h ...
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XR03 Device ID High Register read-only at I/O address 3D7h with index at I/O address 3D6h set to 03h shared by both pipelines A and & B 7-0 Device ID High These bits always carry ...
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... Memory Space Base Address Bit 23 This bit is provided only for backward compatibility only hold-over from earlier CHIPS graphics controllers. The graphics controller requires a 16MB memory space on the host bus through which the linear frame buffer and memory-mapped registers are accessed. This 16MB memory space always begins on a 16MB address boundary, so bit 23 of the linear base address of this 16MB memory space always has the value of 0 ...
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XR08 Host Bus Configuration Register read-only at I/O address 3D7h with index at I/O address 3D6h set to 08h shared by both pipelines A and & B 7-2 Reserved These bits always return the value ...
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XR09 I/O Control Register read/write at I/O address 3D7h with index at I/O address 3D6h set to 09h shadowed for pipelines A and 7-1 Reserved These bits always return the value of 0 ...
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XR0A Frame Buffer Mapping Register read/write at I/O address 3D7h with index at I/O address 3D6h set to 0Ah shared by both pipelines A and Reserved Endian Byte Swapping & B (00) 7-6 Reserved These ...
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Frame Buffer Linear Mapping Enable 0: Disables the linear mapping of the frame buffer. 1: Enables the linear mapping of the frame buffer. 0 Frame Buffer Page Mapping Enable 0: Disables the mapping of the frame buffer in ...
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XR0B PCI Burst Write Support Register read/write at I/O address 3D7h with index at I/O address 3D6h set to 0Bh shared by both pipelines A and Reserved A & B (0000) 7-4 Reserved These bits always ...
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XR0E Frame Buffer Page Select Register read/write at I/O address 3D7h with index at I/O address 3D6h set to 0Eh shared by both pipelines A and Reserved & ( Reserved This bit ...
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XR20 BitBLT Configuration Register read/write at I/O address 3D7h with index at I/O address 3D6h set to 20h shared by both pipelines A and Reserved & B (00) 7-6 Reserved These bits always have the ...
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XR40 Memory Access Control Register read/write at I/O address 3D7h with index at I/O address 3D6h set to 40h shadowed for pipeline A and Reserved (Writable) A Reserved (Writable) B 7-2 Reserved (Writable) These bits ...
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XR60 Video Pin Control Register read/write at I/O address 3D7h with index at I/O address 3D6h set to 60h shared by both pipelines A and Reserved PCLK Pin & Source B (0) (0) 7 Reserved ...
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XR61 DPMS Sync Control Register read/write at I/O address 3D7h with index at I/O address 3D6h set to 61h shared by both pipelines A and Reserved DPMS DPMS A VSYNC HSYNC & B (0) (0) ...
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XR62 GPIO Pin Control Register read/write at I/O address 3D7h with index at I/O address 3D6h set to 62h shared by both pipelines A and Reserved Reserved & B (00) Note: See the FP Pin Control ...
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XR63 GPIO Pin Data Register read/write at I/O address 3D7h with index at I/O address 3D6h set to 63h shared by both pipelines A and Reserved Reserved & (00 Reserved 6-5 Reserved ...
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XR67 Pin Tri-State Control Register read/write at I/O address 3D7h with index at I/O address 3D6h set to 67h shared by both pipelines A and & B 7-2 Reserved These bits always return the value ...
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XR70 Configuration Pins 0 Register read-only at I/O address 3D7h with index at I/O address 3D6h set to 70h shared by both pipelines A and CFG7 CFG6 CFG5 & (x) (x) (x) B The ...