VT8231 ETC-unknow, VT8231 Datasheet

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VT8231

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VT8231
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ETC-unknow
Datasheet

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VT8231 Summary of contents

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.4330.9 ...

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WK http://www.viatech.com ...

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... Updated pinouts to conform to engineering pinout revision 0.4 dated 10/6/99 Updated feature bullets and performed partial edit of Overview text Updated pinouts per engineering pinout rev 0.6 / pinlist rev 0.2 dated 10/20/99 Updated Electrical Specs and added “output drive” and “input voltage” tables -i- VT8231 Initials ...

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... IDE-Controller-Specific Confiiguration Registers ................................................................................................................................ 71 IDE I/O Registers.................................................................................................................................................................................. 76 Function 2 Registers - USB Controller Ports 0-1 ............................................................................................................... 77 PCI Configuration Space Header .......................................................................................................................................................... 77 USB-Specific Configuration Registers.................................................................................................................................................. 78 USB I/O Registers................................................................................................................................................................................. 79 Function 3 Registers - USB Controller Ports 2-3 ............................................................................................................... 80 PCI Configuration Space Header .......................................................................................................................................................... 80 USB-Specific Configuration Registers.................................................................................................................................................. 81 USB I/O Registers................................................................................................................................................................................. 82 Preliminary Revision 0.8 October 29, 1999 T C ABLE OF ONTENTS -ii- VT8231 Table of Contents ...

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... Legacy Power Management Timers .................................................................................................................................................... 123 System Primary and Secondary Events ............................................................................................................................................... 123 Peripheral Events ................................................................................................................................................................................ 123 ELECTRICAL SPECIFICATIONS............................................................................................................................................. 124 BSOLUTE AXIMUM ATINGS DC C .............................................................................................................................................................. 124 HARACTERISTICS O D .......................................................................................................................................................................... 125 UTPUT RIVE I V ........................................................................................................................................................................ 125 NPUT OLTAGE PACKAGE MECHANICAL SPECIFICATIONS ...................................................................................................................... 126 Preliminary Revision 0.8 October 29, 1999 ............................................................................................................................................... 124 -iii- VT8231 Table of Contents ...

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... FIGURE 1. PC SYSTEM CONFIGURATION USING THE VT8231......................................................................................... 6 FIGURE 2. VT8231 BALL DIAGRAM (TOP VIEW) .................................................................................................................. 7 FIGURE 3. VT8231 PIN LIST (NUMERICAL ORDER) ............................................................................................................. 8 FIGURE 4. VT8231 PIN LIST (ALPHABETICAL ORDER) ...................................................................................................... 9 FIGURE 5. STRAP OPTION CIRCUIT....................................................................................................................................... 62 FIGURE 6. POWER MANAGEMENT SUBSYSTEM BLOCK DIAGRAM ......................................................................... 120 FIGURE 8. MECHANICAL SPECIFICATIONS – 376 PIN BALL GRID ARRAY PACKAGE......................................... 126 TABLE 1 ...

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... AST THERNET S P OUNDBLASTER AC97 A MC97 M UDIO AND M ASTER , K ONTROLLER EYBOARD IRQ, SMB , S US ERIAL , ACPI, E NHANCED , OLTAGE AND -1- , FIR), OM AND / ULTI HANNEL I ODEM NTERFACE EIDE C ODE ONTROLLER C , RTC, ONTROLLER EEPROM OWER ANAGEMENT - PEED ONITORING VT8231 , , , Features ...

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... Plug and play with 192 base IO address, 12 IRQ and 4 DMA options Floppy Disk Controller 16 bytes of FIFO Data rates up to 1Mbps Perpendicular recording driver support Two FDDs with drive swap support Plug and play with 48 base IO address, 12 IRQ and 4 DMA options Preliminary Revision 0.8 October 29, 1999 -2- VT8231 Features ...

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... Integrated physical layer transceivers with optional over-current detection status on USB inputs Legacy keyboard and PS/2 mouse support System Management Bus Interface One master / slave SMBus and one slave-only SMBus Host interface for processor communications Slave interface for external SMBus masters Preliminary Revision 0.8 October 29, 1999 -3- VT8231 Features ...

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... One additional steerable interrupt channel for on-board plug and play devices Microsoft Windows 2000 BIOS compliant Built-in NAND-tree pin scan test capability 0.30um, 3.3V, low power CMOS process Single chip 27x27 mm, 376 pin BGA Preliminary Revision 0.8 October 29, 1999 TM , Windows 98SE TM , Windows 98 TM -4- , Windows Windows 95 TM and plug and play VT8231 Features ...

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... LPC (Low Pin Count) interface for BIOS ROM plus optional conventional BIOS ROM support d) Universal Serial Bus controller that is USB v1.1 and Universal HCI v1.1 compliant. The VT8231 includes the root hub with four function ports with integrated physical layer transceivers. The USB controller allows hot plug and play and isochronous peripherals to be inserted into the system with universal driver support ...

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... CPU / Cache Sideband Signals: Init / CPUreset IRQ / NMI SMI / StopClk FERR / IGNNE SLP# (Slot-1) Boot ROM Onboard LPC I/O Figure 1. PC System Configuration Using the VT8231 Preliminary Revision 0.8 October 29, 1999 CA MA/Command North Bridge CD MD PCI SMB USB Ports 0-3 Keyboard / Mouse MIDI / Game Ports ...

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... Note: Some of the pins above have alternate functions and alternate names. The table above contains only one name (usually the most often used function), but the pin lists and pin descriptions contain all names. Preliminary Revision 0.8 October 29, 1999 P INOUTS Figure 2. VT8231 Ball Diagram (Top View ...

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... O MTXD3 / AIRQ D10 IO AD02 H01 I ACSDIN0 D11 IO PD0 / INDEX# H02 I ACSDIN1 Center GND pins (24 pins): J8-J13, K8-K13, L8-L13, M8-M13 Preliminary Revision 0.8 October 29, 1999 Figure 3. VT8231 Pin List (Numerical Order) Pin Pin Name H03 O ACSDOUT H04 I JBB2 / GAMED7 H05 I JAY / GAMED1 H06 P VCC ...

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... C19 I EEDI G16 I C20 O EEDO D17 O MDCK Center GND pins (24 pins): J8-J13, K8-K13, L8-L13, M8-M13 Preliminary Revision 0.8 October 29, 1999 Figure 4. VT8231 Pin List (Alphabetical Order) Pin Name Pin Pin Name ERROR#/HDSEL# D18 IO MDIO W09 IO MEMR# FAN1 Y09 IO MEMW# FAN2/SLPB#/IO18 ...

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... PCI Clock. PCLK provides timing for all transactions on the PCI Bus. PCI Bus Clock Run. This signal indicates whether the PCI clock is or will be stopped (high) or running (low). The VT8231 drives this signal low when the PCI clock is running (default on reset) and releases it when it stops the PCI clock. External devices may assert this signal low to request that the PCI clock be restarted or prevent it from stopping ...

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... Signal Description OD CPU Reset. The VT8231 asserts CPURST to reset the CPU during power-up CPU Interrupt. INTR is driven by the VT8231 to signal the CPU that an interrupt request is pending and needs service Non-Maskable Interrupt. interrupt to the CPU. The VT8231 generates an NMI when either SERR# or IOCHK# is asserted ...

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... Internal APIC Data 1. External APIC Acknowledge. Asserted by the VT8231 to indicate that it internal buffers have been flushed (in response to APICREQ#). This indicates to the external APIC that the VT8231’s internal buffers have been flushed and that for the APIC to send its interrupt APIC Clock ...

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... MII Transmit Data. Parallel transmit data lines synchronized to G19 MTXCLK. G18 F20 F19 MII Transmit Enable. Indicates transmit active from the MII port to the PHY. -13- VT8231 Parallel receive data lines driven by the Always active 2 MHz clock Pinouts ...

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... C Channel 2 Data SMB Alert. (System Management Bus I/O space Rx08[ When the chip is enabled to allow it, assertion generates an IRQ or SMI interrupt or a power management resume event. The same pin is used as General Purpose Input 6 whose value is reflected in Rx48[6] of function 4 I/O space -14- VT8231 2 C Bus) Pinouts ...

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... Primary Device DMA Request. Primary channel DMA request I Secondary Device DMA Request. Secondary channel DMA request O Primary Device DMA Acknowledge. Primary channel DMA acknowledge O Secondary Device DMA Acknowledge. Secondary channel DMA acknowledge I Primary Channel Interrupt Request. I Secondary Channel Interrupt Request. -15- VT8231 Output flow control. The Pinouts ...

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... ATA command block or control block is being accessed. O Secondary Disk Address. SDA[2:0] are used to indicate which byte in either the ATA command block or control block is being accessed. IO Primary Disk Data IO Secondary Disk Data (SPKR strap 4.7K ohms low) or ISA Address (SPKR strap 4.7K ohms high) -16- VT8231 This signal corresponds to Pinouts ...

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... AC97 Serial Data AC97 Serial Data AC97 Serial Data AC97 Bit Clock Game Port Interface I/O Signal Description I Joystick A X-axis I Joystick A Y-axis I Joystick B X-axis I Joystick B Y-axis I Joystick A Button 1 I Joystick A Button 2 I Joystick B Button 1 I Joystick B Button 2 -17- VT8231 Pinouts ...

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... Write Gate. Signal to the drive to enable current flow in the write head. I Disk Change. Sense that the drive door is open or the diskette has been changed since the last drive selection. I Write Protect. Sense for detection that the diskette is write protected (causes write commands to be ignored) -18- VT8231 Pinouts ...

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... Error. Status output from the printer. Low indicates an error condition in the printer Busy. Status output from the printer. High indicates not ready to accept data Paper End. Status output from the printer. High indicates that it is out of paper Parallel Port Data -19- VT8231 Pinouts ...

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... DTR/DSR handshake. Designed for direct input from external RS-232C receiver. I Ring Indicator. Indicator to serial port that an external modem is detecting a ring condition. Used by software to initiate operations to answer and open the communications channel. Designed for direct input from external RS-232C receiver (whose input is typically not connected in direct connect environments). -20- VT8231 Pinouts ...

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... Interrupt 8 (optional external RTC Interrupt 12 (optional external PS2 Mouse Controller). T14 I Interrupt 14 (IDE Primary Channel). U14 I Interrupt 15 (IDE Secondary Channel Speaker Drive. Output of internal timer/counter 2. Serial IRQ Pin # I/O Signal Description V9 I Serial IRQ (Rx68[ and Rx74[ -21- VT8231 Pinouts ...

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... Microcontroller Chip Select (Rx76[ Rx76[ Rx77[0] = 1). Asserted during read or write accesses to I/O ports 62h or 66h Programmable Chip Select 0. (Rx76[ and Rx8B[0] = 1). Asserted during I/O cycles to programmable read or write ISA I/O port ranges. See also Rx59[3] and Rx77[2 Programmable Chip Select 1. -22- VT8231 Pinouts ...

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... General Purpose Input General Purpose Input General Purpose Input General Purpose Input General Purpose Input General Purpose Input General Purpose Input 31 -23- VT8231 Pinouts ...

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... General Purpose Output 25 General Purpose Output 26 General Purpose Output 27 General Purpose Output 28 General Purpose Output 29 General Purpose Output 30 General Purpose Output 31. -24- VT8231 Pinouts ...

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... CPU DTD (Thermal Diode) Channel Plus. L3 Analog I CPU DTD (Thermal Diode)Channel Minus Voltage Reference for Thermal Sensing (5V 5 Fan Speed Monitor 1. (3.3V only Fan Speed Monitor 2. (3.3V only Hardware Monitor Digital Test Out J2 O Hardware Monitor Analog Test Out -25- VT8231 Pinouts ...

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... Used by the Power Management subsystem to monitor the opening and closing of the display lid of notebook computers. Can be used to detect either low-to-high and/or high-to-low transitions to generate an SMI#. The VT8231 performs a 200 usec debounce of this input if Function 4 Rx40[5] is set to 1. (10K PU to VCCS if not used Monitor Input – ...

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... Rx40[6] = 1). Connect to VCC if not used. O PCI Reset. Active low reset signal for the PCI bus. The VT8231 will assert this pin during power-up or from the control register. I RTC Crystal Input: 32.768 KHz crystal or oscillator input. This input is used for the internal RTC and for power-well power management logic ...

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... PLL Ground. Connect to GND through a ferrite bead. P USB Differential Output Power. (USBP0+, P0-, P1+, P1-, P2+, P2-, P3+, P3-). Connect to VCC through a ferrite bead. P USB Differential Output Ground. Connect to GND through a ferrite bead. -28- Power for hardware monitoring subsystem Power for USB differential outputs VT8231 Pinouts ...

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... Register Overview The following tables summarize the configuration and I/O registers of the VT8231. These tables also document the power-on default value (“Default”) and access type (“Acc”) for each register. Access type definitions used are RW (Read/Write), RO (Read/Only), “—” for reserved / used (essentially the same as RO), and RWC (or just WC) (Read / Write 1’ ...

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... Write Single Mask Default Acc RW D6 Write Mode RW D8 Clear Byte Pointer Master Clear DC Clear Mask Default Acc DE Read / Write Mask -30- VT8231 Default Acc Default Acc RW Default Acc — * — * — RW — RW Default Acc RW ...

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... A-F -undefined- Offset Serial Port 2 (COM2=2F8, 4=2E8) 0 Transmit (Wr) / Receive (Rd) Buffer 1 Interrupt Enable 2 FIFO Control 2 Interrupt Status 3 UART Control 4 Handshake Control 5 UART Status 6 Handshake Status 7 Scratchpad 9-8 Baud Rate Generator Divisor A-F -undefined- -31- VT8231 Default Acc Default Acc -- ...

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... ISA Positive Decoding Control 4 85 Extended Function Enable 86-87 PnP IRQ/DRQ Test (do not program) 88 PLL Test 89 PLL Control 8A PCS2/3 I/O Port Address Mask 8B PCS Control 8D-8C PCS2# I/O Port Address 8F-8E PCS3# I/O Port Address 90-FF -reserved- -32- VT8231 Default Acc — ...

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... A Secondary Channel Status -reserved C-F Secondary Channel PRD Table Addr A8A8A8A8 -33- VT8231 Default Acc 03030303 — RW 0200 00 — RW 0200 00 — — — 00 — 0000 0000 RW 00 — ...

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... USB Status 0000 RW 5-4 USB Interrupt Enable 0000 RW 7-6 Frame Number 00000000 RW B-8 Frame List Base Address Start Of Frame Modify 11-10 Port 2 Status / Control 0080 WC 0080 WC 13-12 Port 3 Status / Control 00 — 14-1F -reserved- -34- VT8231 Default Acc RO 1106 3038 RO 0000 RW 0200 ...

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... — 0000 0000 — — — -35- VT8231 Default Acc 0001 RW 00 — — Default Acc 0000 0001 RW 00 — — Register Overview ...

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... RW 0000 0000 WC 0000 0000 RW 0000 0000 RW 00 — Default Acc — — input — input RO 03FF FFFF RW 00 — -36- VT8231 Default Acc 0000 RW 0000 RO 00 — Register Overview ...

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... — 00 — 00 — 00 — -37- VT8231 Default Acc — — — — Register Overview ...

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... Function Enable Plug and Play Control 00 44 MC97 Interface Control RO 00 — 45-47 -reserved NMI Control 00 — 49 -reserved- 0000 RW 4B-4A Game Port Base Address 00 — 4C-FF -reserved- -38- VT8231 Default Acc RO 1106 3068 RO 0000 RW 0200 ...

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... Codec GPI Interrupt Status / GPIO 37-34 Codec GPI Interrupt Enable Default Acc 38-FF Reserved 00 — The above registers are accessable through function 6 only. 0000 0000 RW 00 — 0000 0000 RO 00 — -39- VT8231 Default Acc — Default Acc 0330 RW 0200 ...

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... Processor” functions of the SoundBlaster Pro. Preliminary Revision 0.8 October 29, 1999 I/O Registers – Game Port Default Acc Offset Game Port (200-20F typical -reserved Game Port Status RW 1 Start One-Shot WO 2-F -reserved -40- VT8231 Default Acc Register Overview ...

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... Power-On Password Bytes Inaccessable ..default=0 Reserved ........................................always reads 0 A20 Address Line Enable 0 A20 disabled / forced 0 (real mode) ...... default 1 A20 address line enabled High Speed Reset 0 Normal 1 Briefly pulse system reset to switch from protected mode to real mode Register Descriptions - Legacy I/O Ports VT8231 ...

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... Disable Keyboard Interface 0 Enable Keyboard Inhibit Function......... default 1 Disable Keyboard Inhibit Function 0 Disable mouse interrupts ....................... default 1 Generate interrupt on IRQ12 when mouse data comes in output bufer 0 Disable Keyboard Interrupts.................. default 1 Generate interrupt on IRQ1 when output buffer has been written. Register Descriptions - Legacy I/O Ports VT8231 ...

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... Port 64 - Keyboard / Mouse Command .......................... WO This port is used to send commands to the keyboard / mouse controller. The command codes recognized by the VT8231 are listed n the table below. Note: The VT8231 Keyboard Controller is compatible with the VIA VT82C42 Industry-Standard Keyboard Controller except that due to its integrated nature, many of the input and ...

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... Read Channel 4-7 Request Register ........... RO rd Port D0 –3 Read Channel 4 Mode Register .................. RO th Port D0 –4 Read Channel 5 Mode Register .................. RO th Port D0 –5 Read Channel 6 Mode Register .................. RO th Port D0 –6 Read Channel 7 Mode Register .................. RO Port DE –Channel 4-7 Read All Mask ............................. RO -44- Register Descriptions - Legacy I/O Ports VT8231 ...

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... Port 40 – Counter 0 Base Count Value (LSB 1 Port 41 – Counter 1 Base Count Value (LSB 1 Port 42 – Counter 2 Base Count Value (LSB 1 -45- Register Descriptions - Legacy I/O Ports VT8231 the shadow registers are ...

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... Update Ended Flag 3-0 0 Unused (always read 0) 7 VRT Reads 1 if VBAT voltage is OK 6-0 0 Unused (always read 0) Binary Range BCD Range 01-1Fh 01-0Ch 13-14h Register Descriptions - Legacy I/O Ports VT8231 00-59h 00-59h 00-59h 00-59h 01-12h 81-92h 00-23h 01-12h 81-92h 00-23h 01-07h 01-31h 01-12h 00-99h ...

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... Index E7 – Serial Port 1 I/O Base Address ..................... RW I/O Address 9-3.........................................default = 0 7-1 0 Must be 0 ..............................................default = 0 Index E8 – Serial Port 2 I/O Base Address ..................... RW 7-1 I/O Address 9-3.........................................default = 0 0 Must be 0 ..............................................default = 0 -47- Register Descriptions - Super-I/O I/O Ports VT8231 ...

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... IRTX / IRRX Output from Serial Port 2...... def 1 Function 0 Rx76[ IRRX output from dedicated pin D12 IRTX output from dedicated pin E12 1-0 Reserved ........................................always reads 0 Index F2 – Test Mode (Do Not Program) ....................... RW Index F4 – Test Mode (Do Not Program) ....................... RW -48- Register Descriptions - Super-I/O I/O Ports VT8231 ...

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... Floppy Drive 3 (see table below) 5-4 Floppy Drive 2 (see table below) 3-2 Floppy Drive 1 (see table below) 1-0 Floppy Drive 0 (see table below) DRVEN1 00 DRATE0 01 DRATE0 10 DRATE0 n/a 11 DRATE1 n/a n/a n -49- Register Descriptions - Super-I/O I/O Ports VT8231 DRVEN0 DENSEL DRATE1 DENSEL# DRATE0 ...

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... C3h of the Super-I/O configuration registers). FDCBase is typically set to allow these ports to be accessed at the standard floppy disk controller address range of 3F0-3F7h. Port FDCBase+2 – FDC Command ................................. RW 7 Motor 3 (unused in VT8231: no MTR3# pin) 6 Motor 2 (unused in VT8231: no MTR2# pin) 5 Motor 1 0 ...

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... Port LPTBase+6 – Parallel Port EPP Data Port 2 ......... RW Port LPTBase+7 – Parallel Port EPP Data Port 3 ......... RW Port LPTBase+400h – Parallel Port ECP Data / Cfg A RW Port LPTBase+401h – Parallel Port ECP Config B ....... RW Port LPTBase+401h – Parallel Port ECP Extd Ctrl ...... RW -51- Register Descriptions - Super-I/O I/O Ports VT8231 ...

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... Preliminary Revision 0.8 October 29, 1999 Port COM1Base+4 – Handshake Control ...................... RW 7-5 Undefined ......................................... always read 0 4 Loopback Check 0 Normal operation 1 Loopback enabled 3 General Purpose Output 2 (unused in VT8231) 2 General Purpose Output 1 (unused in VT8231) 1 Request To Send 0 Disabled 1 Enabled 0 Data Terminal Ready 0 Disabled 1 Enabled Port COM1Base+5 – ...

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... Preliminary Revision 0.8 October 29, 1999 Port COM1Base+4 – Handshake Control ...................... RW 7-5 Undefined ......................................... always read 0 4 Loopback Check 0 Normal operation 1 Loopback enabled 3 General Purpose Output 2 (unused in VT8231) 2 General Purpose Output 1 (unused in VT8231) 1 Request To Send 0 Disabled 1 Enabled 0 Data Terminal Ready 0 Disabled 1 Enabled Port COM1Base+5 – ...

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... Finp = Input Filter Fout = Output Filter TFIL = Input Filter Type ST = Stereo / Mono Mode Select = Input Choices (0=Microphone, 1=CD, 3=Line) Command Summary – Sound Processor (see next page) -54- Register Descriptions - Super-I/O I/O Ports VT8231 Test SSSC SSFC Multi Total Level (TL) Decay Rate (DR) Release Rate (RR) Block ...

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... Joystick B Button 1 Status 5 Joystick A Button 2 Status 4 Joystick A Button 1 Status 3 Joystick B One-Shot Status for Y-Potentiometer 2 Joystick B One-Shot Status for X-Potentiometer 1 Joystick A One-Shot Status for Y-Potentiometer 0 Joystick A One-Shot Status for X-Potentiometer I/O Port 201h – Start One-Shot ....................................... WO 7-0 (Value Written is Ignored) -55- Register Descriptions - Super-I/O I/O Ports VT8231 ...

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... Register Number Used to select a specific DWORD in the device’s configuration space ........................................ always reads 0 1-0 Fixed Port CFF-CFC - Configuration Data .............................. RW Preliminary Revision 0.8 October 29, 1999 There are 7 “functions” implemented in the VT8231: Function # Function 0 PCI to ISA Bridge 1 IDE Controller 2 USB Controller Ports 0-1 3 ...

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... Function 0 Registers - PCI to ISA Bridge All registers are located in the function 0 PCI configuration space of the VT8231. These registers are accessed through PCI configuration mechanism #1 via I/O address CF8/CFC. PCI Configuration Space Header Offset 1-0 - Vendor ID = 1106h ......................................... RO Offset 3-2 - Device ID = 8231h .......................................... RO Offset 5-4 - Command ....................................................... RW 15-8 Reserved ...

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... DMA type F Timing on Channel 7............default=0 5 DMA type F Timing on Channel 6............default=0 4 DMA type F Timing on Channel 5............default=0 3 DMA type F Timing on Channel 3............default=0 2 DMA type F Timing on Channel 2............default=0 1 DMA type F Timing on Channel 1............default=0 0 DMA type F Timing on Channel 0............default=0 -58- Function 0 Registers - PCI to ISA Bridge VT8231 ...

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... Write Delay Transaction Time-Out Timer 0 Disable................................................... default 1 Enable 1 Read Delay Transaction Time-Out Timer 0 Disable................................................... default 1 Enable Software PCI Reset ......write 1 to generate PCI reset 0 -59- Function 0 Registers - PCI to ISA Bridge VT8231 Write" function is ...

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... Forward D8000-DBFFF Accesses to PCI ......def=0 5 Forward D4000-D7FFF Accesses to PCI .......def=0 4 Forward D0000-D3FFF Accesses to PCI .......def=0 3 Forward CC000-CFFFF Accesses to PCI .....def=0 2 Forward C8000-CBFFF Accesses to PCI ......def=0 1 Forward C4000-C7FFF Accesses to PCI .......def=0 0 Forward C0000-C3FFF Accesses to PCI .......def=0 -60- Function 0 Registers - PCI to ISA Bridge VT8231 ...

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... PnP IRQ Routing Table 0000 Disabled................................................. default 0001 IRQ1 0010 Reserved 0011 IRQ3 0100 IRQ4 0101 IRQ5 0110 IRQ6 0111 IRQ7 1000 Reserved 1001 IRQ9 1010 IRQ10 1011 IRQ11 1100 IRQ12 1101 Reserved 1110 IRQ14 1111 IRQ15 -61- Function 0 Registers - PCI to ISA Bridge VT8231 ...

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... APIC Connection 0 APIC on SD Bus.................................... default 1 APIC on XD Bus 1 Reserved (Do Not Program) ....................default = 0 0 DMA Line Buffer Disable 0 DMA cycles can be to/from line buffer ....... def 1 Disable DMA Line Buffer -62- Function 0 Registers - PCI to ISA Bridge VT8231 If the internal RTC is ...

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... Channel 6 Base Address Bits 15-4...........default = 0 3 Channel 6 Enable 0 Disable................................................... default 1 Enable 2-0 Reserved ........................................always reads 0 Offset 6F-6E - Distributed DMA Ch 7 Base / Enable .... RW 15-4 Channel 7 Base Address Bits 15-4...........default = 0 3 Channel 7 Enable 0 Disable................................................... default 1 Enable 2-0 Reserved ........................................always reads 0 -63- Function 0 Registers - PCI to ISA Bridge VT8231 ...

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... GPO25 Enable (Pin G5) 0 Rx75[3]=0: Pin G5 defined as DACK2# .... def 1 Pin G5 defined as GPO25 1 GPO24 Enable (Pin H3) 0 Rx75[3]=0: ............................................ default Rx68[3]=0: Pin H3 defined as DRQ2 Rx68[3]=1: Pin H3 defined as SERIRQ 1 Pin H3 defined as GPO24 0 Positive Decode 0 Subtractive Decode................................ default 1 Positive Decode -64- Function 0 Registers - PCI to ISA Bridge VT8231 ...

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... Enable Offset 7F-7E – 32-Bit DMA Control ............................... RW 15-3 32-Bit DMA High Page (A31-24) Registers IOBase ........................................always reads 0 2-1 Reserved 0 32-Bit DMA 0 Disable................................................... default 1 Enable Offset 80 – Programmable Chip Select Mask ................ RW 7-4 PCS1# I/O Port Address Mask [3-0] 3-0 PCS0# I/O Port Address Mask [3-0] -65- Function 0 Registers - PCI to ISA Bridge VT8231 ...

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... Reserved ........................................always reads 0 FDC Decoding Range 0 Primary .................................................. default 1 Secondary Sound Blaster Positive Decoding 0 Disable................................................... default 1 Enable Sound Blaster Decode Range 00 220h-22Fh, 230h-233h .......................... default 01 240h-24Fh, 250h-253h 10 260h-26Fh, 270h-273h 11 280h-28Fh, 290h-293h Function 0 Registers - PCI to ISA Bridge VT8231 ...

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... Function 5 Audio 0 Enable.....................................................default 1 Disable 1 Super-I/O Configuration 0 Disable ...................................................default 1 Enable 0 Super-I/O 0 Disable ...................................................default 1 Enable Preliminary Revision 0.8 October 29, 1999 Offset 86 – PNP IRQ/DRQ Test 1 (Do Not Program) ... RW Offset 87 – PNP IRQ/DRQ Test 2 (Do Not Program) ... RW -67- Function 0 Registers - PCI to ISA Bridge VT8231 ...

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... Disable................................................... default 1 Enable 3 PCS3# 0 Disable................................................... default 1 Enable 2 PCS2# 0 Disable................................................... default 1 Enable 1 PCS1# 0 Disable................................................... default 1 Enable 0 PCS0# 0 Disable................................................... default 1 Enable Offset 8D-8C – PCS2# I/O Port Address ........................ RW 15-0 PCS2# I/O Port Address Offset 8F-8E – PCS3# I/O Port Address ......................... RW 15-0 PCS3# I/O Port Address -68- Function 0 Registers - PCI to ISA Bridge VT8231 ...

Page 75

... PCI configuration registers and Bus Master IDE I/O registers. The PCI configuration registers are located in the function 1 PCI configuration space of the VT8231. The Bus Master IDE I/O registers are defined in the SFF8038i v1.0 specification. PCI Configuration Space Header Offset 1-0 - Vendor ID (1106h=VIA) ................................ RO Offset 3-2 - Device ID (0571h=IDE Controller) ...

Page 76

... Offset 34 - Capability Pointer (C0h) ................................ RO Offset 3C - Interrupt Line (0Eh) ...................................... RO Offset 3D - Interrupt Pin (00h) ......................................... RO 7-0 Interrupt Routing Mode 00h Legacy mode interrupt routing............... default 01h Native mode interrupt routing Offset 3E - Min Gnt (00h) ................................................. RO Offset 3F - Max Latency (00h).......................................... RO -70- Function 1 Registers - Enhanced IDE Controller VT8231 ...

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... Reserved (Do Not Change)........................ default Reserved ........................................ always reads 0 Offset 42 - Reserved (Do Not Program) .......................... RW Preliminary Revision 0.8 October 29, 1999 Offset 43 - FIFO Configuration ....................................... RW 7-4 Reserved ........................................always reads 0 3-2 Threshold for Primary Channel 1/4 10 1/2 .................................................... default 11 3/4 1-0 Threshold for Secondary Channel 1/4 10 1/2 .................................................... default 11 3/4 -71- Function 1 Registers - Enhanced IDE Controller VT8231 ...

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... Max DRDY Pulse Width Maximum DRDY# pulse width after the cycle count. Command will deassert in spite of DRDY# status to avoid system ready hang limitation.......................................... default 01 64 PCI clocks 10 128 PCI clocks 11 192 PCI clocks -72- Function 1 Registers - Enhanced IDE Controller VT8231 ...

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... Sec Drive 1 Transfer Mode 4 Reserved ........................................always reads 0 3 Sec Clock Source 0 33 MHz.................................................. default 1 66 MHz 2-0 Sec Drive 1 Cycle Time Each byte defines UltraDMA operation for the indicated drive. The bit definitions are the same within each byte. -73- Function 1 Registers - Enhanced IDE Controller VT8231 ...

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... Enabled...................................................default 1 Disabled Preliminary Revision 0.8 October 29, 1999 Offset 61-60 - Primary Sector Size .................................. RW 15-12 Reserved ........................................always reads 0 11-0 Number of Bytes Per Sector ...def=200h (512 bytes) Offset 69-68 - Secondary Sector Size .............................. RW 15-12 Reserved ........................................always reads 0 11-0 Number of Bytes Per Sector ...def=200h (512 bytes) -74- Function 1 Registers - Enhanced IDE Controller VT8231 ...

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... Prefetch Buffer Status 5 Post Write Buffer Status 4 DMA Read Prefetch Status 3 DMA Write Prefetch Status 2 S/G Operation Complete 1-0 Reserved ........................................always reads 0 Offset 79 - Secondary Interrupt Control ........................ RW 7-1 Reserved ........................................always reads 0 0 Flush FIFO Before Generating IDE Interrupt 0 Disable................................................... default 1 Enable -75- Function 1 Registers - Enhanced IDE Controller VT8231 ...

Page 82

... Refer to the SFF 8038I v1.0 specification for further details. I/O Offset 0 - Primary Channel Command I/O Offset 2 - Primary Channel Status I/O Offset 4-7 - Primary Channel PRD Table Address I/O Offset 8 - Secondary Channel Command I/O Offset A - Secondary Channel Status I/O Offset C-F - Secondary Channel PRD Table Address -76- Function 1 Registers - Enhanced IDE Controller VT8231 ...

Page 83

... PCI configuration registers and USB I/O registers. The PCI configuration registers are located in the function 2 PCI configuration space of the VT8231. The USB I/O registers are defined in UHCI specification v1.1. The registers in this function control USB ports 0-1 (see function 3 for ports 2-3). PCI Configuration Space Header Offset 1-0 - Vendor ID ...

Page 84

... Set trap 60/64 status bits without checking enable bits 1 A20gate Pass Through Option 0 Pass through A20GATE command sequence defined in UHCI .................................... default 1 Don’t pass through Write I/O port 64 (ff) 0 USB IRQ Test Mode 0 Normal Operation .................................. default 1 Generate USB IRQ -78- Function 2 Registers - USB Controller Ports 0-1 VT8231 ...

Page 85

... Refer to the UHCI v1.1 specification for further details. I/O Offset 1-0 - USB Command I/O Offset 3-2 - USB Status I/O Offset 5-4 - USB Interrupt Enable I/O Offset 7-6 - Frame Number I/O Offset B-8 - Frame List Base Address I/O Offset 0C - Start Of Frame Modify I/O Offset 11-10 - Port 0 Status / Control I/O Offset 13-12 - Port 1 Status / Control -79- Function 2 Registers - USB Controller Ports 0-1 VT8231 ...

Page 86

... PCI configuration registers and USB I/O registers. The PCI configuration registers are located in the function 3 PCI configuration space of the VT8231. The USB I/O registers are defined in UHCI specification v1.1. The registers in this function control USB ports 2-3 (see function 2 for ports 0-1). PCI Configuration Space Header Offset 1-0 - Vendor ID ...

Page 87

... Set trap 60/64 status bits without checking enable bits 1 A20gate Pass Through Option 0 Pass through A20GATE command sequence defined in UHCI .................................... default 1 Don’t pass through Write I/O port 64 (ff) 0 USB IRQ Test Mode 0 Normal Operation .................................. default 1 Generate USB IRQ -81- Function 3 Registers - USB Controller Ports 2-3 VT8231 ...

Page 88

... Refer to the UHCI v1.1 specification for further details. I/O Offset 1-0 - USB Command I/O Offset 3-2 - USB Status I/O Offset 5-4 - USB Interrupt Enable I/O Offset 7-6 - Frame Number I/O Offset B-8 - Frame List Base Address I/O Offset 0C - Start Of Frame Modify I/O Offset 11-10 - Port 0 Status / Control I/O Offset 13-12 - Port 1 Status / Control -82- Function 3 Registers - USB Controller Ports 2-3 VT8231 ...

Page 89

... Power Interface) Power Management system of the VT8231 which includes a System Management Bus (SMBus) interface controller and Hardware Monitoring (HWM) subsystem. The power management system of the VT8231 supports both ACPI and legacy power management functions and is compatible with the APM v1.2 and ACPI v1.0 specifications. ...

Page 90

... RTC Enable Signal Gated with PSON (SUSC#) in Soft-Off Mode 0 Disable................................................... default 1 Enable 1 Clock Throttling Clock Selection 0 32 usec (512 usec cycle time) ................ default 1 1 msec (16 msec cycle time) 0 DEVSEL# Test Mode (Do Not Program).......def = 0 -84- Function 4 Regs - Power Management, SMBus and HWM VT8231 The ...

Page 91

... Ena/Disa IRQ6 as Secondary Intr Channel 5 1/0 = Ena/Disa IRQ5 as Secondary Intr Channel 4 1/0 = Ena/Disa IRQ4 as Secondary Intr Channel 3 1/0 = Ena/Disa IRQ3 as Secondary Intr Channel 2 Reserved ........................................always reads 0 1 1/0 = Ena/Disa IRQ1 as Secondary Intr Channel 0 1/0 = Ena/Disa IRQ0 as Secondary Intr Channel -85- Function 4 Regs - Power Management, SMBus and HWM VT8231 ...

Page 92

... Fast Clock (7.5us) as Throttle Timer Tick 0 Disable................................................... default 1 Enable Reserved ........................................always reads 0 Internal Clock Stop for PCI Idle 0 Disable................................................... default 1 Enable Internal Clock Stop During C3 0 Disable................................................... default 1 Enable Internal Clock Stop During Suspend 0 Disable................................................... default 1 Enable VT8231 ...

Page 93

... GP0 Timer Automatic Reload 0 1 1-0 GP0 Timer Base 00 Disable................................................... default 01 1/16 second 10 1 second 11 1 minute Register (Power -87- Function 4 Regs - Power Management, SMBus and HWM Timer Reload Enable Register GP0 Timer stops at 0 ............................ default Reload GP0 timer automatically after counting down to 0 VT8231 (Power ...

Page 94

... GPO0 (SLOWCLK) Output Selection (Pin T8) 00 From GPO0 (PMU I/O Rx4C[0])...........default Preliminary Revision 0.8 October 29, 1999 Offset 55 – USB Wakeup .................................................. RW 7-1 Reserved ........................................always reads 0 0 USB Wakeup for STR/STD/Soff 0 Disable................................................... default 1 Enable -88- Function 4 Regs - Power Management, SMBus and HWM VT8231 ...

Page 95

... Preliminary Revision 0.8 October 29, 1999 Offset 59 – GP2 Timer ...................................................... RW 7 Write: GP2 Timer Load Value...............default = 0 Read: GP2 Timer Current Count Offset 5A – GP3 Timer ..................................................... RW 7 Write: GP3 Timer Load Value...............default = 0 Read: GP3 Timer Current Count -89- Function 4 Regs - Power Management, SMBus and HWM VT8231 ...

Page 96

... Code) may be changed by writing the desired value to this location. Offset 63 - Base Class Read Value .................................. WO 7-0 Rx0B Read Value The value returned by the register at offset 0Bh (Base Class Code) may be changed by writing the desired value to this location. Preliminary Revision 0.8 October 29, 1999 -90- Function 4 Regs - Power Management, SMBus and HWM VT8231 ...

Page 97

... Bit-0 must be set to 0 for proper operation Offset D5 – SMBus Slave Address for Port 2 ................. RW 7-0 SMBus Slave Address for Port 2...............default=0 Bit-0 must be set to 0 for proper operation Offset D6 – SMBus Revision ID ....................................... RO 7-0 SMBus Revision Code -91- Function 4 Regs - Power Management, SMBus and HWM VT8231 ...

Page 98

... GBL_STS bit is set. Reserved ........................................always reads 0 ........................................always reads 0 Reserved ACPI Timer Enable (TMR_EN) ..............default = 0 This bit may be set to trigger either an SCI or an SMI (depending on the setting of the SCI_EN bit generated when the TMR_STS bit is set. Power Management I/O-Space Registers VT8231 ...

Page 99

... S0 (working) system state. The timer is reset to an initial value of zero during a reset, and then continues counting until the 14.31818 MHz input to the chip is stopped. If the clock is restarted without a reset, then the counter will continue counting from where it stopped. -93- Power Management I/O-Space Registers VT8231 ...

Page 100

... Level 2 Reads from this register put the processor into the Stop Grant state (the VT8231 asserts STPCLK# to suspend the processor). Wake up from Stop Grant state is by interrupt (INTR, SMI, and SCI). Reads from this register return all zeros; writes to this register have no effect ...

Page 101

... Enable SMI on setting of the GPI16_STS bit.def=0 1 Enable SMI on setting of the GPI1_STS bit...def=0 0 Enable SMI on setting of the EXT_STS bit....def=0 These bits allow generation of an SMI using a separate set of conditions from those used for generating an SCI. -95- Power Management I/O-Space Registers VT8231 ...

Page 102

... SMI on Secondary Event Timer Time Out (STTO_EN) ......................................................def=0 This bit may be set to trigger an SMI to be generated when the STTO_STS bit is set. SMI on Primary Activity (PACT_EN) ...........def=0 0 This bit may be set to trigger an SMI to be generated when the PACT_STS bit is set. -96- VT8231 ........................................always reads 0 Power Management I/O-Space Registers ...

Page 103

... Preliminary Revision 0.8 October 29, 1999 I/O Offset 2F - SMI Command (SMI_CMD) ................. RW 7-0 from suspend when -97- SMI Command Writing to this port sets the SW_SMI_STS bit. Note that if the SW_SMI_EN bit is set (see bit-6 of the Global Enable register at offset 2Ah), then an SMI is generated. Power Management I/O-Space Registers VT8231 ...

Page 104

... Don't set PACT_STS if PIDE_STS is set.... def 1 Set PACT_STS if PIDE_STS is set 1 SMI on Primary INTR Status .............. (PIRQ_EN) 0 Don't set PACT_STS if PIRQ_STS is set.... def 1 Set PACT_STS if PIRQ_STS is set 0 SMI on PCI Master Status .................... (DRQ_EN) 0 Don't set PACT_STS if DRQ_STS is set .... def 1 Set PACT_STS if DRQ_STS is set -98- Power Management I/O-Space Registers VT8231 ...

Page 105

... GPIO Ramge 3 Access Status ............. (GPR3_STS) 0 GPIO Ramge 2 Access Status ............. (GPR2_STS) I/O Offset 42 – Extended I/O Trap Enable ..................... RW 7-2 Reserved 1 SMI on GPIO Ramge 3 Access.............(GPR3_EN SMI on GPIO Ramge 2 Access.............(GPR2_EN SIDE_STS, or -99- ......................................... always read 0 ......................................... always read 0 Disable................................................... default Enable Disable................................................... default Enable Power Management I/O-Space Registers VT8231 ...

Page 106

... GPI[23-16] by Refresh Scan .................... Read Only ......................................... always read 0 15-12 Reserved 11-0 GPI[11-0] Input Value ............................. Read Only I/O Offset 4F-4C - GPO Port Output Value (GPOVAL) RW Reads from this register return the last value written (held on chip) ........................................always reads 0 31-26 Reserved 25-0 GPO[25-0] Output Value................def = 3FFFFFFh -100- Power Management I/O-Space Registers VT8231 ...

Page 107

... Reserved ........................................always reads 0 Slave Busy ......................................................... RO 0 SMBus controller slave interface is not processing data ...................................... default 1 SMBus controller slave interface is busy receiving data. None of the other SMBus registers should be accessed if this bit is set. System Management Bus I/O-Space Registers VT8231 ...

Page 108

... It is reset reads of the SMBus Host Control register (I/O Offset 2) and incremented automatically by each access to this register. The transfer of block data into (read) or out of (write) this storage array during an SMBus transaction always starts at index address 0. SMBUS Block Data ..................................default = 0 7-0 -102- System Management Bus I/O-Space Registers VT8231 ...

Page 109

... SMBus Slave Data ....................................default = 0 This field contains the data value which was transmitted during an external SMBus master access whose address field matched one of the slave shadow port addresses or the SMBus host controller slave port address of 10h. -103- System Management Bus I/O-Space Registers VT8231 ...

Page 110

... One consequence of the above is that if high limits are set to all ones (FFh or 11111111b), interrupts are disabled for high limits (i.e., interrupts will only be generated for cases when voltages are equal to or below the low limits). -104- Hardware Monitor I/O Space Registers VT8231 ...

Page 111

... Preliminary Revision 0.8 October 29, 1999 Temperature Resolution All high and low limits -105- VT8231 Hardware Monitor I/O Space Registers ...

Page 112

... Enable interrupt on error status bit set ......... def 1 Disable interrupt on error status bit set 0 Enable interrupt on error status bit set ......... def 1 Disable interrupt on error status bit set ........................................always reads 0 0 Enable interrupt on error status bit set ......... def 1 Disable interrupt on error status bit set Hardware Monitor I/O Space Registers VT8231 ...

Page 113

... Comparator mode. An interrupt occurs if the temperature goes above the hot limit. This interrupt remains active until the temperature goes below the hot limit (i.e., no hysteresis). 11 Default Interrupt Mode (same as 00) -107- Hardware Monitor I/O Space Registers VT8231 An interrupt is ...

Page 114

... SoundBlaster Pro. There are two sets of software accessible registers: PCI configuration registers and I/O registers. The PCI configuration registers for the Audio Codec are located in the function 5 PCI configuration space of the VT8231. The PCI configuration registers for the Modem Codec are located in the function 6 PCI configuration space. The I/O registers are located in the system I/O space. PCI Configuration Space Header – ...

Page 115

... IRQ6 0111 IRQ7 1000 IRQ8 1001 IRQ9 1010 IRQ10 1011 IRQ11 1100 IRQ12 1101 IRQ13 1110 IRQ14 1111 Disabled Offset 3D - Interrupt Pin (03h) ......................................... RO Offset 3E - Minimum Grant (00h) .................................... RO Offset 3F - Maximum Latency (00h) ................................ RO -109- Function 5 & 6 Registers - AC97 Audio & Modem Codecs VT8231 ...

Page 116

... AC Link FM Channel PCM Data Out (SELFM) 0 Disable................................................... default 1 Enable Bit valid in function 5 only (reserved in function Link SB PCM Data Output (SELSB) 0 Disable................................................... default 1 Enable Bit valid in function 5 only (reserved in function 6) -110- Function 5 & 6 Registers - AC97 Audio & Modem Codecs VT8231 ...

Page 117

... FM SGD Data for SoundBlaster Mixing 0 Disable................................................... default 1 Enable 0 FM Trap Interrupt 0 Enable .................................................... default 1 Disable Offset 4B-4A – Game Port Base Address . RW (Function 5) Offset 4B-4A – Game Port Base Address .. RO (Function 6) 15-0 Game Port Base Address .........................default = 0 -111- Function 5 & 6 Registers - AC97 Audio & Modem Codecs VT8231 ...

Page 118

... If the channel “Interrupt on FLAG” bit is set, then an interrupt is generated at the end of this block. STOP Block Stop. If set, transfer pauses at the end of this block. To resume the transfer, write 1 to Rx?0[2]. -112- Function 5 & 6 Registers - AC97 Audio & Modem Codecs VT8231 55-32 31-0 Base Base Count ...

Page 119

... Slot 6 Data Select 15-12 Slot 8 Data Select 11-8 Slot 7 Data Select 7-4 Slot 4 Data Select 3-0 Slot 3 Data Select I/O Offset 4F-4C – 3D Channel SGD Current Count ..... RO 31-24 Current SGD Index 23-0 Current SGD Count -113- Function 5 & 6 Registers - AC97 Audio & Modem Codecs VT8231 ...

Page 120

... I/O Offset 57-54 – FM Channel SGD Table Pointer ...... RW 31-0 SGD Table Pointer Base Address (even addr).....W Current Pointer Address ........................................R I/O Offset 5F-5C – FM Channel SGD Current Count .... RO 31-24 Current SGD Index 23-0 Current SGD Count Preliminary Revision 0.8 October 29, 1999 -114- Function 5 & 6 Registers - AC97 Audio & Modem Codecs VT8231 ...

Page 121

... Disable................................................... default 1 Enable I/O Offset 77-74 – Wr Channel 1 SGD Table Pointer ... RW 31-0 SGD Table Pointer Base Address (even addr) .... W Current Pointer Address ....................................... R I/O Offset 7F-7C – Wr Channel 1 SGD Current Count . RO 31-24 Current SGD Index 23-0 Current SGD Count -115- Function 5 & 6 Registers - AC97 Audio & Modem Codecs VT8231 ...

Page 122

... DX1 Read Chan SGD FLAG Shadow ..... (Rx10[0]) 3 Reserved ........................................always reads 0 2 DX0 Read Chan SGD STOP Shadow ...... (Rx00[2]) 1 DX0 Read Chan SGD EOL Shadow ........ (Rx00[1]) 0 DX0 Read Chan SGD FLAG Shadow ..... (Rx00[0]) -116- Function 5 & 6 Registers - AC97 Audio & Modem Codecs VT8231 ...

Page 123

... Function 5 I/O Base 2 Registers –MIDI / Game Port I/O Offset 1-0 – MIDI Port Base ..................................... RW 15-0 MIDI Port Base Address.................. default = 0330h This register is functional only if Rx42[ I/O Offset 3-2 – Game Port Base ..................................... RW 15-0 Game Port Base Address ................. default = 0200h -117- Function 5 & 6 Registers - AC97 Audio & Modem Codecs VT8231 ...

Page 124

... Enable I/O Offset 17-14 – Modem Wr Chan SGD Table Ptr .... RW 31-0 SGD Table Pointer Base Address (even addr) .... W Current Pointer Address ....................................... R I/O Offset 1F-1C – Modem Wr Chan SGD Current Cnt RO 31-24 Current SGD Index 23-0 Current SGD Count -118- Function 5 & 6 Registers - AC97 Audio & Modem Codecs VT8231 ...

Page 125

... clear 15-0 Codec GPIO .........................................................RW R Reflect status of Codec GPI[15-0] W GPO[15-0]; triggers AC-Link slot-12 output to codec Offset 37-34 – Codec GPI Interrupt Enable ................... RW 31-16 Interrupt on GPI[15-0] Change of Status..........RW 0 Disable 1 Enable ........................................always reads 0 15-0 Reserved -119- Function 5 & 6 Registers - AC97 Audio & Modem Codecs VT8231 ...

Page 126

... Refer to ACPI Specification v1.0 and APM specification v1.2 for additional information. Preliminary Revision 0.8 October 29, 1999 Processor Bus States The VT8231 supports the complete set processor states as specified in the Advanced Configuration and Power Interface (ACPI) specification (and defined in ACPI I/O space Registers 10-15): C0: ...

Page 127

... POS (only SUSA# asserted), to STR (both SUSA# and SUSB# asserted), and to STD (all three SUS# signals asserted). In particular, the assertion of SUSC# can be used to turn off the VCC supply to the VT8231. One additional suspend status indicator (SUSST1#) is provided to inform the north bridge and the rest of the system of the processor and system suspend states ...

Page 128

... PCI Bus PCLK BIOS ROM Keyboard / Mouse Figure 7. System Block Diagram Using the VT8231 Super South Bridge Preliminary Revision 0.8 October 29, 1999 3) Generic Global Events defined in the GBL_STS and System and Processor Resume Events Depending on the system suspend state, different features can be enabled to resume the system ...

Page 129

... Legacy Power Management Timers In addition to the ACPI power management timer, the VT8231 includes the following four legacy power management timers: GP0 Timer: general purpose timer with primary event GP1 Timer: general purpose timer with peripheral event reload Secondary Event Timer: to monitor secondary events ...

Page 130

... Volts V MII Volts V RAM Volts V PLL Volts V BAT Volts FERR#, USBCLK, PWRBTN#, EXTSMI#, BATLOW#, FAN1, FAN2, SMBCLK, SMBDATA Volts All other inputs Unit Condition 4.0mA -1.0mA < V < 0.45 < V < V OUT CC mA Electrical Specifications VT8231 ...

Page 131

... MSI, ACSDIN[2:0], ACBITCLK, GPIOA, GPIOC, GPIOD, GPIOE, GPI0, GPI1, PWRGD, BATLOW#, THRM USBP[3:0]+/-, USBCLK, USBOC[1:0]#, LDRQ#, LAD[3:0], EEDI, PCICLK, APICCLK, WSC#, FAN1, FAN2 / SLPBTN#, PWRBTN#, RTCX1, EXTSMI#, RSMRST#, PME#, LID, RING#, CPUMISS, INTRUDER# -125- VT8231 Load Delay ...

Page 132

... Figure 8. Mechanical Specifications – 376 Pin Ball Grid Array Package Preliminary Revision 0.8 October 29, 1999 M S ECHANICAL PECIFICATIONS 24.00 Ref -126- VT8231 Ø 1.00 (3X) Ref. Ø 0.75±0.15 (376X) Package Mechanical Specifications ...

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