TW9903 ETC-unknow, TW9903 Datasheet
TW9903
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... Techwell, Inc. TW9903 – Multi-standard Video Decoder With High Quality Down Scaler Preliminary Data Sheet Techwell Confidential. Information may change without notice. Disclaimer This document provides technical information for the user. Techwell, Inc. reserves the right to modify the information in this document as necessary. The customer should make sure that they have the most recent data sheet version ...
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... CLKX2 and CLKX1.......................................................20 ITU-R BT.656...............................................................20 Down-scaling and Cropping ..........................................21 TW9903 Down -Scaling.................................................21 TW9903 Cropping........................................................22 VBI Data Processing........................................................24 TW9903 VBI Overview .................................................24 VBI Frame Output Mode...............................................25 VBI Byte Order.............................................................25 Closed Captioning and Extended Data Services ................25 Two Wire Serial Bus Interface...........................................27 Test Modes .....................................................................30 Filter Curves ....................................................................31 Decimation filter ...
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... TW9903 TW9903 – NTSC/PAL/SECAM Analog to Digital Video Decoder with High Quality Scaler Introduction and Features Techwell’s TW9903 is a high quality NTSC, PAL, and SECAM video decoder plus high quality down scaler designed for multimedia applications. TW9903 uses the mixed-signal technology to provide a low-cost and low-power integrated solution ...
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... TW9903 Functional Description C(0) C(1) Yin MUXOUT MUXin0 MUXin1 (1) MUXin2 MUXin3 TRST TCK TMS TDI TDO 27 Mhz SIAD1 SIAD0 SDA SCLK TECHWELL, INC. Figure 1: TW9903 Block Diagram CCVALID VD(15:8) Y VD(7:0) MPOUT CBFLAG VCLK VSYNC HSYNC FIELD VACTIVE HACTIVE DVALI D CLKx2 CLKx1 PDN OE REV. 0. ...
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... The high quality scaler uses multi-tap poly-phase decimation filter to reduce aliasing effects. It can be programmed to scale-down the output picture to an arbitrary ratio with cropping. The TW9903 supports flexible pixel int erface. It outputs YCbCr (4:2:2) data stream over 8 -bit or 16-bit data path. The output is VMI 1.4 compatible. ...
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... Analog to Digital Converter TW9903 contains three 8 -bit pipelined ADCs that consume less power than conventional flash ADC. The output of the Clamp and AGC connects to one ADC that digitizes the composite input or the Y signal of the S-Video input. The second ADC digitizes the C signal when decoding S-video signal ...
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... The default selection for NTSC/PAL is comb filter. The characteristics of the band-pass filter is shown in the filter curve section. In the case of comb filter, the TW9903 separates luma (Y) and chroma ( NTSC composite video signal using a proprietary 2H adaptive comb filter. The filter uses a two-line buffer. Adaptive logic combines the upper-comb and the lower-comb results based on the signal changes among the previous, current and next lines ...
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... Automatic standard detection The TW9903 has build-in automatic standard discrimination circuitry. The circuit uses burst -phase, burst-frequency and frame rate to identify NTSC, PAL or SECAM color signals. The standards that can be identified are NTSC (M), NTSC (4.43), PAL ( I), PAL (M), PAL (N), PAL (60) and SECAM (M) ...
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... TW9903 Video Format support TW9903 supports all common v ideo formats as shown in Table 1. The video decoder needs to be programmed appropriately for each of the composite video input formats. Table 1. Video Input Formats Supported by the TW9903 Format NTSC-M NTSC-Japan (1) PAL- PAL-D PAL-H PAL-I ...
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... The decoded data is made available through CC_DATA and CC_STATUS registers that can be accessed through the 2-WIRE SERIAL MPU interface. Power Management The TW9903 can be put into power-down mode in which its clock is turned off for most of the circuits. The Y, C/Pr and Pb path can be separately powered down. Control Interface The TW9903 registers are accessed via 2 -WIRE SERIAL MPU interface ...
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... CBFLAG, and OE# as shown in Figure 2. In 8-bit output mode, Reg0x03[6] is “0”.In 16-bit output mode,Reg0x03[6] is “1”. The TW9903 outputs all pixel data and control signals synchronous with CLKX2 rising edge for both the 8-bit format and the 16bit format. The mapping of video data stream formats is shown in Table 2. When the output is configured for a 8-bit format, the data is output on pins VD[15:8] with 8 bits of chrominance data preceding 8 bits of luminance data for each pixel output ...
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... Clock and Control Signal Output The default output format of TW9903 is a synchronous 8-bit YCbCr 4:2:2 data format with separate syncs and flags. Video data is compliant with ITU-601format. HSYNC, VSYNC, HACTIVE, VACTIVE, LVALID (MPOUT), FIELD have the same output timings in both 8-bit output mode and 16-bit output modes ...
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... TW9903 HSYNC, VSYNC and FIELD The HSYNC and VSYNC output timing is VMI v1.4 compliant. The leading edge of HSYNC depends on the input video signal. The pulse width of HSYNC is programmable from 8-128 CLKX1 cycles. The leading edge of VSYNC also depends on the video input. It typically occurs on the low period of first serration pulse of the video signal ...
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... TW9903 INPUT HSYNC VSYNC FIELD INPUT HSYNC VSYNC FIELD Figure 7a. HSYNC, VSYNC and FIELD timing for NTSC field transition INPUT HSYNC VSYNC FIELD INPUT HSYNC VSYNC FIELD Figure 7b. HSYNC, VSYNC and FIELD timing for PAL(B,D,G,H,I) field transition TECHWELL, INC ...
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... HACTIVE, if HA_EN is set to “0’, TW9903 doesn ’t output video HACTIVE. During those lines that VACTIVE is high and LVALID is low, if VSCTL is set to “1”, TW9903 outputs video HACTIVE. If VSCTL is set to “0”, TW9903 doesn’t output video HACTIVE. In VBI enable mode (Reg0x19[7]=1), VBI HACTIVE has higher priority than video HACTIVE in VBI output line ...
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... TW9903 VACTIVE VACTIVE is used to indicate the start of active video line. When the line count in each field matches the VDELAY register setting, VACTIVE is asserted ...
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... TW9903 outputs Y invalid data 0x00 and CbCr invalid data 0x00. In 8-bit output mode, the CbCr invalid data is output first and then Y invalid data. TW9903 outputs only even number invalid data in invalid period during HACTIVE active time. TW9903 always outputs CbCr and Y 2-byte pair format data as valid data or invalid data ...
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... TW9903 These are illustrated in Figure 11a, 11b, 11c, 11d, 11e, and 11f Figure 11b. 8-bit DVALID second format timing ...
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... CLKX1 is high. Because TW9903 always outputs 2-byte pair format data on both valid pixel time and invalid pixel time. TW9903 outputs Cb data as the first valid CbCr data during video HACTIVE active time in 8-bit output mode. In 16-bit output mode, TW9903 outputs Cb data as the first valid CbCr data on VD[7:0] pins in video HACTIVE active time ...
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... HACTIVE. EAV code is generated on 4 CLKX2 clock timing after the trailing edge of HACTIVE. 8-bit output mode is normally used in ITU-R BT.656 mode. But even if TW9903 is in 16-bit output mode, if MODE is set to “1”, TW9903 output 4 bytes SAV/EAV code on VD[15:0] pins and the rest of HACTIVE non active period will be filled by Y 0x10 data and CbCr 0x80 data optionally ...
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... SAV, 1 – EAV Down-scaling and Cropping The TW9903 provides two methods to reduc e the amount of output video pixel data, downscaling and cropping. The downscaling provides full video image at lower resolution. Cropping provides only a portion of the video image output. All these mechanisms can be controlled independently to yield maximum flexibility in the output stream ...
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... HSCALE = [(640/320)] * 256 = 512 = 0x200 In this case, with total resolution of 768 per line, the HACTIVE should have a value of 640. The vertical scaling determines the number of vertical lines output by the TW9903. The vertical scaling register (VSCALE 12-bit register, which is the concatenation of a 4-bit register SCALE_HI and an 8 -bit register VSCALE_LO ...
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... TW9903 HDELAY + HACTIVE < Total number of pixels per line. For NTSC output at 13.5 MHz pixel rate, the total number of pixels is 858. The HDELAY should be set to 106 and HACTIVE set to 720. For PAL output at 13.5 MHz rate, the total number of pixels is 864. The HDELAY should be set to 108 and HACTIVE set to 720. ...
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... Vertical Blanking Interval or VBI portion of the video signal. TW9903 VBI Overview In the default configuration of the TW9903, the VBI region of the video signal is treated the same way as the real image signal. It will decode this region of signal was video by Y/C separation and horizontal scaling. The TW9903 can also be configured in a mode known as VBI raw data mode ...
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... TW9903 VBI Frame Output Mode In VBI frame output mode the TW9903 is generating VBI data all the time (i.e., there is no VBI active interval). In essence, the TW9903 is acting as an ADC continuously sampling the entire video signal at the crystal rate. The TW9903 generates HSYNC, VSYNC and FIELD timing signals in addition to the VBI data, but the DVALID, HACTIVE, and VACTIVE signals are all held high during VBI frame output operation ...
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... Each of these 2 bytes bit + odd parity ASCII character which represents text or control characters for positioning or display control. For the purposes EDS, only the Y component of the video signal is used. The TW9903 can be programmed to decode CC or EDS data by setting register 0x1A. Since the CC and EDS are independent, there could be one or both in a particular frame ...
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... TW9903 and even field Closed Captioning are enabled, it must be shorter than 4 times write per 1 frame cycle. Otherwise, FIFO will be in overflow condition theoretically. Typical FIFO Read flows are as follows. These flows are written similar to C language type. Case 1 : typical I2C Master with normal read cycle speed ...
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... Figure 17. One complete register write sequence via the serial bus interface The two wire serial bus interface is used to allow an external micro-controller to write control data to, and read control or other information from the TW9903 registers. SCLK is the serial clock and TECHWELL, INC. Device ID (1-7) ...
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... For both read and write, each byte is transferred MSB first, and the data bit is valid whenever SCLK is high. The TW9903 is operated as a bus slave device. It can be programmed to respond to one of two 7- bit slave device addresses by tying the SIAD (Serial Interface ADdress) pin ether to VDD or GND (See Table 5.). If the SIAD pin is tied to VDD, then the least significant bit of the 7-bit address is a “ ...
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... Test Modes The test mode is provided by the TMODE input pin. If this pin is de-asserted (low), the TW9903 is in its normal operating mode. When this pin is asserted (high), the TW9903 is in test mode, and the mode is controlled by TEST1 and TEST2 input pins as shown in Table 6. ...
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... TW9903 Filter Curves Decimation filter Chroma Band Pass Filter Curves NTSC - TECHWELL, INC ...
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... TW9903 Luma Notch Filter Curve for NTSC and PAL/SECAM Chrominance Low-Pass Filter Curve CBW Low - TECHWELL, INC. PAL/SECAM NTSC ...
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... TW9903 Horizontal Scaler Pre- Filter curves Low - HFLT[1:0]= Vertical Interpolation Filter curves TECHWELL, INC. High HFLT[1:0]=1 HFLT[1:0]=2 Med ...
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... TW9903 Peaking Filter Curves NTSC PAL TECHWELL, INC ...
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... TW9903 Control Register TW9903 Register SUMMARY Index 7 6 (HEX VDLOSS HLOCK SLOCK 02 * FC27 03 MODE LEN LVALID_ DVALID_ VACTIVE POL POL _POL 06 SRESET IREF VREF 07 VDELAY_HI PBW DEM PALSW 0D 0E VSCALE_HI SCURVE * SHLMT ...
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... WSSEN 35 ANCEN TOUTHA VIPCFG 36 37 CRCERR WSSFLD WKAIR 0x00 – Product ID Code Register (ID) Bit Function R/W The TW9903 Product ID code is 00011. 7 The revision number. 2-0 Revision R TECHWELL, INC WPGAIN AGCGAIN[7:0] PEAKWT CLMPL SYNCT PCLAMP VLCKO VMODE DETV CCEVENLINE(VSHT) ...
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... TW9903 0x01 – Chip Status Register (CSTATUS) Bit Function R Video not present. (sync is not detected in number of 7 VDLOSS R consecutive line periods specified by Misscnt register Video detected Horizontal sync PLL is locked to the incoming video source. 6 HLOCK Horizontal sync PLL is not locked. ...
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... TW9903 0x02 – Input Format (INFORM) Bit Function R/W 7 Reserved R Input crystal clock frequency is 27MHz. 6 FC27 0 = Square pixel mode. Must use 24.54MHz for 60Hz field rate source or 29.5MHz for 50Hz field rate source. R Component video decoding 5-4 IFSEL 01 = S-video decoding 00 = Composite video decoding R/W These two bits control the input video selection ...
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... TW9903 0x03 – Output Format Control Register (OPFORM) Bit Function R/W R CCIR601 compatible YCrCb 4:2:2 format with separate syncs 7 MODE and flags ITU-R-656 compatible data sequence format. R 8-bit YCrCb 4:2:2 output format based on CLKX2. 6 LEN 1 = 16-bit YCrCb 4:2:2 output format based on CLKX1. R DVALID is in the first format with VCLK used as data strobe. ...
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... TW9903 0x05 – Output Polarity Register (POLARITY) Bit Function R/W R LVALID pin is active high. 7 LVALID 1 = LVALID pin is active low. R DVALID pin is active high. 6 DVALID 1 = DVALID pin is active low. R VACTIVE pin is active high. 5 VACTIVE 1 = VACTIVE pin is active low. R CBFLAG pin is active high. 4 CBFLAG 1 = CBFLAG pin is active low ...
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... TW9903 0x06 – Analog Control Register (ACNTL) Bit Function R written to this bit resets the device to its default state but all 7 SRESET W register content remain unchanged. This bit is self-resetting. R Internal current reference 1. 6 IREF 1 = Internal current reference 2. R Internal voltage reference. ...
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... TW9903 0x08 – Vertical Delay Register, Low (VDELAY_LO) Bit Function R/W R/W These bits are bit the 10-bit Vertical Delay register. The 7-0 VDELAY_ two MSBs are in the CROP_HI register. It defines the number of LO lines between the leading edge of VSYNC and the start of the active video. 0x09 – ...
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... TW9903 0x0C – Control Register I (CNTRL1) Bit Function R/W R Wide Chroma BPF BW 7 PBW 0 = Normal Chroma BPF BW R/W Slock sensitivity 6 DEM R PAL switch sensitivity low. 5 PALSW 0 = PAL switch sensitivity normal. R The black level is 7.5 IRE above the blank level. 4 SET7 0 = The black level is the same as the blank level. ...
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... TW9903 0x0E – Scaling Register, High (SCALE_HI) Bit Function R/W R/W These bits are bit the 12-bit vertical scaling ratio register. 7-4 VSCALE_ HI R/W These bits are bit the 12-bit horizontal scaling ratio 3-0 HSCALE_ register. HI 0x0F – Horizontal Scaling Register, Low (HSCALE_LO) ...
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... TW9903 0x12 – SHARPNESS Control Register I (SHARPNESS) Bit Function R/W R/W This bit controls the sharpness filter center frequency. 7 SCURVE 0 = Normal 6 Reserved R/W 5-4 Reserved R/W R/W These bits control the amount of sharpness enhancement on the 3-0 SHARP luminance signals. There are 16 levels of control with '0' having no effect on the output image. 1 through 7 provides sharpness enhancement with '7' being the strongest ...
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... TW9903 0x15 – Hue Control Register (HUE) Bit Function R/W R/W These bits control the color hue. They have value from +96 7-0 HUE to -96 (00h). 0x16 – Sharpness Control Register II Bit Function R/W 7-4 SHLMT R/W These bits limit the maximum enhancement level regardless of the SHARP setting. The internal step size is 8. ...
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... TW9903 0x19 – VBI Control Register (VBICNTL) Bit Function R/W R VBI capture disabled. 7 VBI VBI capture enabled. R/W If LEN(Reg0x03[6]) is “1” 6 VBI Byte Order 0 = Pixel … on the VD[15:8] data bus, and pixel … on the VD[7:0] data bus Pixel … on the VD[7:0] data bus, and pixel … ...
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... TW9903 0x1A – CC/EDS Status Register (CC_STATUS) Bit Function R/W R Disable CCVALID interrupt pin. 7 CCVALID _EN 1 = Enable CCVALID interrupt pin. R EDS data is not transferred to the CC_DATA fifo. 6 EDS_EN 1 = EDS data is transferred to the CC_DATA fifo. R data is not transferred to the CC_DATA fifo. 5 CC_EN data is transferred to the CC_DATA fifo ...
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... TW9903 0x1C – Standard Selection (SDT) Bit Function R Idle 7 DETSTUS R Current standard invoked 6-4 STDNOW NTSC( PAL (B,D,G,H, SECAM 3 = NTSC4. PAL ( PAL (CN PAL Not valid R Disable the shadow registers. 3 ATREG 0 = Enable VACTIVE and HDELAY shadow registers value depending on standard ...
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... TW9903 0x1D – Standard Recognition (SDTR) Bit Function R/W R/W Writing 1 to this bit will manually initiate the auto format detection 7 ATSTART process. This bit is a self-resetting bit. R enable recognition of PAL60 disable recognition. R enable recognition of PAL (CN disable recognition. R enable recognition of PAL (M). ...
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... TW9903 0x1F – Test Control Register (TEST) Bit Function R/W R/W This register is reserved for testing purpose. In normal operation, 7-0 TEST only 0 should be written into this register Analog test mode. Y and C channel portion of the device can be tested in this mode. The Y channel ADC output can be obtained from HACTIVE, HSYNC and VD[15:8] for bit1, bit0 and bit9-2, respectively ...
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... TW9903 0x21 – Individual AGC Gain (IAGC) Bit Function R/W R/W These bits control the normal AGC loop maximum correction 7-4 NMGAIN value. R/W Peak AGC loop gain control. 3-1 WPGAIN R/W This bit is the MSB of the 9-bit register that controls the AGC gain 0 AGCGAIN when AGC loop is disabled. ...
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... TW9903 0x26 – Sync Miss Count Register (MISSCNT) Bit Function R/W R/W These bits set the thres hold for horizontal sync miss count 7-4 MISSCNT threshold. R/W These bits determine the Hsync detection window. 3-0 HSWIN 0x27 – Clamp Position Register (PCLAMP) Bit Function R/W R/W These bits set the clamping position from the PLL sync edge ...
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... TW9903 0x29 – Vertical Control II Bit Function R/W R/W Burst PLL center frequency control. 7-5 BSHT R/W Delayed Vsync position control in the increment of half line length 5-0 VSHT or CC decoding line number for even field. 0x2A – Color Killer Level Control Bit Function R/W R/W These bits control the amount of color killer hysteresis. ...
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... TW9903 0x2D – Miscellaneous Control Register I (MISC1) Bit Function R/W R Even field counter in special mode. 7 EVCNT 0 = Normal operation R/W Pre-filter selection for scaler 6-4 HFLT 1** = Bypass 000 = Auto selection based on Horizontal scaling ratio. 001 = Recommended for CIF size image 010 = Recommended for QCIF size image 011 = Recommended for ICON size image R Internal TBC enabled ...
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... TW9903 0x2F – Miscellaneous Control III (MISC3) Bit Function R/W R Enable noisy signal color killer function in NTSC mode. 7 NKILL 0 = Disabled. R Enable automatic noisy color killer function in PAL mode. 6 PKILL 0 = Disabled. R Enable automatic noisy color killer function in SECAM mode. 5 SKILL 0 = Disabled. R Normal output ...
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... TW9903 0x30 – Macrovision Detection Bit Function R/W 7 Reserved R 6 Reserved R 5 Reserved R 4 Reserved Macrovision color stripe detection may be un-reliable 3 CSBAD Macrovision AGC pulse detected. 2 MVCSN Not detected Macrovision color stripe protection burst detected. 1 CSTRIPE Not detected. ...
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... TW9903 0x32 – FILL DATA Bit Function R/W R/W Fill data value for missing data byte in double word sliced VBI data 7-0 FILLDATA output. 0x33 – VBI CNTL1 Bit Function R/W R/W VBI low pass filter selection. 7-6 VBILPF 00 = Disabled type1. R/W Sliced VBI data identification code. 5-0 SDID 0x34 – ...
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... TW9903 R/W These bits control the CC decoding line number in the case of Odd 4-0 CCODDLI field. NE 0x36 – Slice Level Bit Function R/W R/W These bits define the VBI data initial slice level. 7-0 SLICE 0x37 – WSS1 Bit Function R/W This is the CRC error indicator for 525-line WSS. ...
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... TW9903 0x3A – HFREF Bit Function R/W Horizontal line frequency indicator 7-0 HFREF R 0x3B – CLAMP MODE Bit Function R/W R/W Clamping mode control. 3-2 CLMD 0 = Sync top R/W Slice level control 1-0 PSP 0 = low TECHWELL, INC. Description Description 1 = Auto 2 = Pedestal 1 = Med 2 = high 60 Reset X Reset N/A 1 REV. 0. 06/02/2002 ...
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... SCLK 20 20 VDD 21 21 GND 22 22 VD[ VD[ VD[ VD[ VD[ VD[ VD[ VD[ VDD TECHWELL, INC. TW9903 61 TMODE 80 VSYNC 79 FIELD 78 GND 77 76 VDD SIAD1 75 74 VCOM TS2DP 73 AVDD 72 AGND 71 TS2DN 70 69 C_PbIN1 TADCP 68 67 C_PbIN0 AGND 66 65 AVDD VREFP 64 VQVD ...
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... TW9903 Pin Description This section provides a detailed description of each pin for the TW9903. The pins are arranged in functional groups according to their associated interface. The active state of the signal is determined by the trailing symbol at the end of the signal name. A "#" symbol indicates that the signal is active or asserted at a low voltage level. When "#" is not present after the signal name, the signal is active at the high voltage level ...
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... TW9903 Pin# I/O Pin Name 63 I, VQVD analog 49 I, CAGC Analog 68 I, TADCP analog 69 I, C_PbIN1 / analog TADCN 70 O, TS2DN analog 73 O, TS2DP analog Two Wire Interface Pins Pin# I/O Pin Name 19 I, SCLK LVTTL 18 I/OD, SDAT LVTTL 14 I, SIAD0 LVTTL 75 I, SIAD1 LVTTL ...
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... TW9903 Pin# I/O Pin Name LVTTL 94 O, VCLK LVTTL 98 I, OE# LVTTL 78 O, FIELD LVTTL 89 O, CBFLAG LVTTL 2–9 O, VD[15:8] LVTTL 22-29 I/O, VD[7:0] LVTTL 84 O, DVALID LVTTL 87 OD, CCVALID LVTTL 91 I, PDN LVTTL 86 O, VACTIVE LVTTL TECHWELL, INC. Description active or horizontal active signal via the Hactive register logical high during the active/viewable periods of the video stream ...
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... TW9903 Pin# I/O Pin Name 85 O, MPOUT LVTTL 80 I, TMODE LVTTL 16 I, TEST1 LVTTL 17 I, TEST2 LVTTL Clock Interface Pins Pin# I/O Pin Name 12 I XTI 13 O XTO 97 O, CLKx1 LVTTL 99 O, CLKx2 LVTTL Test Pins Pin# I/O Pin Name 34 I/O, TCK LVTTL 36 I/O, TMS LVTTL ...
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... TW9903 Power and Ground Pins Pin# I/O Pin Name 1, 10, 20, P VDD 30, 38, 76, 88, 92, 96 44, 48, P AVDD 60, 65, +3.3V 72 11, 21, G GND 31, 39, 77, 81, 90, 93, 95, 100 42, 47, G AGND 54, 56, 58, 61, 66, 71, 51 TECHWELL, INC. Description +3.3 V Power supply for digital circuitry. All VDD pins must be connected together as close to the device as possible ...
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... TW9903 Parametric Information AC/DC Electrical Parameters Table 7. Absolute Maximum Ratings Parameter AVDD (measured to AGND) V (measured to DGND) DD Voltage on any signal pin (See the note below) Analog Input Voltage Storage Temperature Junction Temperature Vapor Phase Soldering(15 Seconds) Stresses above those listed may cause permanent damage to the device. This is a stress rating only, and functional NOTE: operation at these or any other conditions above those listed in the operational section of this specification is not implied ...
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... TW9903 Parameter Digital Outputs Output High Voltage (I = –4 mA) OH Output Low Voltage ( mA) OL 3-State Current Output Capacitance Analog Input Analog Pin Input voltage Analog Pin Input Capacitance ADCs ADC resolution ADC integral Non -linearity ADC differential non-linearity ADC clock rate ...
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... TW9903 Output CLK CLKx1 CLKx2 CLKx1 Duty Cycle CLKx2 Duty Cycle CLKx2 to CLKx1 Delay CLKx1 to Data Delay CLKx2 to Data Delay CLKx1 (Falling Edge) to VCLK (Rising Edge) CLKx2 (Falling Edge) to VCLK (Rising Edge) Output Video Data 8-bit Mode (1) Data to VCLK (Rising Edge) Delay ...
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... Power-Up After power-up, the TW9903 registers have unknown values. The RST# pin must be asserted and released to bring all registers to its default values. After reset, the TW9903 data outputs are tri- stated. The OPFORM register should be written after reset to enable outputs desired. ...
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... MUX1 VD0-15 CIN0 Video Timing SIAD1 SIAD0 TMODE TEST1 TEST2 OEB TW9903 PDN VREFP MUXOUT VREFN YIN VCOM VQVD DVDD RST# DGND AVDD XTI AGND XTO Typical TW9903 External Circuitry 71 3.3/5V 1.5k 1.5k 3.3V 0.1uF GND Filtered 3.3V 0.1uF Isolated GND plane AGND DGND REV. 0. 06/02/2002 ...
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... TW9903 PCB Layout Considerations The PCB layout should be done to minimize the power and ground noise on the TW9903. This is done by good power de-coupling with minimum lead length on the de-coupling capacitors; well- filtered and regulated analog power input shielding and ground plane isolation. ...
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... Dimension D1 and E1 do include mold mismatch and are determined at datum plane. 2. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed. The maximum b dimension by more than 0.08mm dambar cannot be located on the lower radius or the lead root. TECHWELL, INC TW9903 Top View Millimeter Nom ...
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... Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed. The maximum b dimension by more than 0.08mm dambar cannot be located on the lower radius or the lead root. TECHWELL, INC TW9903 Top View Millimeter Nom. Max. ...