CH7205A-D Chrontel, CH7205A-D Datasheet
CH7205A-D
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CH7205A-D Summary of contents
Page 1
... HDTV sync signals. PLL Serial Port Control Timing NTSC/PAL CVBS, S-Video, Encode, DAC 3 YPbPr 480i/576i 480p/576p DAC 2 YPrPb DAC 1 DAC 0 MUX Four RGB 10-bit DAC's CH7205A GPIO[1:0] 2 Serial Clcok Serial Data RESET* DACA[3:0] 4 Video Switch DACB[3:1] 3 ISET 1 ...
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... Register Control...........................................................................................................................................19 3.1 Non-Macrovision Control Registers Index ..............................................................................................19 3.2 Non-Macrovision Control Registers Map................................................................................................21 3.3 Non-Macrovision Control Registers Description ....................................................................................22 4.0 Electrical Specifications ..............................................................................................................................38 4.1 Absolute Maximum Ratings ....................................................................................................................38 4.2 Recommended Operating Conditions ......................................................................................................38 4.3 Electrical Characteristics .........................................................................................................................39 4.4 Digital Inputs / Outputs............................................................................................................................39 4.5 AC Specifications ....................................................................................................................................40 4.6 Timing Information .................................................................................................................................41 5.0 Package Dimensions ....................................................................................................................................44 6.0 Revision History ..........................................................................................................................................45 2 Table of Contents 201-0000-047 CH7205A Rev. 1.7, 10/20/2003 ...
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... CHRONTEL 1 1.1 Package Diagram 1 D[1] 2 D[2] 3 D[3] 4 D[4] 5 DVDD 6 D[5] 7 D[6] 8 DGND 9 D[7] 10 D[8] D[9] 11 D[10] 12 201-0000-047 Rev. 1.7, 10/20/2004 CHRONTEL CH7205 Figure 2: 48-Pin LQFP Package CH7205A XI/FIN 34 AVDD 33 DVDD 32 RESET* 31 DGND 30 SPC 29 SPD 28 VDD 27 ISET 26 GND 25 Y/G 3 ...
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... This pin functions as the clock pin of the serial port and operates with inputs from 0 to VDDV. RESET* Reset * Input (Internal pull-up) When this pin is low, the device is held in the power-on reset condition. When this pin is high, reset is controlled through the serial port. 201-0000-047 CH7205A Rev. 1.7, 10/20/2003 ...
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... The output is driven from the DVDD supply. This output is valid with TV-Out operation. DVDD Digital Supply Voltage (3.3V) DGND Digital Ground VDDV I/O Supply Voltage (1.1V to 3.3V) AVDD PLL Supply Voltage (3.3V) AGND PLL Ground VDD DAC Supply Voltage (3.3V) GND DAC Ground CH7205A 5 ...
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... YPbPr ITU-R BT.601/656 TV Deinterlace (480p, 576p generation) YPbPr ITU-R BT.601/656 TV Interlace (480i, 576i generation) CVBS, ITU-R BT.601/656 TV Encoder S-Video (NTSC / PAL) CVBS, ITU-R BT.601/656 TV Encoder RGB (SCART format) TV Output Scaling Ratios Ratio Standard 9:8 NTSC 1/1 15:12 PAL 1/1 201-0000-047 CH7205A Described In section 2.1.2 2.1.1 2.1.1 2.1.1 Rev. 1.7, 10/20/2003 ...
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... Input Active Video Pixel Aspect Resolution Aspect Ratio 720x480i 4:3 720x576i 4:3 201-0000-047 Rev. 1.6, 10/03/2003 T H Min 6.73 63.5 14 Output Ratio Standard 9:8 720x480p 15:12 720x576p CH7205A Typ Max Unit 47.62 uS 63 Pixel clocks Pixel clocks 0 uS 0.5 PCK PCK 7 ...
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... The second XCLK/XCLK* waveform represents the input clock for the dual edge transfer (DDR) method. The timing requirements are given in section 4. RCA + 1 S-Video CVBS Y C CVBS SDTV CVBS 201-0000-047 CH7205A SCART CVBS Rev. 1.7, 10/20/2003 ...
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... CD STEP where XCMD is a number between 0 and 15 represented as a binary code t is the adjustment increment (see section 4.5) STEP The delay is also tabulated in Table 23. 201-0000-047 Rev. 1.6, 10/03/2003 between clock and data is given by the following formula XCMD[3:0] 15 CH7205A 9 ...
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... Figure 5: 12-bit Multiplexed Input Data Formats (IDFx = 0,1,2,3,4) Table 7: Multiplexed Input Data Formats (IDF = 0, 1) IDF = Format = Pixel # P0a P0b Bus Data D[11] G0[3] R0[7] D[10] G0[2] R0[6] D[9] G0[1] R0[5] D[8] G0[0] R0[4] D[7] B0[7] R0[3] D[6] B0[6] R0[2] D[5] B0[5] R0[1] D[4] B0[4] R0[0] D[3] B0[3] G0[7] D[2] B0[2] G0[6] D[1] B0[1] G0[5] D[0] B0[0] G0[4] 10 SAV P0a P0b P1a 0 12-bit RGB P1a P1b P0a G1[3] R1[7] G0[4] G1[2] R1[6] G0[3] G1[1] R1[5] G0[2] G1[0] R1[4] B0[7] B1[7] R1[3] B0[6] B1[6] R1[2] B0[5] B1[5] R1[1] B0[4] B1[4] R1[0] B0[3] B1[3] G1[7] G0[0] B1[2] G1[6] B0[2] B1[1] G1[5] B0[1] B1[0] G1[4] B0[0] 201-0000-047 CH7205A P1b P2a P2b 1 12-bit RGB P0b P1a P1b R0[7] G1[4] R1[7] R0[6] G1[3] R1[6] R0[5] G1[2] R1[5] R0[4] B1[7] R1[4] R0[3] B1[6] R1[3] G0[7] B1[5] G1[7] G0[6] B1[4] G1[6] G0[5] B1[3] G1[5] R0[2] G1[0] R1[2] R0[1] B1[2] R1[1] R0[0] B1[1] R1[0] G0[1] B1[0] G1[1] Rev. 1.7, 10/20/2003 ...
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... Y1[6] Cb2[6] Cr0[5] Y1[5] Cb2[5] Cr0[4] Y1[4] Cb2[4] Cr0[3] Y1[3] Cb2[3] Cr0[2] Y1[2] Cb2[2] Cr0[1] Y1[1] Cb2[1] Cr0[0] Y1[0] Cb2[0] 4 YCrCb 8-bit P1a P1b P2a 0 S[7] Cb2[7] 0 S[6] Cb2[6] 0 S[5] Cb2[5] 0 S[4] Cb2[4] 0 S[3] Cb2[3] 0 S[2] Cb2[2] 0 S[1] Cb2[1] 0 S[0] Cb2[0] CH7205A 3 RGB 5-5-5 P0b P1a P1b X G1[5] X R0[7] G1[4] R1[7] R0[6] G1[3] R1[6] R0[5] B1[7] R1[5] R0[4] B1[6] R1[4] R0[3] B1[5] R1[3] G0[7] B1[4] G1[7] G0[6] B1[3] G1[6] P2b P3a P3b Y2[7] Cr2[7] Y3[7] Y2[6] Cr2[6] Y3[6] Y2[5] Cr2[5] Y3[5] Y2[4] Cr2[4] Y3[4] Y2[3] Cr2[3] Y3[3] Y2[2] Cr2[2] ...
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... ITU-R BT.470 requirements, but will fall into a range of values due to the variety of clock frequencies used to support multiple operating modes. In order to minimize the hazard of ESD, a set of protection diodes MUST BE used for each DAC connecting to TV (Refer to AN-38 for details). 12 CH7205A 201-0000-047 Rev. 1.7, 10/20/2003 ...
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... CH7205A Duration (us) NTSC PAL 1.49 - 1.51 1.48 - 1.51 4.69 - 4.72 4.69 - 4.71 0.59 - 0.61 0.88 - 0.92 2.50 - 2.53 2 ...
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... Line vertical interval 270 265 267 268 269 266 269 265 266 267 268 270 201-0000-047 CH7205A 271 272 273 274 275 274 272 273 271 275 Rev. 1.7, 10/20/2003 ...
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... CHRONTEL BURST BLANKING INTERVALS Figure 8: Interlaced PAL Video Timing 201-0000-047 Rev. 1.6, 10/03/2003 START OF VSYNC FIELD 1 FIELD 2 FIELD 3 FIELD CH7205A 15 ...
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... Figure 9: NTSC Y (Luminance) Output Waveform (DACG = 0) Color/Level White 26.75 1.003 Yellow 24.62 0.923 Cyan 21.11 0.792 Green 18.98 0.712 Magenta 15.62 0.586 Red 13.49 0.506 Blue 10.14 0.380 Blank/ Black 8.00 0.300 Sync 0.00 0.000 Figure 10: PAL Y (Luminance) Video Output Waveform (DACG = 1) 16 Color bars: Color bar s: 201-0000-047 Rev. 1.7, CH7205A 10/20/2003 ...
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... Yellow/Blue 23.93 0.897 Peak Burst 19.21 0.720 Blank 15.24 0.572 Peak Burst 11.28 0.423 Yellow/Blue 6.56 0.246 Green/Magenta 3.81 0.143 Cyan/Red 2.97 0.111 Figure 12: PAL C (Chrominance) Video Output Waveform (DACG = 1) 201-0000-047 Rev. 1.6, 10/03/2003 Color bars: 3.579545 MHz Color Burst (9 cycles) Color bars: 4.433619 MHz Color Burst (10 cycles) CH7205A 17 ...
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... Peak Chrome 33.31 1.249 White 26.75 1.003 Peak Burst 11.97 0.449 Blank/Black 8.00 0.300 Peak Burst 4.04 0.151 Sync 0.00 0.000 Figure 14: Composite PAL Video Output Waveform (DACG = 1) 18 Color bars: 3.579545 MHz Color Burst (9 cycles) Color bars: 4.433619 MHz Color Burst (10 cycles) 201-0000-047 CH7205A Rev. 1.7, 10/20/2003 ...
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... SYO H/V sync direction control VSP V sync polarity control for XCM XCLK select for D[11:0] XCMD[3:0] Delay adjust between XCLK and D[11:0] XOSC[2:0] Crystal oscillator adjustments 201-0000-047 Rev. 1.6, 10/03/2003 CH7205A Address 49h 4Bh 48h 48h 48h 49h 4Ah 22h 22h 22h 14h 21h ...
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... Vertical blanking interval defeat VOF[1:0] TV-Out video format (s-video & composite, YPrPb or RGB) VOS[1:0] TV-Out video standard VP[8:0] TV-Out vertical position control YCV[1:0] Composite video luma bandwidth YSV[1:0] S-Video luma bandwidth 20 CH7205A 07h 1Dh 02h 08h 02h 10h-13h 10h 10h 02h 0Ch-0Fh 14h ...
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... SYNCO1 SYNCO0 Reserved BCOEN BCOP Reserved ResetIB ResetDB Reserved DACPD3 DACPD2 VID5 VID4 VID3 DID5 DID4 DID3 PEDL5 PEDL4 PEDL3 CH7205A Bit 2 Bit 1 Bit 0 Reserved Reserved Reserved Reserved Reserved Reserved YSV0 YCV1 YCV0 Reserved Reserved Reserved SAV2 SAV1 SAV0 HP2 HP1 ...
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... NTSC NTSC PAL-M Total Output Standard Frame Pixels/Line [TV Rate X Total Standard] [Hz] Lines/Frame 858x525 ITU-R BT.1358 / 30 EIA-770.1-A 864x625 ITU-R BT.1358 25 201-0000-047 CH7205A Symbol: DM Address: 00h Bits Reserved Reserved Reserved R/W R/W R Pixel Clock (MHz) 13.500000 13.500000 11 NTSC-J Pixel Clock [MHz] 13 ...
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... Reserved Reserved Reserved Reserved Reserved Reserved R/W R/W R Output Configuration YCrCb Composite, S-Video YPrPb SCART + Composite CVBWB CBW YSV1 R/W R/W R CH7205A Symbol: OF Address: 01h Bits R/W R/W R Symbol: VBW Address: 02h Bits YSV0 YCV1 YCV0 ...
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... SAV8 HP8 VP8 R/W R/W R SAV5 SAV4 SAV3 R/W R/W R 201-0000-047 CH7205A 10 11 4.050 6.720 2.660 4.410 Symbol: Misc Address: 03h Bits Reserved Reserved Reserved R/W R/W R Symbol: SAV Address: 04h Bits SAV2 ...
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... VP[8:0] value until the value zero is reached. The next step should set the register to TVLPF-1/2, and then decrement for further changes. 201-0000-047 Rev. 1.6, 10/03/2003 HP5 HP4 HP3 R/W R/W R VP5 VP4 VP3 R/W R/W R CH7205A Symbol: HP Address: 05h Bits HP2 HP1 HP0 R/W R/W R Symbol: VP Address: 06h Bits VP2 ...
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... Figure 15: Contrast Enhancement of the CH7205 BL5 BL4 BL3 R/W R/W R Reserved Reserved R/W R/W R 104 172 240 308 Yin n 201-0000-047 CH7205A Symbol: BL Address: 07h Bits BL2 BL1 BL0 R/W R/W R Symbol: CE Address: 08h Bits CE2 CE1 CE0 ...
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... TV PLL phase detector when the CH7205 is operating in clock master mode. The entire bit field, M[8:0], is 201-0000-047 Rev. 1.6, 10/03/2003 MEM0 N9 N8 R/W R/W R R/W R/W R CH7205A Symbol: TPC Address: 09h Bits PLLCPI PLLCAP R/W R/W R Symbol: PLLM Address: 0Ah Bits R/W R/W R/W ...
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... Symbol: Address: Bits FSCI# FSCI# FSCI# R/W R/W R/W 201-0000-047 CH7205A Symbol: PLLN Address: 0Bh Bits R/W R/W R 9-bits (hex) 0x21 0x21 0x1F 0x1F FSCI 0Ch –0Fh 8 each 2 ...
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... PAL-M PAL-M “Normal Dot “Normal Dot Crawl” Crawl” (dec) (hex) 568,782,819 0x21E6EFE3 PAL-N “Normal Dot Crawl” 569,807,942 CIV25 CIV24 CIVC1 CH7205A Symbol: CIVC Address: 10h Bits CIVC0 PALN CIVEN R R/W R ...
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... CIV# CIV# CIV R/W R/W R M/S* R/W R/W R 201-0000-047 CH7205A Symbol: CIV Address: 11h –13h Bits: 8 each CIV# CIV# CIV Symbol: HDTVM Address: 14h Bits HDTV R/W R/W R Symbol: ...
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... STEP STEP STEP STEP STEP STEP CH7205A Symbol: IC Address: 1Dh Bits XCMD0 R/W R/W R XCLK ahead of Data , XCLK ahead of Data , XCLK ahead of Data , XCLK ahead of Data , XCLK ahead of Data ...
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... GPIOL0 Reserved Reserved R/W R/W R SYO VSP HSP R/W R/W R 201-0000-047 CH7205A Symbol: GPIO Address: 1Eh Bits POUTE POUTP R/W R/W R Symbol: IDF Address: 1Fh Bits ...
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... XOSC2 (bit 6) of register CD contains the MSB value for the XOSC (crystal oscillator gain control) word. The entire bit field, XOSC[2:0], is comprised of this bit plus XOSC[1:0] contained in the DAC Control register (address 21h, bits 7-6). 201-0000-047 Rev. 1.6, 10/03/2003 Reserved DACT3 DACT2 R CH7205A Symbol: CD Address: 20h Bits DACT1 DACT0 SENSE ...
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... BCO[2:0] (bits 2-0) of register BCO select the signal output at the BCO pin, according to the table below Reserved SYNCO1 SYNCO0 DACG1 R/W R/W R BCOEN BCOP R/W R/W R 201-0000-047 CH7205A Symbol: DC Address: 21h Bits DACG0 DACBP R/W R/W R Symbol: BCO Address: 22h Bits ...
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... Cosine ROM MSB 110 VGA Vertical Sync 111 TV Vertical Sync ResetIB ResetDB R/W R/W R Test Pattern No test pattern – Input data is used Color Bars Horizontal Luminance Ramp Horizontal Luminance Ramp CH7205A Symbol: RST Address: 48h Bits Reserved TSTP1 TSTP0 R/W R/W R ...
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... DAC 1 powered down, DACs DAC 2 powered down, DACs DAC 3 powered down, DACs All circuitry is powered down except serial port VID5 VID4 VID3 201-0000-047 CH7205A Symbol: PM Address: 49h Bits TVPD R/W R/W R Symbol: ...
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... NTSC-J and YPrPb. 201-0000-047 Rev. 1.6, 10/03/2003 DID5 DID4 DID3 PEDL5 PEDL4 PEDL3 R/W R/W R CH7205A Symbol: DID Address: 4Bh Bits DID2 DID1 DID0 Symbol: PEDL Address: 4Fh Bits PEDL2 ...
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... Recommended Operating Conditions Symbol Description AVDD PLL Power Supply Voltage VDD DAC Power Supply Voltage DVDD Digital Power Supply Voltage VDDV I/O Power Supply Voltage R Output load to DAC Outputs L 38 CH7205A Min Typ Max -0.5 5.0 GND – 0.5 VDD + 0.5 Indefinite 0 85 -65 150 150 260 ...
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... Min 10 Test Condition Min 1.0 GND-0.5 0.25 Vref+0.25 GND-0.5 DVDD=3.3V 2.7 DVDD=3.3V GND-0 0 -0.4mA DVDD-0 3.2mA 0.4mA VDDV-0 3 MISC CH7205A Typ Max Units 10 10 bits 33 200 0.06 mA Typ Max Unit 0.4 V VDD + 0 DVDD+0.5 V Vref-0.25 V VDD + 0.5 V 0.6 V 5.0 ...
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... Output Fall Time (20% - 80%) t De-skew time increment STEP 40 Test Condition Min < 1.2ns XCLK = XCLK* to 0.35 D[11:0 Vref D[11:0 0.5 Vref to XCLK = XCLK* 15pF load DVDD, VDDV = 3.3V 15pF load DVDD, VDDV = 3.3V 50 201-0000-047 CH7205A Typ Max Unit 1. Rev. 1.7, 10/20/2003 ...
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... Hold Time: D[11:0 XCLK, XCLK XCLK & XCLK* rise/fall time w/15pF load t2 D[11:0 rise/fall time w/ 15pF load 201-0000-047 Rev. 1.6, 10/03/2003 VGA Line t2 CH7205A P0a P0b P1a P1b P2a P2b t2 Min Typ Max Unit see section 4.5 see section 4.5 ...
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... Pout Output Rise Time R t Pout Output Fall Time F t1 XCLK & XCLK* rise/fall time w/15pF load t2 D[11:0 rise/fall time w/15pF load VGA Line t2 201-0000-047 CH7205A P0a P0b P1a P1b P2a P2b t2 Min Typ ...
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... Pout (when configured as outputs) Output Fall Time F t1 XCLK & XCLK* rise/fall time w/15pF load t2 D[11:0] rise/fall time w/15pF load Hold time: t3 P-OUT to HSYNC, VSYNC delay 201-0000-047 Rev. 1.6, 10/03/2003 64 PIXELS 1 VGA Line CH7205A P0a P0b P1a P1b P2a P2b t2 Min Typ ...
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... CHRONTEL 5 ACKAGE IMENSIONS Table of Dimensions No. of Leads mm Milli- MIN 9 7 meters MAX 44 Figure 19: 48 Pin LQFP Package SYMBOL 0.17 1.35 0.05 0.5 0.27 1.45 0.15 201-0000-047 CH7205A 0.45 0.09 0 1.00 0.75 0.20 7 Rev. 1.7, 10/20/2003 ...
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... Updated Electrical Characteristics Updated pin package Removed RGB output for VGA monitor Removed non-interlaced input Removed description for RGB bypass Removed modes 48 and 60 Removed modes 48, 60, 61, and 62 Removed modes 48 and 60 Updated Ordering Information section to include lead-free and tape and reel information. CH7205A 45 ...
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... Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably expect to result in personal injury or death. Part Number CH7205A-D CH7205A-DF CH7205A-D-TR CH7205A-DF-TR 2004 Chrontel, Inc. All Rights Reserved. Printed in the U.S.A. 46 Disclaimer ORDERING INFORMATION ...