A14100A Actel Corporation, A14100A Datasheet

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A14100A

Manufacturer Part Number
A14100A
Description
Manufacturer
Actel Corporation
Datasheet

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RadTolerant FPGAs
Features
General Characteristics
High Density and Performance
Product Family Profile
Table 1 •
October 2004
© 2004 Actel Corporation
Device
Capacity
Logic Modules
User I/Os (Maximum)
Performance
Packages (by Pin Count)
System Gates
Logic Gates
ASIC Equivalent Gates
PLD Equivalent Gates
TTL Equivalent Package
20-Pin PAL Equivalent Packages
S-Modules
C-Modules
System Speed (Maximum)
CQFP
• Tested Total Ionizing Dose (TID) Survivability Level
• No Single Event Latch-Up Below a Minimum LET
• Packages: 84-Pin, 132-Pin, 172-Pin, 196-Pin, and
• Offered as Class B and E-Flow (Actel Space Level
• QML Certified Devices
• 100% Military Temperature Tested (–55°C to
• 4,000 to 20,000 Logic Equivalent Gates
• 2,000 to 10,000 ASIC Equivalent Gates
• Up to 85 MHz Internal Performance
(Linear Energy Transfer) Threshold of 80 MeV-cm
for All RT (RadTolerant) Devices
256-Pin Ceramic Quad Flat Pack
Flow)
+125°C)
RadTolerant Family
RT1020
20 MHz
6,000
4,000
2,000
5,000
547
N/A
547
50
20
69
84
2
/mg
RT1280A
40 MHz
24,000
16,000
20,000
8.000
1,232
200
624
608
140
172
80
Easy Logic Integration
• Up to 60 MHz System Performance
• Up to 228 User I/Os
• Up to Four Fast, Low-Skew Clock Networks
• Nonvolatile, User Programmable
• Pin-Compatible Commercial Devices Available for
• Highly
• 100% Resource Utilization with 100% Pin-Locking
• Secure Programming Technology Prevents Reverse
• Permanently Programmed
• Unique In-System Diagnostic and Verification
Prototyping
Automatic Place-and-Route
Engineering and Design Theft
Power-Up
Capability with Silicon Explorer
RT1425A
60 MHz
7,500
5,000
2,500
6,250
132
310
160
150
100
60
25
Predictable
See Actel’s website for the latest version of the datasheet
RT1460A
60 MHz
18,000
12,000
15.000
6,000
196
150
848
432
416
168
60
Performance
for
RT14100A
60 MHz
30,000
20,000
10,000
25,000
1,377
Operation on
256
250
100
697
680
228
with
v 3 . 1
100%
i

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A14100A Summary of contents

Page 1

... C-Modules User I/Os (Maximum) Performance System Speed (Maximum) Packages (by Pin Count) CQFP October 2004 © 2004 Actel Corporation • MHz System Performance • 228 User I/Os • Four Fast, Low-Skew Clock Networks 2 /mg Easy Logic Integration • Nonvolatile, User Programmable • ...

Page 2

... RT1020 RT1280A = 16,000 Gates—RadTolerant ACT 2 RT1425A = 5,000 Gates—RadTolerant ACT 3 RT1460A = 12,000 Gates—RadTolerant ACT 3 RT14100A = 20,000 Gates—RadTolerant ACT 3 A1020B A1280A A1425A A1460A A14100A = 20,000 Gates—ACT 3 Device Resources FPGA Device Type Logic Modules RT1020/A1020B 547 RT1280A/A1280A 1,232 RT1425A/A1425A ...

Page 3

... Ceramic Quad Flat Pack (CQFP) RT14100A Device 256-Pin Ceramic Quad Flat Pack (CQFP) A14100A Device (Prototyping Use) 256-Pin Ceramic Quad Flat Pack (CQFP) Note: Contact your Actel sales representative for product availability. Availability: ✔ = Available, – Symbol = Not Planned * Speed Grade: –1 = Approx. 15% faster than Standard ...

Page 4

... RT1280A, A1280A Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 RT1425A, A1425A Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 RT1460A, A1460A Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 RT14100A, A14100A Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 Package Pin Assignments 84-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 132-Pin CQFP ...

Page 5

... These devices also have fully pin- and function- compatible commercially-equivalent devices for easy and inexpensive prototyping. The A1425A-CQ132C is used for the RT1425A, the A1460A-CQ196C is used for the RT1460A, and the A14100A-CQ256C is used for the RT14100A. Radiation Survivability Actel Total dose results are summarized in two ways. The first ...

Page 6

RadTolerant FPGAs QML Certification Actel has achieved full QML certification, demonstrating that quality management, procedures, processes, and controls are in place and comply with MIL-PRF-38535, the performance specification used by the Department of Defense for monolithic integrated certification is an ...

Page 7

The S-module, shown in Figure implement high-speed sequential functions within a single logic module. The S-module implements the same combinatorial logic function as the C-module while adding a sequential element. The sequential element can be configured as either a D-type ...

Page 8

RadTolerant FPGAs The RT1020 Logic Module The RT1020 logic module is an 8-input, 1-output logic circuit chosen for the wide range of functions it implements and for its efficient use of interconnect routing resources (Figure 1-3). Figure 1-3 • RT1020 ...

Page 9

Long segments are uncommitted and can be assigned during routing. Each output segment spans four channels (two above and two below), except near the top and bottom of the ...

Page 10

RadTolerant FPGAs 1 Table 1-2 • Actel Extended Flow Step Screen 2 1. Wafer Lot Acceptance 3 2. Destructive In-Line Bond Pull 3. Internal Visual 4. Serialization 5. Temperature Cycling 6. Constant Acceleration 7. Particle Impact Noise Detection 8. Radiographic ...

Page 11

Absolute Maximum Ratings Stresses beyond those listed in this table may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the recommended operating conditions. ...

Page 12

RadTolerant FPGAs Package Thermal Characteristics The device junction to case thermal characteristic is θ and the junction to ambient air characteristic is θ thermal characteristics for θ are shown with two ja different air flow rates. Max. junction temp. (°C) ...

Page 13

... Measurements are made over a range of frequencies at a fixed value of V capacitance is frequency-independent, so the results can be used over a wide range of operating conditions. Equivalent capacitance values are shown in RT1020, RT1280A, A1020B A1280A 3.7 5.8 22.1 12.9 32.1 23.8 ) 4.6 3.9 n/a n/a n/a n/a v3.1 RadTolerant FPGAs 1-4 active CC . Equivalent CC Table 1-7. RT1425A, A1425A, RT1460A, A1460A, RT14100A, A14100A 6.7 7.2 10.4 1.6 0.7 0.9 1-9 ...

Page 14

... Table 1-8 • Fixed Capacitance Values for Actel FPGAs (pF) m Device Type n RT1020, A1020B p RT1280A, A1280A RT1425A, A1425A RT1460A, A1460A RT14100A, A14100A Table 1-9 • Fixed Clock Loads (s1/s2 – ACT 3 Only) RT1020, A1020B, Device Type RT1425A, A1425A RT1460A, A1460A RT14100A, A14100A v3 0 outputs 1 EQCR q1 routed_Clk1 * ...

Page 15

... Average First Routed Array Clock Rate (f q1 Average Second Routed Array Clock Rate (f Average Dedicated Array Clock Rate ( Average Dedicated I/O Clock Rate ( RT1425A, A1425A, RT1460A, A1460A, RT14100A, A14100A Logic Modules (m) Input Switching (n) Outputs Switching (p) First Routed Array Clock Loads ( Second Routed Array Clock Loads (q ) ...

Page 16

RadTolerant FPGAs Input Delay I/O Module t INYL = 3.9 ns ARRAY CLOCK t CKH = 6 MAX = 55 MHz Figure 1-6 • RT1020, A1020B Timing Model Input Delays I/O Module t INYL = 3 ...

Page 17

... CLOCK t HCKH = 5 HMAX = 100 MHz t IOCKH = 3.5 ns I/O CLOCK (pad-to-pad) F IOMAX = 100 MHz Note: *Values shown for RT14100A –1 at worst-case military conditions. Figure 1-8 • RT1425A, A1425A, RT1460A, A1460A, RT14100A, A14100A Timing Model* Predicted Internal Delays Routing Delays Combinatorial Logic Module t RD1 = 1 RD4 = 2 ...

Page 18

RadTolerant FPGAs Parameter Measurement V CC GND In 50% 50 1.5V PAD 1. DLH t DHL Figure 1-9 • Output Buffer Delays Load 1 (Used to measure propagation delay) To the Output under Test Figure ...

Page 19

... Figure 1-13 • Flip-Flops and Latches (RT1280A, A1280A SUD G, CLK E Q CLR D represents all data functions involving A, B, and S for multiplexed flip-flops. Figure 1-14 • Flip-Flops and Latches (RT1425A, A1425A, RT1460A, A1460A, RT14100A, A14100A) D PRE Y E CLK CLR (Positive Edge Triggered ...

Page 20

RadTolerant FPGAs CLK PAD Figure 1-15 • Input Buffer Latches (R1280A, A1280A Figure 1-16 • Output Buffer Latches (RT1280A, A1280A PAD IBDL G CLKBUF PAD G t INSU t HEXT CLK t SUEXT D PAD ...

Page 21

RT1020, A1020B Timing Characteristics Table 1-10 • RT1020, A1020B Logic and Input Modules Worst-Case Military Conditions, V Parameter Logic Module Propagation Delays t Single Module PD1 t Dual Module Macros PD2 t Sequential Clock Latch G ...

Page 22

RadTolerant FPGAs Table 1-11 • RT1020, A1020B Output Module Worst-Case Military Conditions, V Parameter Global Clock Network t Input Low to High CKH t Input High to Low CKL t Minimum Pulse Width High PWH t Minimum Pulse Width Low ...

Page 23

RT1280A, A1280A Timing Characteristics Table 1-12 • RT1280A, A1280A Logic Module Worst-Case Military Conditions, V Parameter Description Logic Module Propagation Delays t Single Module PD1 t Sequential Clock-to Latch G-to Flip-Flop (Latch) Reset-to-Q RS Logic Module ...

Page 24

RadTolerant FPGAs Table 1-13 • RT1280A, A1280A Input Module Worst-Case Military Conditions, V Parameter Description Input Module Propagation Delays t Pad-to-Y HIGH INYH t Pad-to-Y LOW INYL t G-to-Y HIGH INGH t G-to-Y LOW INGL Input Module Predicted Routing Delays ...

Page 25

Table 1-14 • RT1280A, A1280A Output Module Worst-Case Military Conditions, V Parameter Description 1 TTL Output Module Timing t Data-to-Pad HIGH DLH t Data-to-Pad LOW DHL t Enable-to-Pad Z to HIGH ENZH t Enable-to-Pad Z to LOW ENZL t Enable-to-Pad ...

Page 26

RadTolerant FPGAs RT1425A, A1425A Timing Characteristics Table 1-15 • RT1425A, A1425A Logic and Input Modules Worst-Case Military Conditions, V Parameter Description Logic Module Propagation Delays t Internal Array Module PD t Sequential Clock Asynchronous Clear to ...

Page 27

Table 1-16 • RT1425A, A1425A Logic and Input Modules Worst-Case Military Conditions, V Parameter Description I/O Module Sequential Timing t Input F-F Data Hold (w.r.t. IOCLK Pad) INH t Input F-F Data Setup (w.r.t. IOCLK Pad) INSU t Input Data ...

Page 28

RadTolerant FPGAs Table 1-17 • RT1425A, A1425A Clock Networks Worst-Case Military Conditions, V Parameter Description Dedicated (Hard-Wired) I/O Clock Network t Input Low to High IOCKH (Pad to I/O Module Input) t Minimum Pulse Width High IOPWH t Minimum Pulse ...

Page 29

RT1460A, A1460A Timing Characteristics Table 1-18 • RT1460A, A1460A Logic and Input Modules Worst-Case Military Conditions, V Parameter Description Logic Module Propagation Delays t Internal Array Module PD t Sequential Clock Asynchronous Clear to Q CLR ...

Page 30

RadTolerant FPGAs Table 1-19 • RT1460A, A1460A I/O and Output Modules Worst-Case Military Conditions, V Parameter Description I/O Module Sequential Timing t Input F-F Data Hold (w.r.t. IOCLK Pad) INH t Input F-F Data Setup (w.r.t. IOCLK Pad) INSU t ...

Page 31

Table 1-20 • RT1460A, A1460A Clock Networks Worst-Case Military Conditions, V Parameter Description Dedicated (Hard-Wired) I/O Clock Network t Input Low to High (Pad to I/O Module Input) IOCKH t Minimum Pulse Width High IOPWH t Minimum Pulse Width Low ...

Page 32

... RadTolerant FPGAs RT14100A, A14100A Timing Characteristics Table 1-21 • RT14100A, A14100A Logic and Input Modules Worst-Case Military Conditions, V Parameter Description Logic Module Propagation Delays t Internal Array Module PD t Sequential Clock-to Asynchronous Clear-to-Q CLR Logic Module Predicted Routing Delays t FO=1 Routing Delay RD1 ...

Page 33

... Table 1-22 • RT14100A, A14100A I/O and Output Modules Worst-Case Military Conditions, V Parameter Description I/O Module Sequential Timing t Input Flip-Flop Data Hold INH t Input Flip-Flop Data Setup INSU t Input Data Enable Hold IDEH t Input Data Enable Setup IDESU t Output Flip-Flop Data Hold OUTH t Output Flip-Flop Data Setup ...

Page 34

... RadTolerant FPGAs Table 1-23 • RT14100A, A14100A Clock Networks Worst-Case Military Conditions, V Parameter Description Dedicated (Hard-Wired) I/O Clock Network t Input LOW to HIGH IOCKH (Pad to I/O Module Input) t Minimum Pulse Width HIGH IOPWH t Minimum Pulse Width LOW IOPWL t Minimum Asynchronous Pulse Width IOSAPW t Maximum Skew ...

Page 35

... In the RT1020, A1020B, RT1280, and A1280A devices, unused I/O pins are automatically driven LOW. In the RT1425, A1425A, RT1460, A1460A, A14100A devices, unused I/O pins are automatically tristated. IOCLK Dedicated (Hard-Wired) I/O Clock (Input) Not applicable for RT1020, A1020B, RT1280A and A1280A. TTL clock input for I/O modules. This input is directly wired to each I/O module, offering clock speeds independent of the number of I/O modules being driven ...

Page 36

...

Page 37

Package Pin Assignments 84-Pin CQFP Pin #1 Index Figure 2-1 • 84-Pin CQFP (Top View ...

Page 38

RadTolerant FPGAs 84-Pin CQFP Pin A1020B RT1020 Number Function Function I/O I/O 3 I/O I/O 4 I/O I/O 5 I/O I/O 6 I/O I/O 7 GND GND 8 GND GND 9 I/O I/O 10 I/O I/O ...

Page 39

CQFP 132131130129128127126125124 Pin #1 Index Figure 2-2 • 132-Pin CQFP (Top View) 107106105104103 ...

Page 40

RadTolerant FPGAs 132-Pin CQFP Pin A1425A RT1425A Number Function Function GND GND 3 SDI, I/O SDI, I/O 4 I/O I/O 5 I/O I/O 6 I/O I/O 7 I/O I/O 8 I/O I/O 9 MODE MODE 10 ...

Page 41

CQFP Pin A1425A RT1425A Number Function Function 106 GND GND 107 108 I/O I/O 109 I/O I/O 110 I/O I/O 111 I/O I/O 112 I/O I/O 113 I/O I/O 114 I/O I/O 115 I/O I/O ...

Page 42

RadTolerant FPGAs 172-Pin CQFP 172 171 170 169 168 167 166 165 164 Pin #1 Index ...

Page 43

CQFP Pin A1280A RT1280A Number Function Function 1 MODE MODE 2 I/O I/O 3 I/O I/O 4 I/O I/O 5 I/O I/O 6 I/O I/O 7 GND GND 8 I/O I/O 9 I/O I/O 10 I/O I/O 11 I/O ...

Page 44

RadTolerant FPGAs 172-Pin CQFP Pin A1280A RT1280A Number Function Function 106 GND GND 107 108 GND GND 109 110 111 I/O I/O 112 I/O I/O 113 V V ...

Page 45

CQFP 196 195 194 193 192 191 190 189 188 Pin #1 Index Figure 2-4 • 196-Pin CQFP (Top View) 155 154 ...

Page 46

RadTolerant FPGAs 196-Pin CQFP Pin A1460A RT1460A Number Function Function 1 GND GND 2 SDI, I/O SDI, I/O 3 I/O I/O 4 I/O I/O 5 I/O I/O 6 I/O I/O 7 I/O I/O 8 I/O I/O 9 I/O I/O 10 ...

Page 47

CQFP Pin A1460A RT1460A Number Function Function 106 I/O I/O 107 I/O I/O 108 I/O I/O 109 I/O I/O 110 111 112 GND GND 113 I/O I/O 114 I/O I/O 115 ...

Page 48

RadTolerant FPGAs 256-Pin CQFP 256 255 254 253 252 251 250 249 248 Pin #1 Index Figure 2-5 • 256-Pin CQFP (Top View) ...

Page 49

... I/O 48 I/O I/O 49 I/O I/O 50 I/O I/O 51 I/O I/O 52 I/O I/O 53 I/O I/O 54 I/O I/O 55 I/O I/O 56 I/O I/O 57 I/O I/O 58 I/O I/O 59 GND GND 60 I/O I/O 61 I/O I/O 62 I/O I/O 63 I/O I/O 64 I/O I/O 65 I/O I/O 66 I/O I/O 67 I/O I/O 68 I/O I/O 69 I/O I/O 70 I/O I/O v3.1 RadTolerant FPGAs 256-Pin CQFP Pin A14100A RT14100A Number Function Function 71 I/O I/O 72 I/O I/O 73 I/O I/O 74 I/O I/O 75 I/O I/O 76 I/O I/O 77 I/O I/O 78 I/O I/O 79 I/O I/O 80 I/O I/O 81 I/O I/O 82 I/O I/O 83 I/O I/O 84 I/O I/O 85 I/O I/O 86 I/O I/O 87 I/O I/O 88 I/O I/O 89 I/O I/O 90 PRB, I/O PRB, I/O 91 GND GND GND ...

Page 50

... I/O I/O 164 I/O I/O 165 I/O I/O 166 I/O I/O 167 I/O I/O 168 I/O I/O 169 I/O I/O 170 I/O I/O 171 I/O I/O 172 I/O I/O 173 I/O I/O 174 175 GND GND v3.1 256-Pin CQFP Pin A14100A RT14100A Number Function Function 176 GND GND 177 I/O I/O 178 I/O I/O 179 I/O I/O 180 I/O I/O 181 I/O I/O 182 I/O I/O 183 I/O I/O 184 I/O I/O 185 I/O I/O 186 I/O I/O 187 I/O I/O 188 IOCLK, I/O IOCLK, I/O ...

Page 51

... I/O I/O 231 I/O I/O 232 I/O I/O 233 I/O I/O 234 I/O I/O 235 I/O I/O 236 I/O I/O 237 I/O I/O 238 I/O I/O 239 I/O I/O 240 GND GND 241 I/O I/O 242 I/O I/O 243 I/O I/O 244 I/O I/O 245 I/O I/O 256-Pin CQFP Pin A14100A RT14100A Number Function Function 246 I/O I/O 247 I/O I/O 248 I/O I/O 249 I/O I/O 250 I/O I/O 251 I/O I/O 252 I/O I/O 253 I/O I/O 254 I/O I/O 255 I/O I/O 256 DCLK, I/O DCLK, I/O v3.1 RadTolerant FPGAs 2-15 ...

Page 52

...

Page 53

... The following pins changed in the • Pin 124 change to I/O for the A14100A and RT14100A devices. • Pin 127 changed to IOPCL for the A14100A and RT14100A devices. Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as " ...

Page 54

... Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel Corporation Actel Europe Ltd. 2061 Stierlin Court Dunlop House, Riverside Way Mountain View, CA Camberley, Surrey GU15 3YL 94043-4655 USA United Kingdom Phone 650.318.4200 Phone +44 (0)1276 401 450 Fax 650 ...

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