GL850A Genesys Logic, GL850A Datasheet

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GL850A

Manufacturer Part Number
GL850A
Description
Manufacturer
Genesys Logic
Datasheet

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Bonase Electronics (HK) Co., Limited Bonase Electronics (HK) Co., Limited
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GL850A
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Genesys Logic, Inc.
GL850A
USB 2.0
Low-Power
HUB Controller
Datasheet
Revision 1.70
Jan. 25, 2008

Related parts for GL850A

GL850A Summary of contents

Page 1

... Genesys Logic, Inc. GL850A USB 2.0 Low-Power HUB Controller Datasheet Revision 1.70 Jan. 25, 2008 ...

Page 2

... All trademarks are the properties of their respective owners. Office: Genesys Logic, Inc. 12F, No. 205, Sec. 3, Beishin Rd., Shindian City, Taipei, Taiwan Tel: (886-2) 8913-1888 Fax: (886-2) 6629-6168 http ://www.genesyslogic.com ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850A USB 2.0 Low-Power HUB Controller Page 2 ...

Page 3

... Modify Pin List and Pin Descriptions of EE_CS, EE_DI, EE_SK, p.11~12 Input Voltage for digital I/O(Ovcur1-4,Pself,Reset) pins,p.24 Add Modify 93C46 Configuration, Table 5.1, p.22 Modify Table 6.1-Maximum Ratings, p.24 Modify RESET# Setting, Ch5.2.1, p.18 Modify PGANG/SUSPND Setting, Ch5.2.2, p.19 Add Package Thermal Characteristics, Ch7.1, p.27 Modify GL850A 48 Pin List, Table 3.1, p.11 Page 3 ...

Page 4

... ONFIGURATION AND CHAPTER 6 ELECTRICAL CHARACTERISTICS............................... 23 6 AXIMUM ATINGS 6 PERATING ANGES 6 HARACTERISTICS 6 OWER ONSUMPTION CHAPTER 7 PACKAGE DIMENSION..................................................... 26 CHAPTER 8 ORDERING INFORMATION ............................................ 28 ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850A USB 2.0 Low-Power HUB Controller TABLE OF CONTENTS ................................................................................... 12 I/O S ....................................................... 17 ETTINGS ................................................................................. 23 ................................................................................ 23 ............................................................................ 23 ............................................................................ 24 Page 4 ...

Page 5

... F 3.1- - - - GL850A 48 P IGURE F 3.2- - - - GL850A 64 P IGURE F 4.1 – GL850A B IGURE F 5.1 – O IGURE PERATING IN F 5.2 – O IGURE PERATING IN F 5.3 – RESET# (E IGURE F 5.4 – P IGURE OWER ON SEQUENCE OF F 5.5 – T IGURE IMING OF F 5.6 – GANG M IGURE ODE F 5.7 – ...

Page 6

... T 3.1- - - - GL850A 48 P ABLE T 3.2 - - - - GL850A 64 P ABLE T 3 ABLE IN ESCRIPTIONS T 5.1 – 93C46 C ABLE ONFIGURATION T 6.1 – M ABLE AXIMUM T 6.2 – O ABLE PERATING T 6.3 – ABLE HARACTERISTICS T 6.4 – ABLE HARACTERISTICS OF T 6.5 – ABLE HARACTERISTICS OF T 6.6 – ...

Page 7

... Gang mode. Please refer the table in the end of this chapter for more detail. To fully meet the cost/performance requirement, GL850A is a single TT hub solution for the cost requirement. Genesys Logic also provides GL852 for multiple TT hub solution to target on systems which require higher performance for full/low-speed devices, like docking station, embedded system … ...

Page 8

... Internal power-fail detection for ESD recovery • 64/48-pin LQFP package • Applications: Stand-alone USB hub − PC motherboard USB hub, Docking of notebook − − Any compound device to support USB HUB function ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850A USB 2.0 Low-Power HUB Controller Page 8 ...

Page 9

... CHAPTER 3 PIN ASSIGNMENT 3.1 Pinouts Figure 3.1 ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850A USB 2.0 Low-Power HUB Controller GL850A - - - - G L850A 48 Pin LQFP Pinout Diagram Page 9 ...

Page 10

... Figure 3.2 ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850A USB 2.0 Low-Power HUB Controller - - - - G L850A 64 Pin LQFP Pinout Diagram Page 10 ...

Page 11

... B 9 DP1 AVDD P 12 AGND DM2 B ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850A USB 2.0 Low-Power HUB Controller - - - - Table 3.1 G L850A 48 Pin List 13 AGND P 25 AMBER4 DGND DVDD 16 AVDD P 28 RESET# ...

Page 12

... Individual/gang mode is strapped during this period. After the strapping period, this pin will be set to output mode, and then output high for normal mode. B When GL850A is suspended, this pin will output low. *For detailed explanation, please see Chapter 5 Gang input:1, output: 0@normal, 1@suspend ...

Page 13

... DGND 38, 51,58,62 43,47 2,5~7, 10,13,16 24,27,30, 33 Note: Analog circuits are quite sensitive to power and ground noise. PCB layout must take care the power routing and the ground plane. For detailed information, please refer to GL850A Design Guideline. Notation: Type O Output I Input B Bi-directional B/I Bi-directional, default input ...

Page 14

... USPORT Transceiver UTMI REPEATER DSPORT1 Logic DSPORT Transceiver D- LED/ D+ OVCUR/ PWRENB Figure 4.1 – GL850A Block Diagram (single TT) ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850A USB 2.0 Low-Power HUB Controller 12MHz PLL FRTIMER x40, x10 USPORT SIE Logic TT (Transaction Translator) REPEATER / TT Routing Logic ...

Page 15

... The functionality of FRTIMER is described in section 11.2 of USB Specification Revision 2.0. 5.1.4 µ the micro-processor unit of GL850A 8-bit RISC processor with 2K ROM and 64 bytes RAM. It operates at 6MIPS of 12Mhz clock to decode the USB command issued from host and then prepares the data to respond to the host. In addition, C can handle GPIO (general purpose I/O) settings and reading content of EEPROM to support high flexibility for customers of different configurations of hub ...

Page 16

... TT implements the control logic defined in section 11.14 ~ 11.22 of USB specification Revision 2.0. TT basically handles the unbalanced traffic speed between the USPORT (operating in HS) and DSPORTS (operating in FS/LS) of hub. GL850A adopts the single TT architecture to provide the most cost effective solution. Single TT shares the same buffer control module for each downstream port. GL852 adopts multiple TT architecture to provide the most performance effective solution ...

Page 17

... Configuration and I/O Settings 5.2.1 RESET# Setting GL850A integrates in the pull-up 1.5K resister of the upstream port. When RESET# is enabled, the internal 1.5K pull-up resister will be disconnected to the 3.3V power. To meet the requirement (p.141) of the USB 2.0 specification, pull-up resister should be disconnected while lacking of USB cable power (Vbus) ...

Page 18

... Figure 5.3 – RESET# (External Reset) setting and application GL850A internally contains a power on reset circuit. The power on sequence is depicted in the next picture. To fully control the reset process of GL850A, we suggest the reset time applied in the external reset circuit should longer than that of the internal reset circuit. ...

Page 19

... SELF/BUS Power Setting GL850A can operate under bus power and conform to the power consumption limitation completely (suspend current < 2.5 mA, normal operation current < 100 mA). By setting PSELF, GL850A can be configured as a bus-power or a self-power hub. ©2000-2008 Genesys Logic Inc. - All rights reserved. ...

Page 20

... Power Self 0: Power Bus 5.2.4 LED Connections GL850A controls the LED lighting according to the flow defined in section 11.5.3 of Universal Serial Bus Specification Revision2.0 . Both manual mode and Automatic mode are supported in GL850A. When GL850A is globally suspended, GL850A will turn off the LED to save power. ...

Page 21

... PRODUCT LENGTH: offset 40h contains the length of product string. Values of product string is contained from 41h~6Fh. 9. SERIAL NUMBER LENGTH: offset 70h contains the value of serial number string. Values of serial number string is contained after offset 71h. ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850A USB 2.0 Low-Power HUB Controller Table 5.1 – 93C46 Configuration ...

Page 22

... EE_DO Figure 5.9 – Schematics Between GL850A and 93C46 GL850A firstly verifies the check sum after power on reset. If the check sum is correct, GL850A will take the configuration of 93C46 as part of the descriptor contents. To prevent the content of 93C46 from being over-written, amber LED will be disabled when 93C46 exists. ...

Page 23

... Leakage current for pads with internal pull up or pull I OLK down resistor R Pad internal pull down resister DN R Pad internal pull up resister UP ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850A USB 2.0 Low-Power HUB Controller Table 6.1 – Maximum Ratings Parameter Table 6.2 – Operating Ranges Parameter Parameter =8Ma OL =8Ma OH Min. ...

Page 24

... Driver output resistance for USB 2.0 HS DRV 6.4 Power Consumption Table 6.6 – DC Supply Current Symbol Active ports I SUSP ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850A USB 2.0 Low-Power HUB Controller Parameter of 1. 15K to GND ) L Parameter of 1. Condition Host Device Suspend *2 F ...

Page 25

... No Active *1: 48/64-pin package types *2: F: Full-Speed, H: High-Speed ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850A USB 2.0 Low-Power HUB Controller Page 25 ...

Page 26

... CHAPTER 7 PACKAGE DIMENSION Figure 7.1 – GL850A 48 Pin LQFP Package ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850A USB 2.0 Low-Power HUB Controller GL850A AAAAAAAGAA YWWXXXXXXXX Page 26 ...

Page 27

... Figure 7.2 – GL850A 64 Pin LQFP Package ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850A USB 2.0 Low-Power HUB Controller GL850A AAAAAAAGAA YWWXXXXXXXX Page 27 ...

Page 28

... Part Number GL850A-MSNXX 64-pin LQFP GL850A-MNNXX 48-pin LQFP GL850A-MSGXX 64-pin LQFP GL850A-MNGXX 48-pin LQFP ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850A USB 2.0 Low-Power HUB Controller Table 8.1 – Ordering Information Package Normal/Green Normal Package Normal Package Green Package Green Package Version Status ...

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