VT86C926 ETC-unknow, VT86C926 Datasheet
VT86C926
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VT86C926 Summary of contents
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... VT86C926 A MAZON PCI E THERNET DATA SHEET (Preliminary) DATE : June 27, 1995 VIA TECHNOLOGIES, INC. C ONTROLLER ...
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... Via Technologies Incorporated. The VT86C926 may only be used to identify products of Via Technologies. All trademarks are the properties of their respective owners. Disclaimer Notice: No license is granted, implied or otherwise, under any patent or patent rights of Via Technologies ...
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... VIA T ECHNOLOGIES VT86C926 A MAZON PCI E C THERNET ONTROLLER * Single chip Ethernet controller for PCI bus interface * Software compatible to NE2000+, NE2000 * Support 35ns access time SRAM * Integrated 10BaseT TP interface -- Built-in pre-equalization circuitry for transmitter -- smart squelch circuit with programmable threshold for receiver ...
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... VIA ECHNOLOGIES IAGRAM . VT86C926 RELIMINARY ...
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... PCICLK provides timing for all transactions on PCI and is an input pin to every PCI device. INTA asynchronous signal which is used to request an interrupt When PCIRST# is asserted low, the VT86C926 chip performs an internal system hardware reset. PCIRST# may be asynchronous to CLK when asserted or deasserted recommended that the deassertion be synchronous to guarantee clean and bounce free edge ...
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... After the link is up, it will turn on for at least 786ms and then become a normal receiver indicator. Collision/Jabber LED: An open drain active low output. Normally off. It turns on for minimum 25ms whenever VT86C926 detects a collision retriggerable. During jabber state it stays on. N.C. ...
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... VT86C926 controller via the memory support data bus. Note 1: The Chip Select of external buffer RAM is always enabled. Memory Support Bus Write: Strobes data from VT86C926 controller into the external RAM via the memory support data bus. A 100K pull- down device is connected. ...
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... PCI Plug&Play compatability and Early Interrupt Receive/Transmit. The VT86C926 integrates the entire bus interface of PCI systems. Setting hardware jumpers or software configures the VT86C926 bus interface. The VT86C926 also complies with PCI specification v2.0. and is software compatible to either the NE2000. The VT86C926 supports the 10BASE5 or 10BAE2 network interfaces via an external transciever connected to its AUI port ...
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... VIA ECHNOLOGIES 6. EEPROM I NTERFACE AND VT86C926 uses an 93C46 to store configuration data and Ethernet address. 6 .1. EEPROM Contents D15 3FH Reserved for 93C46 . . . . . . 10H 0FH 0EH 08H 07H SUBVID1 03H Checksum 02H Ethernet Address 5 01H Ethernet Address 3 00H Ethernet Address 1 Note 1. The word on location 03H is optional to user's application requirement. ...
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... I ECHNOLOGIES jumper DWID. Remember that as long as WTS is set to 1, the VT86C926 sends one word at one time with _IOCS16 asserted -- regardless of the data width of I/O instruction used. Note 4. Regardless of the data width of I/O instruction used, the VT86C926 sends one byte at one time with _IOCS16 deasserted and WTS set to 0 ...
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... EEPROM has been programmed and verified (remember to program the upper byte of 0EH with 73H), the user must give VT86C926 a power-on reset to return to normal operation and to read in the new data. The Direct Programming mode is mainly used for production to program every bit of the EEPROM. Once the upper byte of 0EH has been programmed with 073H and a power-on reset has been performed, there is ...
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... For more information, refer to EECSR. 6.6. Embedded Programming of EEPROM If the upper byte of 0FH of EEPROM has been programmed to 073H when VT86C926 is loading the EEPROM data during power-on reset, the EEPR bit of Signature Register will be set to prohibit the Direct Programming mode. However, the user can still program the configuration registers A, B, and C using the Embedded Programming mode by following the routine specified in the pseudo code below ...
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... R ONTROL AND TATUS EGISTERS * VT86C926 supports the control and status registers of DP8390 except those explained as follows. * VT86C926 supports all page 1 registers. Only part of Page 2 is supported. * VT86C926 supports Early Transmit Underrun (ETUN) * VT86C926 supports most of page 0 registers. * The meaning and use of 01H (CLAD0) and 02H (CLAD1) of page 0 is altered. ...
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... VIA ECHNOLOGIES 9. J UMPERED OPERATION SUPPORT 9.1 Fully Jumpered Operation Figure 8 below depicts this operation. options are selected by jumpers on the VT86C926 controller memory bus +5V Figure 3: Example of Jumper Configuration . NC In this configuration, most VT86C926 MD0 ISA I/O Base MD2 MD3 INT 0~f MD6 MD0 ...
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... In order for the transmit packet to be ready for transmission, it must follow the IEEE 820.3 specification (see figure 4). When the transmit packet is set up in the memory, the VT86C926 will initialize the packet starting address (TPSR) and the packet length (TPCR0, TBCR1). Then the PTX bit (transmit packet) of the command register will be set to start transmission ...
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... Process The VT86C926 will begin to check for the two consecutive ONEs than indicates the start of the frame delimiter (SFD) once VT86C926 dectects the active CTS signal and the ONE-ZERO preamble. After the detection of the SFD, the incoming data is deserialized and sent to the address filter (see figure 6). If the packet passes the address filter, then the packet is sent to the receive buffer ring through the DMA ...
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... Buffer Ram ( KB) Buffer # 1 Direction Buffer # 2 of Rotation Buffer # 3 Buffer # n Figure 7. Receive Buffer Ring . NC 256 Bytes Page Start Address Receive Buffer Ring Page Stop Address 17 P VT86C926 RELIMINARY 1 n Direction of Rotation ...
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... Length (L) Current Page Length (H) Register (after reception of first packe Direction of Rotation n-2 n-1 Figure 9. Packet Rejection 18 P VT86C926 RELIMINARY n Packet Status Begining Current Page Register Packet Ends Current Page Register (after reception of 3 packet 4 n-2 n-1 Begining Current Page Register Runt Packet, ...
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... Boundary Pointer Direction of Rotation Figure 11. Receive Buffer Ring Overwrite Protection . Remote DMA 2 Removes Packet 3 4 New Packets n-2 Arriving n-1 1 Remote DMA 2 Removes Packet n-2 n-1 New Packets Arriving VT86C926 RELIMINARY 1st Packet 2nd Packet Reception Aborted by NIC overflow 1st Packet 2nd Packet ...
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... Packet page interrupt Every time the receiver buffer is completly filled and a new buffer is requested, the VT86C926 will generate an interrupt with PRX of RSR unset as Packet header interrupt. Therefore, this kind of interrupt is issued every 256 byte time (~200us) until packet reception is done. The current byte count of packet being received can be accessed from register 01H (CLDC0) and 02H (CLDC1) of page 0 ...
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... ECHNOLOGIES 12.1.1. Enable Early Interrupt Mode To set the VT86C926 to Early Interrupt mode, set bit 3 (EIEN) of the Diagnostic Register to high. To set the VT86C926 back to normal mode, set bit 3 (EIEN) of the Diagnostic Register to low. You can set Early interrupt mode in any state. But your receive interrupt service routine must able to receive fragments from Ethernet data ...
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... In order to provide the VT86C926 with parallel processing between the ISA bus and Ethernet media, the VT86C926 must be set to detect early transmit error mode. This error may occur when the system's master device uses the ISA bus and then uses the data bus. ...
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... Figure 13: Early Transmit Error Detect Block Diagram Note: If Write_point<Read_point, then Early_Tx_Error. If Write_point>Read_point, then Stop_Local_DMA. P RELIMINARY Buffer RAM Data Bus Address Bus ETEN Local DMA Registers & Write_point Read_point Local_ DMA_ Status Early Transmit State Machine Stop_Local_DMA 23 VT86C926 State Machines ...
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... VIA T ECHNOLOGIES DITOR P S RODUCT PECIFICATIONS P D ROJECT ESIGNER F A INAL PPROVAL , ROJECT IGN FF HEET VT86C926 P R RELIMINARY ELEASE N S AME Alex Tsao Jeffery Chang Antonio Weng Tzu-Mu Lin 24 P VT86C926 RELIMINARY D IGNATURE ATE ...