CH7011A-TF Chrontel, CH7011A-TF Datasheet

no-image

CH7011A-TF

Manufacturer Part Number
CH7011A-TF
Description
Manufacturer
Chrontel
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CH7011A-TF
Manufacturer:
CHRONT
Quantity:
1 000
Part Number:
CH7011A-TF
Manufacturer:
CHRONT
Quantity:
20 000
CHRONTEL
CHRONTEL
CHRONTEL
CHRONTEL
CHRONTEL
Chrontel
1. F
• TV output supporting graphics resolutions up to
• Macrovision
• Programmable digital interface supports RGB and
• True scale rendering engine supports underscan in all
• Enhanced text sharpness and adaptive flicker
• Support for all NTSC and PAL formats
• Provides CVBS, S-Video and SCART (RGB) outputs
• TV Programmable power management
• 10-bit video DAC outputs
• Fully programmable through serial port
• Complete Windows and DOS driver support
• Low voltage interface support to graphics device
• Offered in a 64-pin LQFP package
201-0000-037 Rev 2.1, 10/20/2004
1024x768 pixels
YCrCb
TV output resolutions
removal with up to 7 lines of filtering
PIXEL DATA
EATURES
GPIO[1:0]
D[11:0]
INTERFACE
SERIAL PORT REGISTER &
7.1.L1 copy protection support
DIGITAL
SPC
INPUT
CONTROL BLOCK
SPD
CONVERTER
CH7011 TV Output Device
RGB-YUV
RESET*
Figure 1: Functional Block Diagram
DEFLICKERING
SYSTEM CLOCK
TRUE SCALE
XCLK/XCLK*
SCALING &
MEMORY
ENGINE
PLL
LINE
2. G
The CH7011 is a display controller device which
accepts a digital graphics input signal, and encodes and
transmits data to a TV output (analog composite, s-
video or RGB). The device accepts data over one 12-bit
wide variable voltage data port which supports five
different data formats including RGB and YCrCb.
The TV-Out processor will perform non-interlace to
interlace conversion with scaling and flicker filters, and
encode the data into any of the NTSC or PAL video
standards. The scaling and flicker filter is adaptive and
programmable to enable superior text display. Eight
graphics resolutions are supported up to 1024 by 768
with full vertical and horizontal underscan capability in
all modes. A high accuracy low jitter phase locked loop
is integrated to create outstanding video quality.
Support is provided for Macrovision
mode which enables driving a VGA CRT with the input
data.
YUV-RGB CONVERTER
H
ENERAL
TIMING & SYNC
GENERATOR
ENCODER
& FILTERS
NTSC/PAL
V
XI/FIN
D
XO
ESCRIPTION
CSYNC
P-OUT
10-bit
DAC’s
Four
BCO
CH7011A
and RGB bypass
CVBS (DAC3)
Y/G (DAC1)
C/R (DAC2)
CVBS/B
ISET
(DAC0)
1

Related parts for CH7011A-TF

CH7011A-TF Summary of contents

Page 1

... TRUE SCALE SCALING & NTSC/PAL DEFLICKERING ENCODER ENGINE & FILTERS SYSTEM CLOCK TIMING & SYNC PLL GENERATOR H V XCLK/XCLK* Figure 1: Functional Block Diagram CH7011A D ESCRIPTION ™ and RGB bypass CVBS (DAC3) Y/G (DAC1) Four 10-bit DAC’s C/R (DAC2) CVBS/B (DAC0) ISET BCO ...

Page 2

... VREF DGND 7 GPIO[1] 8 GPIO[ DGND 12 DVDD 13 RESET* 14 SPD 15 SPC 16 AGND 2 Chrontel CH7011 Figure 2: 64-Pin LQFP CH7011A SYNC 47 BCO / V SYNC 46 P-OUT 45 DVDDV 44 AVDD FIN 41 AGND 40 GND 39 CVBS / CVBS 35 ISET 34 GND 33 VDD ...

Page 3

... This pin functions as the clock pin of the serial port interface, and uses the DVDD supply. ISET Current Set Resistor Input This pin sets the DAC current. A 140 ohm resistor should be connected between this pin and GND (DAC ground) using short and wide traces. CH7011A 3 ...

Page 4

... The output is driven from the DVDD supply. D[11] - D[0] Data[11] through Data[0] Inputs These pins accept the 12 data inputs from a digital video port of a graphics controller. The levels are 0 to DVDDV, and the VREF signal is used as the threshold level. CH7011A The output is 201-0000-037 Rev 2.1, 10/20/2004 ...

Page 5

... The output clocks from this pad cell are able to have their polarities reversed under the control of the MCP bit Connect DVDD Digital Supply Voltage DGND Digital Ground DVDDV I/O Supply Voltage NC No Connect NC No Connect AVDD PLL Supply Voltage AGND PLL Ground VDD DAC Supply Voltage GND DAC Ground CH7011A (3.3V) (3.3V to 1.1V) (3.3V) (3.3V) 5 ...

Page 6

... In order to minimize the hazard of ESD, a set of protection diodes MUST BE used for each DAC connecting to TV (Refer to AN-38 for details Output Stan- Scaling Ratios Ratio dard 1:1 PAL 5/4, 1/1 1:1 NTSC 5/4, 1/1 PAL 5/4, 1/1 NTSC 5/4, 1/1 1:1 PAL 5/4, 1/1 1:1 NTSC 5/4, 1/1, 7/8 1:1 PAL 5/4, 1/1, 5/6 1:1 NTSC 1/1, 7/8, 5/6 9:8 NTSC 9:8 NTSC 1/1, 7/8, 5/6 15:12 PAL 15:12 PAL 1/1, 5/6, 5/7 1:1 PAL 1/1, 5/6, 5/7 1:1 NTSC 3/4, 7/10, 5/8 1:1 PAL 5/7, 5/8, 5/9 1:1 NTSC 5/8, 5/9, 1/2 CH7011A 1/1 1/1 201-0000-037 Rev 2.1, 10/20/2004 ...

Page 7

... Data D[11: Latch, Demux H,V H Latch VREF 201-0000-037 Rev 2.1, 10/20/2004 TV-PLL Timing Scaling TV Scan Conv 24 Encode Flicker Filt Figure 3: TV Output Modes CH7011A C/H SYNC ISET CVBS (DAC3) Four Y/G (DAC 1) 10-bit C/R (DAC 2) DAC's CVBS/B (DAC0 GPIO[1:0] Serial AS Port SPC SPD Control ...

Page 8

... The second XCLK/XCLK* waveform represents the input clock for the multiplexed data, clock at 1X pixel rate method. XCLK / XCLK * XCLK / XCLK * D[11: Regarding the CH7011 timing specifications, please see for details P-OUT 1 VGA Line Figure 4: Interface Timing CH7011A 201-0000-037 Rev 2.1, 10/20/2004 ...

Page 9

... Y1 byte refers to the next luminance sample, per CCIR-656 standards (the clock frequency is dependent upon the current mode, and is not 27MHz as specified in CCIR-656). All non-active pixels should RGB formats, and 16 for Y and 128 for CrCb in YCrCb formats. 201-0000-037 Rev 2.1, 10/20/2004 CH7011A 9 ...

Page 10

... Data) P[7:0] (Blue Data) Figure 5: Multiplexed Input Data Formats (IDF = SAV P0a P0b P0b[11:4] P0b[3:0], P0a[11:8] P0b[11:7], P0b[3:1] P0b[6:4], P0a[11:9], P0b[0], P0a[3] P0a[8:4], P0a[2:0] CH7011A P1a P1b P2a P2b P1b[11:4] P2b[11:4] P2b[3:0], P1b[3:0], P1a[11:8] P2a[11:8] P0a[7:0] P1a[7:0] P2a[7:0] P2b[11:7] P1b[11:7], P1b[3:1] ...

Page 11

... The following data is latched for IDF = 4 CRA (internal signal) P[23:16] (Y Data) P[15:8] (CrCb Data) P[7:0] (ignored) Figure 6: 201-0000-037 Rev 2.1, 10/20/2004 SAV P0a P0b Multiplexed Input Data Formats (IDF = CH7011A P1a P1b P2a P2b P0b[11:7] P1b[11:7] P2b[11:7] P2b[6:4], P0b[6:4], P0a[11:9] P1b[6:4], P1a[11:9] P2a[11:9] P0a[8:4] P1a[8:4] P2a[8:4] ...

Page 12

... RGB 5-6-5 P0b P1a P1b P0a R0[7] G1[4] R1[7] G0[5] R0[6] G1[3] R1[6] G0[4] R0[5] G1[2] R1[5] G0[3] R0[4] B1[7] R1[4] B0[7] R0[3] B1[6] R1[3] B0[6] G0[7] B1[5] G1[7] B0[5] G0[6] B1[4] G1[6] B0[4] G0[5] B1[3] G1[5] B0[3] 4 YCrCb 8-bit P0b P1a P1b P2a Y0[7] Cr0[7] Y1[7] Cb2[7] Y0[6] Cr0[6] Y1[6] Cb2[6] Y0[5] Cr0[5] Y1[5] Cb2[5] Y0[4] Cr0[4] Y1[4] Cb2[4] Y0[3] Cr0[3] Y1[3] Cb2[3] Y0[2] Cr0[2] Y1[2] Cb2[2] Y0[1] Cr0[1] Y1[1] Cb2[1] Y0[0] Cr0[0] Y1[0] Cb2[0] CH7011A 1 12-bit RGB (12-12) P0b P1a P1b R0[7] G1[4] R1[7] R0[6] G1[3] R1[6] R0[5] G1[2] R1[5] R0[4] B1[7] R1[4] R0[3] B1[6] R1[3] G0[7] B1[5] G1[7] G0[6] B1[4] G1[6] G0[5] B1[3] G1[5] R0[2] G1[0] R1[2] R0[1] B1[2] R1[1] R0[0] B1[1] R1[0] G0[1] B1[0] G1[1] 3 RGB 5-5-5 P0b P1a P1b X G1[5] X R0[7] G1[4] R1[7] R0[6] G1[3] R1[6] R0[5] B1[7] R1[5] R0[4] B1[6] R1[4] R0[3] B1[5] R1[3] G0[7] B1[4] G1[7] G0[6] B1[3] G1[6] P2b P3a P3b Y2[7] ...

Page 13

... S[3] Cb2[ S[2] Cb2[ S[1] Cb2[ S[0] Cb2[0] Level (mV) NTSC PAL 287 300 0 0 287 300 287 300 287 300 340 300 340 300 340 300 CH7011A P2b P3a P3b Y2[7] Cr2[7] Y3[7] Y2[6] Cr2[6] Y3[6] Y2[5] Cr2[5] Y3[5] Y2[4] Cr2[4] Y3[4] Y2[3] Cr2[3] Y3[3] Y2[2] Cr2[2] Y3[2] Y2[1] Cr2[1] Y3[1] Y2[0] Cr2[0] Y3[0] Duration (uS) NTSC PAL 1.49 - 1.51 1.48 - 1.51 4.69 - 4.72 4.69 - 4.71 ...

Page 14

... CHRONTEL Figure 7: NTSC / PAL Composite Output CH7011A 201-0000-037 Rev 2.1, 10/20/2004 ...

Page 15

... CH7011A 271 272 273 274 275 268 268 270 270 271 271 ...

Page 16

... FIE LD 4 FIE LD 4 312 313 314 315 316 317 312 313 314 315 316 ° ° ° ° ° ° CH7011A 321 322 323 318 319 320 321 322 323 6 ...

Page 17

... Green 18.98 Magenta 15.62 Red 13.49 Blue 10.14 Blank/ Black 8.00 Sync 0.00 Figure 11: PAL Y (Luminance) Video Output Waveform (DACG = 1) 201-0000-037 Rev 2.1, 10/20/2004 Color bars: V 1.000 0.925 0.801 0.726 0.608 0.533 0.415 0.340 0.287 0.000 Color bars: V 1.003 0.923 0.792 0.712 0.586 0.506 0.380 0.300 0.000 CH7011A 17 ...

Page 18

... Green/Magenta 26.68 1.000 Yellow/Blue 23.93 0.897 Peak Burst 19.21 0.720 Blank 15.24 0.572 Peak Burst 11.28 0.423 Yellow/Blue 6.56 0.246 Green/Magenta 3.81 0.143 Cyan/Red 2.97 0.111 Figure 13: PAL C (Chrominance) Video Output Waveform (DACG = 1) 18 Color bars: (9 cycles) Color bars: 4.433619 MHz Color Burst (10 cycles) CH7011A 201-0000-037 Rev 2.1, 10/20/2004 ...

Page 19

... Color/Level V Peak Chrome 33.31 1.249 White 26.75 1.003 Peak Burst 11.97 0.449 Blank/Black 8.00 0.300 Peak Burst 4.04 0.151 Sync 0.00 0.000 Figure 15: Composite PAL Video Output Waveform (DACG = 1) 201-0000-037 Rev 2.1, 10/20/2004 Color bars: 3.579545 MHz Color Burst (9 cycles) Color bars: 4.433619 MHz Color Burst (10 cycles) CH7011A 19 ...

Page 20

... DAC gain control DACBP DAC bypass XOSC[1:0] Crystal oscillator adjustments 20 . The serial port uses only the SPC clock to latch data into registers, ™ links is not changed) ™ links is not changed) ™ Link, DACT3, DACT2, DACT1, DACT0, SENSE) CH7011A 201-0000-037 Rev 2.1, 10/20/2004 ...

Page 21

... Calculated sub-carrier control (hysteresis, CIV[25:0] Calculated sub-carrier increment value read out CIVPN Select PAL-N when in a CIV mode MEM[2:0] Memory sense amp reference adjust VBID Vertical blanking interval defeat PLLCPI TV-Out PLL charge pump current control PLLCAP TV-Out capacitor control 201-0000-037 Rev 2.1, 10/20/2004 CH7011A 21 ...

Page 22

... VSP HSP Reserved DACT3 DACT2 SYNCO1 SYNCO0 SHF0 BCOEN BCOP ResetIB ResetDB TV DACPD3 DACPD2 VID5 VID4 VID3 DID5 DID4 DID3 CH7011A Bit 2 Bit 1 Bit 0 SR2 SR1 SR0 YFFT0 YFFNT1 YFFNT0 YSV0 YCV1 YCV0 TE2 TE1 TE0 SAV2 SAV1 SAV0 HP2 HP1 ...

Page 23

... PAL 1400x1000 1024x768 PAL 1024x768 1400x1125 PAL 1024x768 1160x840 NTSC 1024x768 1160x945 NTSC 1168x1050 1024x768 NTSC 720x576 864x625 PAL 720x480 858x525 NTSC CH7011A Symbol: DM Address: 00h Bits SR2 SR1 R/W R/W R can be supported C Scaling Percent Pixel Clock Overscan ...

Page 24

... CBW YSV1 R/W R/W R CH7011A 11 NTSC-J Symbol: FF Address: 01h Bits YFFT0 YFFNT1 YFFNT0 R/W R Symbol: VBW Address: 02h Bits YSV0 YCV1 YCV0 R/W R 201-0000-037 Rev 2.1, 10/20/2004 ...

Page 25

... CH7011A 10 11 3.540 5.880 4.430 7.350 3.020 5.010 3.700 6.140 4.750 7.870 6.080 10.100 4.010 6.660 4.970 8.240 4.220 7.000 5 ...

Page 26

... SAV8 HP8 VP8 R/W R/W R SAV5 SAV4 SAV3 R/W R/W R HP5 HP4 HP3 R/W R/W R CH7011A Symbol: TE Address: 03h Bits TE2 TE1 R/W R Symbol: SAV Address: 04h Bits SAV2 SAV1 SAV0 R/W R Symbol: HP Address: ...

Page 27

... Rev 2.1, 10/20/2004 VP5 VP4 VP3 R/W R/W R BL5 BL4 BL3 R/W R/W R CH7011A Symbol: VP Address: 06h Bits VP2 VP1 R/W R Symbol: BL Address: 07h Bits BL2 BL1 R/W R/W ...

Page 28

... Yin IBI N9 R/W R Mode PLLCAP Value CH7011A 308 376 444 Symbol: TPC Address: 09h Bits PLLCPI PLLCAP R/W R/W R 201-0000-037 Rev 2.1, 10/20/2004 512 0 R/W 0 ...

Page 29

... Rev 2.1, 10/20/2004 R/W R/W R R/W R/W R CH7011A Symbol: PLLM Address: 0Ah Bits R/W R Symbol: PLLN Address: 0Bh Bits R/W R R/W 1 ...

Page 30

... PAL, 5 1024x768, PAL, 5 1024x768, NTSC, 5 1024x768, NTSC, 5 1024x768, NTSC, 1 720x576, PAL, 1 720x480, NTSC, 1 FSCI# FSCI# FSCI# R/W R/W R/W CH7011A N M 10- 9-bits bits 142 63 214 647 313 302 89 126 33 75 ...

Page 31

... CIV25 CIV24 CIVC1 R/W R/W R CH7011A PAL-M “Normal Dot Crawl” 762,524,467 622,468,953 573,798,541 463,452,668 645,523,358 521,384,251 451,866,351 622,468,953 544,660,334 508,349,645 553,305,736 484,142,519 451,866,351 469,245,826 428,083,911 391,038,188 525,878,943 467,447,949 417,821,626 ...

Page 32

... XCLK is twice the pixel frequency (single edge clocking mode CIV# CIV# CIV# R/W R/W R M/S* R/W CH7011A Symbol: CIV Address: 11h – 13h Bits: 8 each CIV# CIV# CIV# R/W R Symbol: ...

Page 33

... Bits 7-6 of register GPIO control the direction of the GPIO pins. A value of ‘1’ sets the corresponding GPIO pin to an input, and a value of ‘0’ sets the corresponding pin to an output. 201-0000-037 Rev 2.1, 10/20/2004 XCMD3 XCMD2 XCMD1 R/W R/W R R/W R/W R CH7011A Symbol: IC Address: 1Dh Bits XCMD0 R/W R Symbol: GPIO Address: 1Eh Bits: 8 ...

Page 34

... TV. Again, a “1” indicates a valid connection, a “0” indicates an unconnected output SYO VSP HSP R/W R/W R DACT3 DACT2 CH7011A Symbol: IDF Address: 1Fh Bits IDF2 IDF1 IDF0 R/W R Symbol: CD Address: 20h Bits: 5 ...

Page 35

... SHF0 BCOEN BCOP R/W R/W R BCO[2:0] Buffered Clock Output 100 (for test use only) 101 (for test use only) 110 VGA Vertical Sync 111 TV Vertical Sync CH7011A Symbol: DC Address: 21h Bits DACG1 DACG0 DACBP R/W R Symbol: BCO Address: 22h ...

Page 36

... Reserved Reserved TYPE: R/W R/W DEFAULT: 0 Register PM controls which circuitry within the CH7011 is operating, according to Table 22 below ResetIB ResetDB R/W R DACPD3 DACPD2 DACPD1 DACPD0 R/W R/W R CH7011A Symbol: TSTP Address: 48h Bits RSA TSTP1 TSTP0 R/W R Symbol: PM Address: 49h Bits ...

Page 37

... Full Power Down All circuitry is powered down except serial port VID5 VID4 VID3 DID5 DID4 DID3 CH7011A Symbol: VID Address: 4Ah Bits VID2 VID1 VID0 Symbol: DID Address: 4Bh Bits ...

Page 38

... DAC’s Enabled I VDD I AVDD I DVDD DVDDV (1.8V) current (15pF load) 38 Min - 0.5 1 GND - 0 Min 3.1 3.1 3.1 1 VDD, AVDD, DVDD = 3.3V ± 5%) A Min 10 CH7011A Typ Max Units 5.0 V VDD + 0.5 V Indefinite Sec 70 C 150 C 150 C 260 C 245 C 225 C The temperature 5V can 0. Typ Max Units 3 ...

Page 39

... 2.0 mA 2.7 GND-0.5 Vref+0.25 GND-0.5 DVDD=3.3V 2.7 DVDD=3.3V GND-0 0 -0.4mA VDD-0 3.2mA 400 uA DVDDV-0 3 refers to GPIOx, AS and RESET* inputs, GPIOx, MISCA V - refers to P-OUT output. MISCB CH7011A Typ Max Unit 0.4 V DVDD+0.5 V 1.4 V DVDD+0.5 V Vref-0.25 V VDD + 0 ...

Page 40

... Single-ended Clock: (XCLK =VREF) to (D[11:0 & VREF) t4 Hold time: Differential Clock: (XCLK = XCLK*) to (D[11:0 & VREF) Single-ended Clock: (XCLK =VREF) to (D[11:0 & VREF) t5 D[11:0 & DE rise/fall time w/15pF load PIXELS 1 VGA Line t5 CH7011A t4 t3 P0a P0b P1a P1b P2a P2b t5 t3 Min Typ Max Unit ...

Page 41

... Hold time: Differential Clock: (XCLK = XCLK*) to (D[11:0 & VREF) Single-ended Clock: (XCLK =VREF) to (D[11:0 & VREF) t5 D[11:0 & DE rise/fall time w/15pF load 201-0000-037 Rev 2.1, 10/20/2004 PIXELS 1 VGA Line t5 CH7011A P0a P0b P1a P1b P2a P2b t5 t3 Min ...

Page 42

... Single-ended Clock: (XCLK =VREF) to (D[11:0 & VREF) t5 D[11:0 & DE rise/fall time w/15pF load t6 Hold time: P-OUT to HSYNC, VSYNC delay t7 (P-OUT=VREF) to (XCLK =XCLK*) delay PIXELS 1 VGA Line t5 t2 CH7011A P0a P0b P1a P1b P2a P2b t5 t3 Min Typ Max ...

Page 43

... Dimension B: Top Package body size may be smaller than bottom package size by as much as 0.15 mm. 3. Dimension B does not include allowable mold protrusions up to 0.25 mm per side. 201-0000-037 Rev 2.1, 10/20/2004 SYMBOL 0.17 1.35 0.05 0.50 0.27 1.45 0.15 CH7011A LEAD CO-PLANARITY E .004 “ 0.45 0.09 0 1.00 0.75 0. ...

Page 44

... Register 07h 44 Description First official release of CH7011A datasheet, rev. 1.0 1. New document format, which is organized with chapters and all the chapter titles and sub-titles, figures and tables are book-marked. 2. Correct default setting and TBD values. 3. Change Power management register explanation format. 4. Change 3.3 voltage supply to 3.3/3.6 v. ...

Page 45

... Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably expect to result in personal injury or death. Part number CH7011A-T CH7011A-T-TR CH7011A-TF CH7011A-TF-TR 2004 Chrontel, Inc. All Rights Reserved. Printed in the U.S.A. 201-0000-037 Rev 2.1, 10/20/2004 Disclaimer ORDERING INFORMATION ...

Related keywords