M12L16161A-7T ETC ETC, M12L16161A-7T Datasheet

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M12L16161A-7T

Manufacturer Part Number
M12L16161A-7T
Description
512K x 16Bit x 2Banks Synchronous DRAM
Manufacturer
ETC ETC
Datasheet

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512K x 16Bit x 2Banks Synchronous DRAM
FEATURES
PIN CONFIGURATION (TOP VIEW)
Elite Semiconductor Memory Technology Inc.
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Dual banks operation
MRS cycle with address key programs
-
-
-
All inputs are sampled at the positive going edge
of the system clock
Burst Read Single-bit Write operation
DQM for masking
Auto & self refresh
32ms refresh period (2K cycle)
CAS Latency (2 & 3 )
Burst Length (1, 2, 4, 8 & full page)
Burst Type (Sequential & Interleave)
V
DQ0
DQ1
V
DQ2
DQ3
V
DQ4
DQ5
V
DQ6
DQ7
V
LDQM
WE
CAS
RAS
CS
BA
A10/AP
A0
A1
A2
A3
V
DD
SSQ
DDQ
SSQ
DDQ
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
ORDERING INFORMATION
M12L16161A-4.3T
M12L16161A-5T
M12L16161A-5.5T
M12L16161A-6T
M12L16161A-7T
M12L16161A-8T
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
GENERAL DESCRIPTION
P.1
nous high data rate Dynamic RAM organized as
2 x 524,288 words by 16 bits, fabricated with
high performance CMOS technology. Synchro-
nous design allows precise cycle control with the
use of system clock I/O transactions are possible
on every clock cycle. Range of operating fre-
quencies, programmable burst length and pro-
grammable latencies allow the same device to be
useful for a variety of high bandwidth, high
performance memory system applications.
V
DQ15
DQ14
V
DQ13
DQ12
V
DQ11
DQ10
V
DQ9
DQ8
V
N.C/RFU
UDQM
CLK
CKE
N.C
A9
A8
A7
A6
A5
A4
V
Part NO.
SS
SSQ
DDQ
SSQ
DDQ
SS
The M12L16161A is 16,777,216 bits synchro-
(0.8 mm PIN PITCH)
(400mil x 825mil)
50PIN TSOP(II)
MAX Freq.
233MHz
200MHz
183MHz
166MHz
143MHz
125MHz
Publication Date : Jan. 2000
M12L16161A
Interface
LVTTL
Revision : 1.3u
TSOP(II)
Package
50

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M12L16161A-7T Summary of contents

Page 1

... Range of operating fre- quencies, programmable burst length and pro- grammable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ORDERING INFORMATION Part NO. M12L16161A-4.3T M12L16161A-5T M12L16161A-5.5T M12L16161A-6T M12L16161A-7T M12L16161A- DQ0 2 49 ...

Page 2

... SHZ Blocks data input when L(U)DQM active. Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. P.2 M12L16161A LWE LDQM DQi LDQM Publication Date : Jan. 2000 ...

Page 3

... 10ns acceptable. 10ns acceptable. + 0.3V, all other pins are not under test = 0V 1MHz) A Symbol Min C 2.5 CLK C 2 2.5 ADD C 4.0 OUT P.3 M12L16161A Unit Max Unit Note Max Unit 4 ...

Page 4

... (min), CLK V (max 0Ma, Page Burst CCD CCD t (min (min). CC P.4 M12L16161A (min)/V (max)=2.0V/0.8V) IL Version Unit Note -8 250 230 210 190 160 140 270 250 230 210 180 160 mA ...

Page 5

... RAS 100 t (max) RAS 47 (min (min) CDL t (min) RDL t (min) BDL t (min) CCD CAS latency=3 CAS latency=2 P.5 M12L16161A = Unit Vtt =1.4V è 50 è Z0= (Fig.2) AC Output Load Circuit Unit Note - ...

Page 6

... SLZ - SHZ - *All AC parameters are measured from half to half. P.6 M12L16161A - Unit Note 1000 ns 1000 1000 2.5 2 ...

Page 7

... M12L16161A-6T CAS Latency Frequency 166MHz(6.0ns) 3 143MHz(7.0ns) 3 125MHz(8.0ns) 2 111MHz(9.0ns) 2 100MHz(10.0ns) 2 M12L16161A-7T CAS Latency Frequency 143MHz(7.0ns) 3 125MHz(8.0ns) 3 111MHz(9.0ns) 2 100MHz(10.0ns) 2 83MHz(12.0ns) 2 M12L16161A-8T CAS Latency Frequency 125MHz(8.0ns) 3 111MHz(9.0ns) 3 100MHz(10 ...

Page 8

... Vender Specific Mode Register Set Burst length Wrap type Latency mode Mode Register Write P.8 M12L16161A v =Valid x =Don’t care Bit2-0 WT=0 WT=1 000 1 1 001 2 2 010 4 4 011 8 8 100 R R 101 R R 110 ...

Page 9

... P.9 Publication Date : Jan. 2000 M12L16161A Interleave Addressing Sequence (decimal Interleave Addressing Sequence (decimal ...

Page 10

... (V= Valid, X= Don’t Care, H= Logic High , L = Logic Low) t after the end of burst. RP P.10 M12L16161A DQM BA A10/AP A9~A0 Note CODE 1 Row Address 4 Column ...

Page 11

... P.11 M12L16161A *Note2 Publication Date : Jan. 2000 ...

Page 12

... Enable auto precharge, precharge bank A at end of burst Enable auto precharge, precharge bank B at end of burst. 4.A10/AP and BA control bank precharge when precharge command is asserted. A10/AP BA precharge 0 0 Bank Bank Both Banks Elite Semiconductor Memory Technology Inc. Operation P.12 Publication Date : Jan. 2000 M12L16161A Revision : 1.3u ...

Page 13

... Elite Semiconductor Memory Technology Inc P.13 M12L16161A ...

Page 14

... *Note4 SAC Prech Row Active (A-B ank) (A-Ba nk after the clock. SHZ (t t +CAS latency-1)+ RCD P.14 M12L16161A ...

Page 15

... Qa0 Qa1 Qb0 Qb1 Dc0 Qb2 Qa0 Qa1 Qb1 Qb2 Dc0 t CDL *Note1 Read Write (A-Bank) (A-Bank) t before Row precharge, will be written. RDL P.15 M12L16161A *Note2 Cd0 t RDL Dc1 Dd0 Dd1 Dc1 Dd0 Dd2 *Note3 Write Precharge (A-Bank) (A-Bank) : Don't care Publication Date : Jan ...

Page 16

... Elite Semiconductor Memory Technology Inc HIGH CAc CBb QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 Read Read (B-Bank) (A-Bank) P.16 M12L16161A *Note2 CBd CAe Read Precharge Read (B-Bank) (A-Bank) (A-Bank) : Don't care Publication Date : Jan ...

Page 17

... HIGH CBb CAc DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 DBd1 t CDL Write Write (B-Bank) (A-Bank) P.17 M12L16161A *Note2 CBd t RDL *Note1 Precharge (Both Banks) Write (B-Bank) : Don't care Publication Date : Jan. 2000 Revision : 1.3u ...

Page 18

... HIGH RBb CBb RBb RBb QAa1 QAa2 QAa3 DBb0 QAa1 QAa0 QAa2 QAa3 DBb0 Write Precharge (B-Bank) (A-Bank) Row Active (B-Bank) P.18 M12L16161A RAc CAc RAc *Note1 t CDL DBb1 DBb2 DBb3 QAc0 QAc1 DBb1 DBb2 ...

Page 19

... CL= 2 Auto Precharge Start Point ( A - Bank) CL= 3 Auto Precharge Start Point ( A - Bank) t before internal precharge start RAS P.19 M12L16161A ...

Page 20

... P.20 M12L16161A ...

Page 21

... P.21 M12L16161A ...

Page 22

... P.22 M12L16161A ...

Page 23

... Read with Auto Precharge (A-Bank) P.23 M12L16161A ...

Page 24

... Row Active Read Active Precharge Active Power-down Power-Down Power-down Exit Exit Entry P.24 M12L16161A Publication Date : Jan. 2000 ...

Page 25

... *Note3 * required before exit from self refresh. RAS P.25 M12L16161A Publication Date : Jan ...

Page 26

... Mode Register Set table. Elite Semiconductor Memory Technology Inc. Auto Refresh Cycle P.26 M12L16161A Publication Date : Jan ...

Page 27

... P.27 M12L16161A O (4X GAGE O (4X DETAIL WITH PLATING SECTION B-B BASE METAL b 1 Dimension in inch Nom Max - - 0.047 0.004 0.006 0.039 ...

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