CH7009B-T Chrontel, CH7009B-T Datasheet

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CH7009B-T

Manufacturer Part Number
CH7009B-T
Description
Manufacturer
Chrontel
Datasheet

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CHRONTEL
CHRONTEL
CHRONTEL
1. F
• DVI Transmitter up to 165M pixels/second
• DVI low jitter PLL
• DVI hot plug detection
• TV output supporting graphics resolutions up to
• Macrovision
• Programmable digital interface supports RGB and
• True scale rendering engine supports underscan in all TV
• Enhanced text sharpness and adaptive flicker removal
• Support for all NTSC and PAL formats
• Provides CVBS, S-Video and SCART (RGB) outputs
• TV connection detection
• Programmable power management
• 10-bit video DAC outputs
• Fully programmable through serial port
• Complete Windows and DOS driver support
• Low voltage interface support to graphics device
• Offered in a 64-pin LQFP package
201-0000-035 Rev 3.31, 11/4/2004
CHRONTEL
Chrontel
1024 x768 pixels
YCrCb
output resolutions
with up to 7 lines of filtering
P-OUT/TLDET*
XCLK, XCLK*
EATURES
XI/FIN,XO
D[11:0]
H,V,DE
VREF
7.1.L1 copy protection support
12
3
2
CH7009 DVI / TV Output Device
H, V, DE
Demux
Latch,
Driver
Clock
Latch
Data
Figure 1. Functional Block Diagram
24
3
2
2. G
The CH7009 is a display controller device which accepts a
digital graphics input signal, and encodes and transmits data
through a DVI (DFP can also be supported) or TV output
(analog composite, s-video or RGB). The device accepts data
over one 12-bit wide variable voltage data port which supports
five different data formats including RGB and YCrCb.
The DVI processor includes a low jitter PLL for generation of
the high frequency serialized clock, and all circuitry required
to encode, serialize and transmit data. The CH7009 comes in
versions able to drive a DVI display at a pixel rate of up to
165MHz, supporting UXGA resolution displays. No scaling
of input data is performed on the data output to the DVI
device.
The TV-Out processor performs non-interlace to interlace
conversion with scaling and flicker filters, and encodes the
data into any of the NTSC or PAL video standards. The scaling
and flicker filter is adaptive and programmable to enable
superior text display. Eight graphics resolutions are supported
up to 1024 by 768 with full vertical and horizontal underscan
capability in all modes. A high accuracy low jitter phase
locked loop is integrated to create outstanding video quality.
Support is provided for Macrovision
which enables driving a VGA CRT with the input data.
24
24
3
3
Flicker Filt
ENERAL
Encode
Scaling
Conv
Scan
DVI
24
Timing
PLL3
DVI PLL
Serialize
Encode
DVI
TV
D
ESCRIPTION
DAC’s
10-bit
Driver
Four
Control
DVI
Serial
port
2
2
2
2
2
and RGB bypass mode
CH7009B
BCO
TLC,TLC*
TDC0,TDC0*
TDC1,TDC1*
TDC2,TDC2*
VSWING
HPDET
GPIO[1:0]
AS
SPD
RESET*
C/H SYNC
ISET
CVBS
Y/G
C/R
CVBS/B
SPC
(DAC2)
(DAC1)
(DAC3)
(DAC0)
1

Related parts for CH7009B-T

CH7009B-T Summary of contents

Page 1

... VGA CRT with the input data. DVI Encode PLL3 Timing Scaling 3 Scan Conv 24 Flicker Filt 24 Figure 1. Functional Block Diagram CH7009B D ESCRIPTION ™ and RGB bypass mode TLC,TLC* DVI PLL 2 TDC0,TDC0* 2 DVI DVI TDC1,TDC1* Serialize Driver 2 TDC2,TDC2* 2 ...

Page 2

... DGND 6 GPIO[1] / TLDET* 7 GPIO[0] 8 HPDET DGND 11 DVDD 12 RESET* 13 SPD 14 SPC 15 AGND 16 2 Chrontel CH7009 Figure 2. 64-Pin LQFP 201-0000-035 Rev 3.31, 11/4/2004 CH7009B SYNC BCO / VSYNC 47 P-OUT/TLDET DVDDV 44 VAVDD FIN 41 AGND 40 GND CVBS / CVBS 36 ...

Page 3

... P-OUT/TLDET* or GPIO[1]/TLDET* pin pulling low. When the HPDET is pulled low, the DVI output driver will be shut down. AS Address Select (Internal pull-up) This pin determines the serial port address of the device (1,1,1,0,1,AS*,AS). CH7009B (Open drain or internal weak pull-up) 3 ...

Page 4

... The output can be selected to be composite video or blue FIN Crystal Input / External Reference Input A parallel resonance 14.31818MHz crystal (+ 20 ppm) should be attached between this pin and XO. However, an external clock can drive the XI/FIN input. CH7009B 201-0000-035 Rev 3.31, 11/4/2004 ...

Page 5

... MCP bit (in register 1Ch). DVDD Digital Supply Voltage DGND Digital Ground DVDDV I/O Supply Voltage TVDD DVI Transmitter Supply Voltage TGND DVI Transmitter Ground AVDD PLL Supply Voltage AGND PLL Ground VDD DAC Supply Voltage GND DAC Ground CH7009B (3.3V-3.6V) (3.3V to 1.1V) (3.3V-3.6V) (3.3V-3.6V) (3.3V-3.6V) 5 ...

Page 6

... VESA TIMING DEFINITION FOR FLAT PANEL MONITORS. Pixel Aspect Refresh Rate Ratio (Hz) 4:3 1.35:1.00 <85 8:5 1:1 <85 4:3 1:1 <85 4:3 9:8 59.94 4:3 15:12 50 4:3 1:1 <85 4:3 1:1 <85 16:9 1:1 <60 15:9 1:1 <60 4:3 1:1 <85 16:9 1:1 <60 4:3 1:1 <60 16:9 1:1 2 <30 CH7009B VESA DISPLAY MONITOR XCLK DVI Frequency Frequency (MHz) (Mbits) <35.5 <355 <31.5 <315 <36 <360 27 270 27 270 <57 <570 <95 <950 <67 <670 <75 <750 <158 <1580 <80 <800 <165 <1650 <140 <1400 201-0000-035 Rev 3.31, 11/4/2004 The ...

Page 7

... P-OUT/TLDET* BCO 201-0000-035 Rev 3.31, 11/4/2004 DVI PLL DVI 24 Encode Serialize PLL3 Timing Scaling Scan 3 Encode Conv 24 Flicker Filt 24 Figure 3. DVI Output CH7009B TLC,TLC* 2 TDC0,TDC0* 2 DVI DVI TDC1,TDC1* Driver 2 TDC2,TDC2* 2 VSWING HPDET GPIO[1: Serial SPC port Control SPD RESET* ...

Page 8

... In order to minimize the hazard of ESD, a set of protection diodes MUST BE used for each DAC connecting to TV (Refer to AN-38 for details). 8 Pixel Aspect TV Output Ratio Ratio Standard 4:3 1:1 PAL 4:3 1:1 NTSC 4:3 1.35:1.00 PAL 4:3 1.35:1.00 NTSC 8:5 1:1 PAL 8:5 1:1 NTSC 4:3 1:1 PAL 4:3 1:1 NTSC 4:3 9:8 NTSC 4:3 9:8 NTSC 4:3 15:12 PAL 4:3 15:12 PAL 4:3 1:1 PAL 4:3 1:1 NTSC 4:3 1:1 PAL 4:3 1:1 NTSC CH7009B Scaling Ratios 5/4, 1/1 5/4, 1/1 5/4, 1/1 5/4, 1/1 5/4, 1/1 5/4, 1/1, 7/8 5/4, 1/1, 5/6 1/1, 7/8, 5/6 1/1 1/1, 7/8, 5/6 1/1 1/1, 5/6, 5/7 1/1, 5/6, 5/7 3/4, 7/10, 5/8 5/7, 5/8, 5/9 5/8, 5/9, 1/2 201-0000-035 Rev 3.31, 11/4/2004 ...

Page 9

... BCO 201-0000-035 Rev 3.31, 11/4/2004 DVI PLL DVI Encode Serialize PLL3 Timing Scaling 3 Scan Conv Encode Flicker Filt 24 24 Figure 4. TV Output Modes CH7009B TLC,TLC* 2 TDC0,TDC0* 2 DVI DVI TDC1,TDC1* Driver 2 TDC2,TDC2* 2 VSWING HPDET GPIO[1: Serial SPC Port Control SPD ...

Page 10

... The second XCLK/XCLK* waveform represents the input clock for the multiplexed data, clock at 1X pixel rate method. XCLK XCLK XCLK XCLK D[11: Regarding the CH7009 timing specifications, please see Figure 18 - Figure 20 for details P-OUT 1 VGA Line Figure 5. Interface Timing CH7009B 201-0000-035 Rev 3.31, 11/4/2004 ...

Page 11

... Y1 byte refers to the next luminance sample, per CCIR-656 standards (the clock frequency is dependent upon the current mode, and is not 27MHz as specified in CCIR-656). All non-active pixels should RGB formats, and 16 for Y and 128 for CrCb in YCrCb formats. 201-0000-035 Rev 3.31, 11/4/2004 CH7009B 11 ...

Page 12

... Data) P[7:0] (Blue Data) Figure 6. Multiplexed Input Data Formats (IDF = SAV P0a P0b P0b[11:4] P0b[3:0], P0a[11:8] P0b[11:7], P0b[3:1] P0b[6:4], P0a[11:9], P0b[0], P0a[3] P0a[8:4], P0a[2:0] CH7009B P1a P1b P2a P2b P1b[11:4] P2b[11:4] P2b[3:0], P1b[3:0], P1a[11:8] P2a[11:8] P0a[7:0] P1a[7:0] P2a[7:0] P2b[11:7] P1b[11:7], P1b[3:1] ...

Page 13

... CRA (internal signal) P[23:16] (Y Data) P[15:8] (CrCb Data) P[7:0] (ignored) Figure 7. Multiplexed Input Data Formats (IDF = 201-0000-035 Rev 3.31, 11/4/2004 SAV P0a P0b P0b[6:4], P0a[11:9] P0b[5:4], P0a[11:9] CH7009B P1a P1b P2a P2b P0b[11:7] P1b[11:7] P2b[11:7] P2b[6:4], P1b[6:4], P1a[11:9] P2a[11:9] P0a[8:4] P1a[8:4] P2a[8:4] P0b[10:6] P1b[10:6] ...

Page 14

... RGB 5-6-5 P0b P1a P1b P0a R0[7] G1[4] R1[7] G0[5] R0[6] G1[3] R1[6] G0[4] R0[5] G1[2] R1[5] G0[3] R0[4] B1[7] R1[4] B0[7] R0[3] B1[6] R1[3] B0[6] G0[7] B1[5] G1[7] B0[5] G0[6] B1[4] G1[6] B0[4] G0[5] B1[3] G1[5] B0[3] 4 YCrCb 8-bit P0b P1a P1b P2a Y0[7] Cr0[7] Y1[7] Cb2[7] Y0[6] Cr0[6] Y1[6] Cb2[6] Y0[5] Cr0[5] Y1[5] Cb2[5] Y0[4] Cr0[4] Y1[4] Cb2[4] Y0[3] Cr0[3] Y1[3] Cb2[3] Y0[2] Cr0[2] Y1[2] Cb2[2] Y0[1] Cr0[1] Y1[1] Cb2[1] Y0[0] Cr0[0] Y1[0] Cb2[0] CH7009B 1 12-bit RGB (12-12) P0b P1a P1b R0[7] G1[4] R1[7] R0[6] G1[3] R1[6] R0[5] G1[2] R1[5] R0[4] B1[7] R1[4] R0[3] B1[6] R1[3] G0[7] B1[5] G1[7] G0[6] B1[4] G1[6] G0[5] B1[3] G1[5] R0[2] G1[0] R1[2] R0[1] B1[2] R1[1] R0[0] B1[1] R1[0] G0[1] B1[0] G1[1] 3 RGB 5-5-5 P0b P1a P1b X G1[5] X R0[7] G1[4] R1[7] R0[6] G1[3] R1[6] R0[5] B1[7] R1[5] R0[4] B1[6] R1[4] R0[3] B1[5] R1[3] G0[7] B1[4] G1[7] G0[6] B1[3] G1[6] P2b P3a P3b Y2[7] ...

Page 15

... Bits S[7] and S[3..0] are ignored. 201-0000-035 Rev 3.31, 11/4/2004 4 YCrCb 8-bit P0b P1a P1b P2a 00 00 S[7] Cb2[ S[6] Cb2[ S[5] Cb2[ S[4] Cb2[ S[3] Cb2[ S[2] Cb2[ S[1] Cb2[ S[0] Cb2[0] CH7009B P2b P3a P3b Y2[7] Cr2[7] Y3[7] Y2[6] Cr2[6] Y3[6] Y2[5] Cr2[5] Y3[5] Y2[4] Cr2[4] Y3[4] Y2[3] Cr2[3] Y3[3] Y2[2] Cr2[2] Y3[2] Y2[1] Cr2[1] Y3[1] Y2[0] Cr2[0] Y3[0] 15 ...

Page 16

... Black times (F and H) vary with position controls Figure 8. NTSC / PAL Composite Output 16 Level (mV) NTSC PAL 287 300 0 0 287 300 287 300 287 300 340 300 340 300 340 300 CH7009B Duration (uS) NTSC PAL 1.49 - 1.51 1.48 - 1.51 4.69 - 4.72 4.69 - 4.71 0.59 - 0.61 0.88 - 0.92 2.50 - 2.53 2.24 - 2.26 1.55 - 1.61 2.62 - 2.71 0.00 - 7.50 0.00 - 8.67 37.66 - 52.67 34.68 - 52.01 0.00 - 7.50 0.00 - 8.67 201-0000-035 Rev 3.31, 11/4/2004 ...

Page 17

... Interlaced NTSC Video Timing CH7009B 271 272 273 274 275 268 268 270 270 ...

Page 18

... FIE LD 4 FIE LD 4 312 313 314 315 316 317 312 313 314 315 316 ° ° ° ° ° ° CH7009B 318 319 31 9 320 32 0 321 321 322 322 323 323 6 ...

Page 19

... Figure 11. NTSC Y (Luminance) Output Waveform (DACG = 0) Color/Level mA White 26.75 Yellow 24.62 Cyan 21.11 Green 18.98 Magenta 15.62 Red 13.49 Blue 10.14 Blank/ Black 8.00 Sync 0.00 Figure 12. PAL Y (Luminance) Video Output Waveform (DACG = 1) 201-0000-035 Rev 3.31, 11/4/2004 Color bars: Color bars: V 1.003 0.923 0.792 0.712 0.586 0.506 0.380 0.300 0.000 CH7009B 19 ...

Page 20

... Green/Magenta 26.68 1.000 Yellow/Blue 23.93 0.897 Peak Burst 19.21 0.720 Blank 15.24 0.572 Peak Burst 11.28 0.423 4.433619 MHz Color Burst Yellow/Blue 6.56 0.246 Green/Magenta 3.81 0.143 Cyan/Red 2.97 0.111 Figure 14. PAL C (Chrominance) Video Output Waveform (DACG = 1) 20 Color bars: (9 cycles) Color bars: (10 cycles) CH7009B 201-0000-035 Rev 3.31, 11/4/2004 ...

Page 21

... Color/Level V Peak Chrome 33.31 1.249 White 26.75 1.003 Peak Burst 11.97 0.449 Blank/Black 8.00 0.300 Peak Burst 4.04 0.151 Sync 0.00 0.000 Figure 16. Composite PAL Video Output Waveform (DACG = 1) 201-0000-035 Rev 3.31, 11/4/2004 Color bars: 3.579545 MHz Color Burst (9 cycles) Color bars: 4.433619 MHz Color Burst (10 cycles) CH7009B 21 ...

Page 22

... Select output signal for BCO pin BCOP BCO polarity GPIOL[1:0] Read or write level for GPIO pins GOENB[1:0] Direction control for GPIO pins SYNCO[1:0] Enables/selects sync output for Scart and bypass modes DACG[1:0] DAC gain control DACBP DAC bypass XOSC[2:0] Crystal oscillator adjustments 22 CH7009B 201-0000-035 Rev 3.31, 11/4/2004 ...

Page 23

... Calculated sub-carrier increment value read out PALN Select PAL-Nc (Argentina) when in a CIV mode MEM[2:0] Memory sense amp reference adjust VBID Vertical blanking interval defeat PLLCPI TV-Out PLL charge pump current control PLLCAP TV-Out PLL capacitor control SenseSEL Select TV connection method 201-0000-035 Rev 3.31, 11/4/2004 CH7009B 23 ...

Page 24

... TPVCO8 ResetIB ResetDB TV DACPD3 DACPD2 VID5 VID4 VID3 DID5 DID4 DID3 IR0 VOS1 VOS0 R/W R/W R CH7009B Bit 2 Bit 1 Bit 0 SR2 SR1 SR0 YFFT0 YFFNT1 YFFNT0 YSV0 YCV1 YCV0 TE2 TE1 TE0 SAV2 SAV1 SAV0 HP2 HP1 HP0 VP2 VP1 VP0 ...

Page 25

... NTSC 1024x768 1400x875 PAL 1024x768 1400x1000 PAL 1024x768 1400x1125 PAL 1024x768 1160x840 NTSC 1024x768 1160x945 NTSC 1024x768 1168x1050 NTSC 720x576 864x625 PAL 720x480 858x525 NTSC CH7009B can be supported C Scaling Percent Pixel Clock Overscan (MHz) 5/4 -17 21.000000 1/1 -33 26.250000 5/4 0 20.139860 1/1 -20 24.671329 5/4 -13 28.125000 1/1 -30 36.000000 ...

Page 26

... CBW YSV1 R/W R/W R CH7009B 11 NTSC-J Symbol: FF Address: 01h Bits YFFT0 YFFNT1 YFFNT0 R/W R Symbol: VBW Address: 02h Bits YSV0 YCV1 YCV0 R/W R 201-0000-035 Rev 3.31, 11/4/2004 ...

Page 27

... CH7009B 10 11 3.540 5.880 4.430 7.350 3.020 5.010 3.700 6.140 4.750 7.870 6.080 10.100 4.010 6.660 4.970 8.240 4.220 7.000 5 ...

Page 28

... SAV8 HP8 VP8 R/W R/W R SAV5 SAV4 SAV3 R/W R/W R HP5 HP4 HP3 R/W R/W R CH7009B Symbol: TE Address: 03h Bits TE2 TE1 R/W R Symbol: SAV Address: 04h Bits SAV2 SAV1 SAV0 R/W R Symbol: HP Address: ...

Page 29

... Rev 3.31, 11/4/2004 VP5 VP4 VP3 R/W R/W R BL5 BL4 BL3 R/W R/W R CH7009B Symbol: VP Address: 06h Bits VP2 VP1 R/W R Symbol: BL Address: 07h Bits BL2 BL1 R/W R/W ...

Page 30

... Bit 0 of register TPC controls the TV PLL loop filter capacitor. A recommended listing of PLLCAP setting versus mode is listed in Table 15 below. 30 104 172 240 Yin IBI N9 R/W R/W R CH7009B 308 376 444 Symbol: TPC Address: 09h Bits PLLCPI PLLCAP R/W R/W ...

Page 31

... Rev 3.31, 11/4/2004 Mode PLLCAP Value R/W R CH7009B Symbol: PLLM Address: 0Ah Bits R/W R ...

Page 32

... NTSC, 5 1024x768, PAL, 5 1024x768, PAL, 5 1024x768, PAL, 5 1024x768, NTSC, 5 1024x768, NTSC, 5 1024x768, NTSC, 1 720x576, PAL, 1 720x480, NTSC, 1:1 63 CH7009B Symbol: PLLN Address: 0Bh Bits R/W R 10- 9-bits bits 142 63 214 ...

Page 33

... CH7009B Symbol: FSCI Address: 0Ch – 0Fh Bits: 8 each FSCI# FSCI# FSCI# R/W R/W PAL-M “Normal Dot Crawl” 762,524,467 622,468,953 573,798,541 ...

Page 34

... Dot Crawl” 651,209,077 520,967,262 486,236,111 379,871,962 547,015,625 434,139,385 651,209,077 520,967,262 434,139,385 558,179,209 455,846,354 390,725,446 521,519,134 427,355,957 366,305,106 502,361,288 439,566,127 390,725,446 569,807,942 CIV25 CIV24 CIVC1 CH7009B Symbol: CIVC Address: 10h Bits CIVC0 PALN CIVEN R/W R 201-0000-035 Rev 3.31, 11/4/2004 0 R/W 1 ...

Page 35

... TV PLL’s operating frequency. In slave mode (M/S* = ‘0’) the XCLK input is used as a reference to the TV PLL. The M and N TV PLL divider values are forced to one. 201-0000-035 Rev 3.31, 11/4/2004 CIV# CIV# CIV M/S* R/W CH7009B Symbol: CIV Address: 11h – 13h Bits: 8 each CIV# CIV# CIV ...

Page 36

... XCLK behind Data STEP XCLK behind Data STEP XCLK behind Data STEP XCLK behind Data STEP XCLK behind Data STEP XCLK behind Data STEP CH7009B Symbol: IC Address: 1Dh Bits XCMD0 R/W R 201-0000-035 Rev 3.31, 11/4/2004 0 R/W 0 ...

Page 37

... Bit 7 of register IDF selects the input buffer used for the data, sync and clock input pins. 201-0000-035 Rev 3.31, 11/4/2004 HPIR R/W R/W R SYO VSP HSP R/W R/W R CH7009B Symbol: GPIO Address: 1Eh Bits HPIE POUTE POUTP R/W R Symbol: IDF Address: 1Fh Bits: 8 ...

Page 38

... Bits 4-3 of register DC select the signal to be output from the C/H Sync pin according to Table 20 below DVIT DACT3 DACT2 SYNCO1 SYNCO0 R/W R CH7009B Symbol: CD Address: 20h Bits DACT1 DACT0 SENSE Symbol: DC Address: ...

Page 39

... TV Horizontal Sync SHF0 BCOEN BCOP R/W R/W R BCO[2:0] Buffered Clock Output 100 (for test use only) 101 (for test use only) 110 VGA Vertical Sync 111 TV Vertical Sync CH7009B Symbol: BCO Address: 22h Bits BCO2 BCO1 BCO0 R ...

Page 40

... Register TVCO controls the state of the DVI PLL VCO, and should be set according to Table 23 R/W R/W R TPPD 1 TPPD 0 CTL3 R/W R/W R R/W R/W R CH7009B Symbol: TERM Address: 23h Bits HPDD Reserved Reserved R/W R Symbol: TCTL Address: 31h Bits CTL2 CTL1 CTL0 R/W R/W 0 ...

Page 41

... Please see Table 23 for the default values in terms of the frequency ranges. 201-0000-035 Rev 3.31, 11/4/2004 DVID0 DVII TPPSD1 TPPSD0 R/W R/W R R/W R/W R TPVT5 TPVT4 TPVT3 R/W R/W R CH7009B Symbol: TPCP Address: 33h Bits TPCP1 TPCP0 R/W R Symbol: TPD Address: 34h Bits TPFBD0 R/W R Symbol: TPVT ...

Page 42

... TPF 37h TVCOO TPLPF1 TPLPF0 Reserved Reserved Reserved R/W R/W R R/W R <= 65MHz 00h 23h 08h 16h 30h 60h 00h CH7009B Symbol: TLPF Address: 36h Bits Reserved R/W R Symbol: TCT Address: 37h Bits R/W R/W R > ...

Page 43

... R/W R FPD Operating State 0 Composite Off, S-video on 0 Composite On/S-video off 0 Normal (On) 0 VGA to TV Encoder Off 0 DVI Encode, Serialize, Transmitter, and PLL on 1 Full Power Down CH7009B Symbol: RES Address: 48h Bits Reserved R/W R Symbol: PM Address: 49h Bits: ...

Page 44

... Register DID is a read only register containing the device ID number of the CH7009 VID5 VID4 VID3 DID5 DID4 DID3 CH7009B Symbol: VID Address: 4Ah Bits VID2 VID1 VID0 Symbol: DID Address: 4Bh Bits ...

Page 45

... AVDD I TV-Out Enabled, DVI Disabled DVDD I TV-Out Disbled, DVI Enabled (85 MHz Pixel Clock) DVDD 201-0000-035 Rev 3.31, 11/4/2004 Min - 0.5 1 GND - 0 Min 3.1 3.1 3.1 1.1 A Min 10 CH7009B Typ Max Units 5.0 V VDD + 0.5 V Indefinite Sec °C 85 °C 150 °C 150 °C 260 °C 245 225 °C Typ ...

Page 46

... DVDD-0 3.2mA 400 uA DVDDV TVDD = 3.3V +/- 5% TVDD R 50 ohm +/- 1% 0.01 TERM R 2400 ohm +/- 1% TVDD - 0.6 SWING 400 TVDD 0.01 V MISCA 201-0000-035 Rev 3.31, 11/4/2004 CH7009B VDD, AVDD Typ Max Unit 0.4 V DVDD+0.5 V 1.4 V DVDD+0.5 V Vref-0.25 V DVDD + V 0.5 0 ...

Page 47

... XCLK f = 165MHz 75 XCLK f = 165MHz XCLK f = 165MHz XCLK f = 165MHz XCLK XCLK = XCLK* to 0.5 D[11:0 Vref D[11:0 0.5 Vref to XCLK = XCLK* 15pF load VDDV = 3.3V 15pF load VDDV = 3.3V 50 CH7009B Typ Max Unit 165 MHz 242 ps 242 1.2 ns 150 1. ...

Page 48

... Pout (when configured as outputs) Output Fall Time F t1 XCLK & XCLK* rise/fall time w/15pF load t2 D[11:0] & DE rise/fall time w/15pF load t3 Hold time: P-OUT to HSYNC, VSYNC delay PIXELS 1 VGA Line Parameter CH7009B P0a P0b P1a P1b P2a P2b Min Typ ...

Page 49

... Hold Time: D[11:0 and DE to XCLK, XCLK XCLK & XCLK* rise/fall time w/15pF load t2 D[11:0 & DE rise/fall time w/ 15pF load 201-0000-035 Rev 3.31, 11/4/2004 PIXELS 1 VGA Line t2 t2 CH7009B P0a P0b P1a P1b P2a P2b Min Typ Max ...

Page 50

... R t Pout Output Fall Time F t1 XCLK & XCLK* rise/fall time w/15pF load t2 D[11:0 & DE rise/fall time w/15pF load PIXELS 1 VGA Line t2 t2 CH7009B t t POUTR POUTF P0a P0b P1a P1b P2a P2b Min Typ ...

Page 51

... Dimension B: Top Package body size may be smaller than bottom package size by as much as 0.15 mm. 3. Dimension B does not include allowable mold protrusions up to 0.25 mm per side. 201-0000-035 Rev 3.31, 11/4/2004 SYMBOL 0.17 1.35 0.05 0.50 0.27 1.45 0.15 CH7009B LEAD CO-PLANARITY E .004 “ 0.45 0.09 0° 1.00 0.75 0.20 7° 51 ...

Page 52

... Section 5.4 52 Description First official release of CH7009A datasheet, rev. 1.0 CH7009A changed to CH7009B Pin description of Table 1 updated. Table 29 added into datasheet. Register map updated. Default bit values and public bits changed on various registers. 02h, 0Bh, 23h, 31h, 32h, 33h, 34h, 35h, 36h, 37h, 38h. ...

Page 53

... Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably expect to result in personal injury or death. Part number CH7009B-T CH7009B-T-TR CH7009B-TF CH7009B-TF-TR ©2004 Chrontel, Inc. All Rights Reserved. Printed in the U.S.A. 201-0000-035 Rev 3.31, 11/4/2004 Disclaimer ORDERING INFORMATION ...

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