A1010B-VQ80C Actel, A1010B-VQ80C Datasheet
A1010B-VQ80C
Available stocks
Related parts for A1010B-VQ80C
A1010B-VQ80C Summary of contents
Page 1
... Apr i l 199 6 © 1996 Actel Corporation A security fuse may be programmed to disable all further programming and to protect the design from being copied or reverse engineered A1010B Device A10V10B Capacity Gate Array Equivalent Gates PLD Equivalent Gates ...
Page 2
The systems are available for 386/486/Pentium ™ ™ HP and Sun workstations and for running Viewlogic Figure 1 • Partial View of an ACT 1 Device ACT Struct partial view of an ...
Page 3
... These pins allow the user to observe any two internal signals by entering the appropriate net name in the diagnostic software. Signals may be viewed on a logic analyzer using ® Actel’s Actionprobe diagnostic tools. The probe pins can also be used as user-defined I/Os when debugging is finished. Orderin g Infor ...
Page 4
... Plastic Leaded Chip Carrier (PL) 84-pin Plastic Leaded Chip Carrier (PL) 80-pin Very Thin (1.0 mm) Quad Flatpack (VQ) Applications Commercial Availability Industrial M = Military B = MIL-STD-883 De vice R es ources Device Logic Modules A1010B, A10V10B 295 A1020B, A10V20B 547 1-286 Speed Grade* Std –1 –2 –3 — ...
Page 5
Pin ption CLK Clock (Input) TTL Clock input for global clock distribution network. The Clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. DCLK Diagnostic Clock (Input) ...
Page 6
Ele c trical Spe ci fica t i ons (5V ) Symbol Parameter –10 mA –6 mA – ...
Page 7
... I/O. The power can be divided into two components: static and active. Static Power Component Actel FPGAs have small static power components that result in lower power dissipation than PALs or PLDs. By integrating multiple PALs/PLDs into one FPGA, an even greater reduction in board-level power dissipation can be achieved. ...
Page 8
... Average output buffer switching rate in MHz Average first routed array clock rate in MHz (All q1 . Equivalent CC Fixed Capacitance Values for Actel FPGAs (pF) Device Type A1010B A1010B A1020B A1020B 3.2 3.7 A10V10B 10.9 22.1 A10V20B 11.6 31.2 Determining Average Switching Frequency To determine the switching frequency for a design, you must have a detailed understanding of the data input values to the 4 ...
Page 9
... ACT 1 devices are AC tested to a “binning” circuit specification. The circuit consists of one input buffer + n logic modules + one output buffer ( for A1010B for A1020B). The Outpu t Buffer Per for m anc (5V) Sink ...
Page 10
... This tight distribution is achieved in two ways: by decreasing the delay of the interconnect elements and by decreasing the number of interconnect elements per path. Actel’s patented PLICE antifuse offers a very low resistive/capacitive interconnect. The ACT 1 family’s antifuses, fabricated in 1.0 micron lithography, offer nominal levels of 200 ohms resistance and 7 ...
Page 11
Timing Derating A best case timing derating factor of 0.45 is used to reflect best case processing. Note that this factor is relative to the Timing Derati ng Fact and ...
Page 12
Te mp erature and age tors (n ormali zed Commercial 2.7 ...
Page 13
Parameter Meas Output Buffer Delays GND 50% 50 1.5 V PAD 1 DLH DHL AC Test Loads Load 1 (Used to measure propagation delay) To the ...
Page 14
Se q uen tial Timi ng C har act Flip-Flops and Latches SUD CLK E Q PRE, CLR Note: D represents all data functions involving for multiplexed flip-flops. ...
Page 15
Timi (Worst-Case Commercial Conditions, V Logic Module Propagation Delays Parameter Description t Single Module PD1 t Dual Module Macros PD2 t Sequential Clk ...
Page 16
ACT 1 Timing Char act (Worst-Case Commercial Conditions) Input Module Propagation Delays Parameter Description t Pad to Y High INYH t Pad to Y Low INYL Input Module Predicted Routing Delays t FO=1 Routing Delay ...
Page 17
... THL Notes: 1. Delays based loading. 2. SSO information can be found in the “Simultaneous Switching Output Limits for Actel FPGAs” application note on page 4-125. (continued) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3 V Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 6 ...
Page 18
... GND 38 49 CLK, I/O MODE 52 54 VCC SDI, I/O 55 DCLK, I PRA, I/O PRB, I GND 68-Pin PLCC A1010B, A10V10B A1020B, A10V20B Function Functions VCC VCC GND GND GND GND VCC VCC VCC VCC GND GND VCC VCC GND GND CLK, I/O CLK, I/O MODE ...
Page 19
Pack age Pin ent s 84-Pin PLCC Signal Notes: 1. NC: Denotes No Connection 2. ...
Page 20
... GND 77 VCC I/O 86 I/O 87 I/O 90 GND 92 GND 93 VCC 94 VCC 95 I/O 96 I 100 A1010B A1020B Function Function VCC VCC GND GND VCC VCC I/O NC I/O NC I/O GND GND GND GND CLK, I/O CLK, I/O MODE MODE ...
Page 21
... I/O 50 I/O 52 GND 53 VCC 54 I/O 55 I/O 56 I/O 57 VCC 58 GND 59 VCC 60 I/O 61 I/O 68 I/O 74 ™ eri es FPG As A1010B, A10V10B A1020B, A10V20B Function Function GND GND CLK, I/O CLK, I/O MODE MODE VCC VCC NC I/O NC I/O NC I/O SDI, I/O SDI, I/O DCLK, I/O DCLK, I/O PRA, I/O PRA, I PRB, I/O PRB, I/O GND GND ...
Page 22
... F9 GND F10 PRB, I/O G2 SDI,I/O G10 I/O J2 I/O J10 DCLK, I/O K1 I/O K2 I/O K5 I/O K7 GND K10 GND K11 VCC A1010B Function A1020B Function VCC VCC MODE MODE VCC VCC CLK, I/O CLK, I/O GND GND VCC VCC GND GND NC I/O NC I/O NC I/O VCC VCC GND GND VCC VCC ...
Page 23
Pack age Pin ent s 84-Pin CQFP 84 Pin #1 Index 1 Pin A1020B Function GND 8 GND 14 VCC 15 VCC 22 VCC 29 GND 35 VCC 49 GND 50 GND ...
Page 24
1-306 ...