NT5SV4M16DT-7K NANYA, NT5SV4M16DT-7K Datasheet
NT5SV4M16DT-7K
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NT5SV4M16DT-7K Summary of contents
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... Fully Synchronous to Positive Clock Edge • Four Banks controlled by BS0/BS1 (Bank Select) Description The NT5SV16M4DT, NT5SV8M8DT, and NT5SV4M16DT are four-bank Synchronous DRAMs organized as 4Mbit Bank, 2Mbit Bank, and 1Mbit Bank, respectively. These synchronous devices achieve ...
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... 54-pin Plastic TSOP(II) 400 mil 4Mbit Bank NT5SV16M4DT 2Mbit Bank NT5SV8M8DT 1Mbit Bank NT5SV4M16DT 2 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice DQ7 DQ15 V V ...
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... NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT 64Mb Synchronous DRAM Pin Description CK CKE CS RAS CAS WE BS1, BS0 A0 - A11 Input/Output Functional Description Symbol Type Polarity Positive CLK Input Edge CKE Input Active High CS Input Active Low RAS, CAS, Input Active Low WE BS0, BS1 Input — A11 Input — ...
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... NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT 64Mb Synchronous DRAM Ordering Information Organization Part Number NT5SV16M4DT-6K 16M x 4 NT5SV16M4DT-7K NT5SV16M4DT-7 NT5SV8M8DT- NT5SV8M8DT-7K NT5SV8M8DT-7 NT5SV4M16DT- NT5SV4M16DT-7K NT5SV4M16DT-7 REV 1.1 10/01 Speed Grade Clock Frequency@CAS Latency 166MHz@CL3 133MHz@CL2 143MHz@CL3 133MHz@CL2 143MHz@CL3 100MHz@CL2 166MHz@CL3 133MHz@CL2 143MHz@CL3 133MHz@CL2 143MHz@CL3 ...
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... NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT 64Mb Synchronous DRAM Block Diagram CKE Buffer CKE CLK CLK Buffer A11 BS0 BS1 A10 CS RAS CAS WE Cell Array, per bank, for 4Mb x 4 DQ: 4096 Row x 1024 Col (DQ0-DQ3). ...
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... NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT 64Mb Synchronous DRAM Mode Register Operation (Address Input For Mode Set) BS1 BS0 A11 A10 Operation Mode Operation Mode M1 3 M12 M11 M10 REV 1.1 10/ CAS Latency Burst Type M3 Mode ...
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... NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT 64Mb Synchronous DRAM Burst Mode Operation Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). There are three parameters that define how the burst mode will operate. These parameters include burst sequence, burst length, and operation mode ...
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... NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT 64Mb Synchronous DRAM Command Truth Table (See note 1) Function Device State Mode Register Set Idle Auto (CBR) Refresh Idle Entry Self Refresh Idle Idle (Self- Exit Self Refresh Refresh) See Current Single Bank Precharge State Table See Current ...
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... NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT 64Mb Synchronous DRAM Clock Enable (CKE) Truth Table CKE Current State Previous Current Cycle Cycle Self Refresh Power Down All Banks Idle ...
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... NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT 64Mb Synchronous DRAM Current State Truth Table Current State CS RAS CAS WE BS0,BS1 Idle ...
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... NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT 64Mb Synchronous DRAM Current State Truth Table Current State CS RAS CAS WE BS0,BS1 Read with Auto Pre charge ...
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... NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT 64Mb Synchronous DRAM Current State Truth Table Current State CS RAS CAS WE BS0,BS1 Write Recovering Write ...
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... NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT 64Mb Synchronous DRAM Absolute Maximum Ratings Symbol Parameter V Power Supply Voltage DD V Power Supply Voltage for Output DDQ V Input Voltage IN V Output Voltage OUT T Operating Temperature (ambient Storage Temperature STG P Power Dissipation D I Short Circuit Output Current OUT 1. Stresses greater than those listed under “ ...
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... NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT 64Mb Synchronous DRAM DC Electrical Characteristics Symbol Input Leakage Current, any input I I(L) (0. All Other Pins Not Under Test = Output Leakage Current I O( disabled, 0.0V OUT Output Level (LVTTL Output “H” Level Voltage ( Output Level (LVTTL Output “ ...
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... NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT 64Mb Synchronous DRAM Operating, Standby, and Refresh Currents Parameter Symbol Operating Current I CC1 I CC2P Precharge Standby Current in Power Down Mode I CC2PS I Precharge Standby Current CC2N in Non-Power Down Mode I CC2NS I No Operating Current CC3N (Active state: 4 bank) I CC3P Operating Current (Burst ...
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... NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT 64Mb Synchronous DRAM AC Characteristics ( + initial pause of 200 s, with DQM and CKE held high, is required after power-up. A Precharge All Banks command must be given followed by a minimum of two Auto (CBR) Refresh cycles before or after the Mode Register Set operation. ...
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... NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT 64Mb Synchronous DRAM Clock and Clock Enable Parameters Symbol Parameter t Clock Cycle Time, CAS Latency = 3 CK3 t Clock Cycle Time, CAS Latency = 2 CK2 t Clock Access Time, CAS Latency = 3 AC3 (A) t Clock Access Time, CAS Latency = 2 AC2 (A) t Clock Access Time, CAS Latency = 3 ...
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... NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT 64Mb Synchronous DRAM Read Cycle Symbol Parameter t Data Out Hold Time OH t Data Out to Low Impedance Time LZ t Data Out to High Impedance Time HZ3 t Data Out to High Impedance Time HZ2 t DQM Data Out Disable Latency DQZ 1. AC Output Load Circuit A. ...
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... NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT 64Mb Synchronous DRAM Clock Frequency and Latency Symbol Parameter f Clock Frequency Clock Cycle Time CK t CAS Latency AA t Precharge Time RP t RAS to CAS Delay RCD t Bank Cycle Time RC t Minimum Bank Active Time RAS t Data In to Precharge ...
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... NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT 64Mb Synchronous DRAM Package Dimensions (400mil; 54 lead; Thin Small Outline Package) 22.22 Lead #1 0.80 Basic REV 1.1 10/01 0.13 + 0.10 0.35 - 0.71REF 0.05 0.05 Min 20 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. Detail A Seating Plane 0.10 Detail A Gage Plane 0.25 Basic 0.5 0.1 © . All rights reserved. ...
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... NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT 64Mb Synchronous DRAM Revision Log Rev 05/01 Preliminary Changed to Revision 1.0 Removed -75B speed grade 09/01 Added -7 speed grade. Removed Icc6 low power product grade. Changed to Revision 1.1 10/01 Changed tOH from 2.7ns to 3ns for all speed sort. REV 1.1 10/01 Contents of Modification 21 © NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP ...