CS4231A-KQ ETC ETC, CS4231A-KQ Datasheet

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CS4231A-KQ

Manufacturer Part Number
CS4231A-KQ
Description
CS4231A-KQPARALLEL INTERFACE MULTIMEDIA AUDIO CODEC
Manufacturer
ETC ETC
Datasheet

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Semiconductor Corporation
Features
Preliminary Product Information
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 Fax: (512) 445-7581
Windows Sound System
Compatible Codec
ADPCM Compression/Decompression
Extensive Software Support
MPC Level 2 Compatible Mixer
Dual DMA Registers support Full
Duplex Operation
On-Chip FIFOs for higher performance
Selectable Serial Audio Data Port
Pin Compatible with CS4231/CS4248
D<7:0>
A<1:0>
DBDIR
XCTL1
XCTL0
PDWN
CDRQ
PDRQ
DBEN
CDAK
PDAK
IRQ
WR
CS
RD
Parallel Interface, Multimedia Audio Codec
8
2
DGND1 DGND2
VD1
Interface
Parallel
Bus
VD2
VD3
Samples
Samples
DGND3/4/7/8
FIFO
FIFO
16
16
16 Bit Timer
VD4
SDOUT SDIN SCLK FSYNC
TM
Audio Data Serial Port
I 16
I20,I21
TEST
I16
This document contains information for a new product. Crystal
Semiconductor reserves the right to modify this product without notice.
ADPCM
I8 or I28
ADPCM
Optional
XTAL1I
Linear
A-law
Linear
Dither
A-law
I10
-law
I8
-law
Copyright
XTAL1O
Attenuation
VREF
Loopback
Oscillators
Digital
VREF
General Description
The CS4231A includes stereo 16-bit audio converters
and complete on-chip filtering for record and playback
of 16-bit audio data. In addition, analog mixing and
programmable gain and attenuation are included to
provide a complete audio subsystem. A selectable se-
rial port can pass audio data to and from DSPs or
ASICs. Crystal-developed high-performance software
drivers for various operating systems are available that
support all the CS4231A features including full duplex
transfers. The CS4231A is a pin compatible upgrade to
the CS4231 and CS4248.
ORDERING INFORMATION:
XTAL2I
VREFI
Crystal Semiconductor Corporation 1994
I13
(All Rights Reserved)
16-bit
16-bit
16-bit
16-bit
D/A
D/A
A/D
A/D
I8
CS4231A-KL
CS4231A-KQ
XTAL2O
LFILT RFILT
I6
I7
Mute
Mute
Gain
Mix
MIN
Gain
Gain
I0
I1
I26
CS4231A
Gain
Mix
AGND1
0 to 70 C
0 to 70 C
I0
I1
Mux
I3
I2
Gain
Mix
AGND2
VA1 VA2
I19
I18
20dB Gain
Gain
Mix
I0
I1
Mute
I26
I4
I5
68-pin PLCC
100-pin TQFP
DS139PP2
LAUX1
RAUX1
SEPT ’94
LMIC
RMIC
LLINE
RLINE
LOUT
MOUT
ROUT
LAUX2
RAUX2
1

Related parts for CS4231A-KQ

CS4231A-KQ Summary of contents

Page 1

... XTAL2I This document contains information for a new product. Crystal Semiconductor reserves the right to modify this product without notice. Copyright Crystal Semiconductor Corporation 1994 (All Rights Reserved) CS4231A CS4231A- CS4231A- LFILT RFILT VA1 VA2 20dB Gain I0 I1 Gain I0 ...

Page 2

... Playback DMA Registers......................................26 Capture DMA Registers .......................................26 Digital Loopback......................................................26 Timer Registers.......................................................27 Interrupts .................................................................27 Error Conditions ......................................................27 2 CS4231A REGISTER MAPPING .............................28 Physical Mapping....................................................28 Index Address Register................ (R0)................29 Index Data Register ..................... (R1)................29 Status Register............................. (R2, RO) ........29 Capture I/O Data Register ........... (R3, RO) ........30 Playback I/O Data Register ......... (R3, WO) .......31 Left ADC Input Control................. (I0) .................31 Right ADC Input Control ...

Page 3

... Line Inputs THD Mic Inputs Line to Line Inputs Line to Mic Inputs Line-to-AUX1 Line-to-AUX2 Line Inputs Mic Inputs Line Inputs 0 dB gain (MGE=1) MIC Inputs (MGE=0) MIC Inputs (Note 1) (Note 1) CS4231A Min Typ Max Units 16 Bits LSB 0 ...

Page 4

... IDR (Note 3) THD (Note 3) Line Out (Note -81 dB -82 -94.5 dB (Notes 3, 5) OUT, MOUT (Note 1) (Note 1) (Fs=8kHz) Digital, Operating Analog, Operating Total Digital, Power Down Analog, Power Down (Note 1) CS4231A Min Typ Max Units 16 Bits LSB 0 0.01 0. ...

Page 5

... DGND = 0V, all voltages with respect to 0V.) Symbol Digital VD1-VD4 Analog VA1,VA2 (Except Supply Pins) (Except Supply Pins) (Power Applied) (AGND, DGND = 0V, all voltages with repect Symbol Digital VD1-VD4 Analog VA1,VA2 T A CS4231A Min Typ Max Units 45 46 1.3 1.5 1.7 dB 2.3 3.0 3.4 ...

Page 6

... ADCs DACs (T = 25°C; VA1, VA2, VD1-VD4 = 5V; A Symbol Digital Inputs V IH XTAL1I, XTAL2I, PDWN - 4.0 mA (Digital Inputs) (High-Z Digital Outputs) CS4231A Min Typ Max Units 0 0.40xFs -0.5 +0.2 0.1 0.40xFs 0.60xFs 0.60xFs 74 10/Fs 14/Fs 18/Fs 0.0 0.1/Fs Min Max Units 2 ...

Page 7

... DKSUa t DKSUb t DHD2 t DRHD t BWND t DHD1 t DKHDa t DKHDb t DBDL t PDWN (Notes 1,7,8) (Notes 1,8) (Notes 1,8) (Note 1) Fs (Note 9) t SCLKW t PD1 t PD2 CS4231A Min Max Units ...

Page 8

... SF1,0=01,10 FSYNC SF1,0=00 SCLK SDIN SDOUT CDRQ t DKSUa CDAK DBEN DBDIR RD D<7:0> pd2 t t pd2 pd2 sckw MSB, Left MSB, Left t pd1 Serial Port Timing t DRHD t DBDL t DBDL t STW t RDDV 8-Bit Mono DMA Read/Capture Cycle CS4231A DKHDb t DHD1 DS139PP2 ...

Page 9

... DS139PP2 t DRHD t DKSUb t DBDL t STW t WDSU 8-Bit Mono DMA Write/Playback Cycle t BWDN LEFT/LOW BYTE 8-Bit Stereo or 16-Bit Mono DMA Cycle t BWDN HIGH BYTE LEFT SAMPLE 16-Bit Stereo or ADPCM DMA Cycle CS4231A t DKHDa t DHD2 RIGHT/HIGH BYTE HIGH LOW BYTE BYTE RIGHT SAMPLE 9 ...

Page 10

... CDRQ/PDRQ CDAK/PDAK CS DBEN DBDIR RD D<7:0> A<1:0> CDRQ/PDRQ CDAK/PDAK CS DBEN DBDIR (high) WR D<7:0> A<1:0> SUDK1 t SUDK2 t CSSU t CSHD t DBDL t DBDL t RDDV t ADSU I/O Read Cycle t SUDK1 t SUDK2 t CSHD t CSSU t DBDL t STW t WDSU t ADSU I/O Write Cycle CS4231A t DHD1 t ADHD t DHD2 t ADHD DS139PP2 ...

Page 11

... DS139PP2 Ferrite Bead 2.0 0.1 F 0 VA1 VD4 VD3 VD1 CS4231A PLCC ) ( Pinout TEST DGND3 Figure 1. Recommended Connection Diagram CS4231A +5V Supply VD2 51 SCLK 50 FSYNC 52 SDOUT 49 SDIN VD3/4 23 PDWN Address Decode 9 A1 ...

Page 12

... DAC with full volume control. Several data modes are supported in- cluding 8- and 16-bit linear as well as 8-bit companded, 4-bit ADPCM compressed, and 16- bit Big Endian. The CS4231A is packaged in a 68-pin PLCC or a 100-pin TQFP. Enhanced Functions (MODE 2) The CS4231A’s initial state is labeled MODE 1 and forces the CS4231A to appear as a CS4248 ...

Page 13

... Analog Outputs The analog output section of the CS4231A pro- vides a stereo line-level output. The other output types (headphone and speaker) can be imple- mented with external circuitry. LOUT and ROUT outputs should be capacitively coupled to external circuitry ...

Page 14

... Microchannel. Two types of accesses can occur via the parallel interface: Programmed I/O (PIO) access, and DMA access. There is no provision for the CS4231A to "hold off" or extend a cycle occurring on the parallel interface. Therefore, the internal architecture of the CS4231A accepts asynchronous parallel bus cycles without interfering with the flow of data to or from the ADC and DAC sections ...

Page 15

... The logic interfaced with the CS4231A responds with an acknowledge signal and strobes data to and from the CS4231A, 8 bits at a time. The CS4231A keeps the request pin active until the appropriate number of 8-bit cycles have occurred to transfer one audio sam- ple ...

Page 16

... ADCs is sent to the SDOUT pin and the audio data input on the SDIN pin is routed to the DACs. The parallel bus on the CS4231A is still used for control in- formation such as volume and audio data formats. While the serial port is enabled, audio ...

Page 17

... Left Data Figure 7. 64-bit mode (SF1,0 = 01) ... ... ... ... Clocks Left Data Right Data Figure 8. 32-bit mode (SF1,0 = 10) CS4231A 7 zeros 13 zeros INT CEN PEN OVR 32 Bits INT = Interrupt Bit CEN = Capture Enable PEN = Playback Enable OVR = Left Overrange or Right Overrange ... 0 15 ...

Page 18

... Fig- ure 1. Grounding is covered in the Grounding and Layout section. An interrupt pin, IRQ, is provided to allow for host notification by the CS4231A. Since the in- terrupt is mainly a software function described in more detail under the software sec- tion. Crystals / Clocks ...

Page 19

... To put the CS4231A into a power-down mode, the PDWN pin is pulled low. In this state the host interface reads 80h indicating that it is un- able to respond and all analog circuits are turned off. To let the CS4231A go through its reset initiali- zation the PDWN pin should be set high. This CS4231A 19 ...

Page 20

... While the CS4231A is initializing, 80 hex is returned from all reads by the host computer. All writes during initialization of the CS4231A will be ignored. At the end of the initialization, all registers are set to known reset values as documented in the register definition section ...

Page 21

... The CS4231A resynchronizes its internal states to the new clock. During this time the CS4231A will be unable to respond at its parallel interface. Writes to the CS4231A will not be recognized and reads will always return the value 80 hex. ...

Page 22

... Capture Data Format register (I28). The CS4231A always orders the left channel data before the right channel. Note that these definitions apply regardless of the specific for- mat of the data. For example, 8-bit linear data streams look exactly like 8-bit companded data streams ...

Page 23

... RIGHT Figure 13. 8-bit Stereo, Unsigned Audio Data sample 5 sample 4 sample 3 MONO sample 3 sample 2 sample 2 RIGHT CS4231A 32-bit Word Time sample 2 sample 1 MONO 32-bit Word Time sample 1 sample 1 LEFT 32-bit Word Time sample 2 sample 1 ...

Page 24

... Figure 17. 4-bit Stereo, ADPCM Audio Data sample 3 sample 3 sample 2 MONO LO MONO sample 2 sample 2 sample 1 RIGHT LO RIGHT CS4231A sample 4 sample 3 sample 2 sample 1 MONO MONO MONO sample 2 sample 2 sample 1 sample 1 LEFT RIGHT LEFT 32-bit Word ...

Page 25

... This can be accomplished by disabling the DMA controller or not sending data in PIO mode. The underrun will be detected by the CS4231A and the adapta- tion will freeze. As data is sent to the codec, adaptation is resumed critical that all play- back ADPCM samples are sent to the codec, since dropped samples will cause errors in the adaptation ...

Page 26

... Loopback Control register (I13). Loopback is then summed with DAC data supplied at the digital bus interface. When loopback is enabled, it will "freerun" syn- chronous with the sample rate. The digital loopback is shown in the CS4231A Block Dia- gram on the front cover. This loopback can be DS139PP2 ...

Page 27

... The Interrupt Enable (IEN) bit in the Pin Control register (I10) determines whether the interrupt pin responds to the interrupt event in the CS4231A. When the IEN bit is 0, the interrupt is masked and the IRQ pin of the CS4231A is forced low. However, the INT bit in the Status register (R2) always responds to the counter ...

Page 28

... CS4231A regis- ters via an index register. The other two registers provide status information and allow audio data to be transferred to and from the CS4231A with- out using DMA cycles or indexing. Physical Mapping The PIO registers are I/O mapped via four loca- tions. Two address pins provide access to all of the CS4231A’ ...

Page 29

... D7 I28. INIT CS4231A Initialization: This bit is read as 1 when the CS4231A state in which it cannot respond to parallel interface cycles. This bit is read-only. Immediately after RESET (and once the CS4231A has left the INIT state), the state of ...

Page 30

... In ADPCM it indi- cates, along with CL/R, which one of four ADPCM bytes is waiting. 30 CS4231A 0 - Lower or 1/3 ADPCM byte waiting 1 - Upper, any 8-bit mode, or 2/4 ADPCM byte waiting Note on PRDY/CRDY: These two bits are de- signed to be read as one when action is required by the host. For example, when PRDY is set to one, the device is ready for more data ...

Page 31

... LX1G4-LX1G0 Left Auxiliary #1, LAUX1, Mix Gain LX1M This register’s initial state after reset is: 1xx01000. CS4231A Left ADC Input Source Select. These bits select the input source for the left ADC channel Left Line: LLINE 1 - Left Auxiliary 1: LAUX1 2 - Left Microphone: LMIC ...

Page 32

... D1 D0 RDM res RDA5 RDA4 RDA3 RDA2 RDA1 RDA0 RDA5-RDA0 RDM This register’s initial state after reset is: 1x000000 CS4231A Left DAC Attenuator. The least signifi- cant bit represents -1.5 dB, with 000000 = 0 dB. See Table 6. Left DAC Mute. When set to 1, the left DAC output to the mixer will be muted ...

Page 33

... FMT1 is not available in MODE 1 (forced to 0). This register’s initial state after reset is: 0000000. CS4231A Stereo/Mono Select: This bit deter- mines how the audio data streams are formatted. Selecting stereo will result in alternating samples repre- senting left and right audio channels. ...

Page 34

... Playback Disabled (PDRQ and PIO inactive Playback Enabled CEN Capture Enabled. This bit enables the capture of data. The CS4231A will generate CDRQ and respond to CDAK signals when CEN is enabled and CPIO=0. If CPIO=1, CEN en- ables PIO capture mode. CEN may be set and reset without setting the MCE bit ...

Page 35

... Between -1.5 dB and Between 0 dB and 1.5 dB overrange 3 - Greater than 1.5 dB overrange DRQ Status: This bit indicates the current status of the PDRQ and CDRQ pins of the CS4231A CDRQ AND PDRQ are presently inactive 1 - CDRQ OR PDRQ are presently active Auto-calibrate In-Progress: This bit indicates the state of calibration. The length of time high is dependent on the calibration mode selected ...

Page 36

... These bits are read only. 1010 MODE2 MODE 2: Enables the expanded mode of the CS4231A. Must be set to en- able access to indirect registers 16-31 and their associated features MODE 1: CS4248 "look-alike" MODE 2: Expanded features. This register’s initial state after reset is: 10xx1010 ...

Page 37

... Left Line Input Control (I18) D7 LLM LLG4-LLG0 LLM This register’s initial state after reset is: 1xx01000. CS4231A Output Level Bit: Sets the analog out- put level. When clear, analog line outputs are attenuated 3 dB Full scale of 2 Vpp (-3 dB Full scale of 2.8 Vpp (0 dB) ...

Page 38

... TL4 TU6 TU5 TU4 - - - - - - MBY - - - - C/L S CUB5 CUB4 CLB5 CLB4 Table 3. Register Bit Summary CS4231A IA3 IA2 IA1 ID3 ID2 ID1 PU/L PL/R PRDY CD3 CD2 CD1 PD3 PD2 PD1 LAG3 LAG2 LAG1 RAG3 RAG2 RAG1 LX1G3 LX1G2 LX1G1 RX1G3 ...

Page 39

... Table 5. AUX1 & AUX2 & LINE Mixer Gain CFS2 CFS1 CFS0 Level -36 -39 -42 -45.0 dB FMT1 FMT0 C CS4231A ...

Page 40

... This register’s initial state after reset is: xxxxxxxx Alternate Feature Enable III (I23) D7 res ACF TL2 TL1 TL0 This register’s initial state after reset is: xxxxxxx0 TU2 TU1 TU0 CS4231A res res res res res res res ...

Page 41

... CS4231A, the version number is changed so software can distinguish between the different ver- sions. 100 - All CS4231 revisions. See Appendix A. 101 - CS4231A. This Data Sheet. Chip Identification. Distinguishes between this chip and future chips that support this register set. 000 - CS4231 or CS4231A D6 ...

Page 42

... This register’s initial state after reset is: 0000000 Capture Lower Base (I31) res res res D7 CLB7 CLB6 CLB5 CLB4 CLB3 CLB2 CLB1 CLB0 CLB7-CLB0 This register’s initial state after reset is: 00000000 CS4231A res res res res res D6 ...

Page 43

... Figure 17 shows the recommended positioning of the decoupling capacitors. The capacitors must be on the same layer as, and close to, the CS4231A. The vias shown go through to the ground plane layer. Vias, power supply traces, and VREF traces should be as large as possible to minimize the impedance. Schematic & ...

Page 44

... Figure 17. Recommended Decoupling Capacitor Positions 44 1/8" 65 PINS 8 Ground Connection +5V Ferrite Bead CPU & Digital Codec Logic digital signals Figure 16. Suggested Layout Guideline = vias through to ground plane 0 CS4231A CS4231A Digital Analog Pins Pins Analog Ground Plane Codec analog signals & Components DS139PP2 VA ...

Page 45

... ADC/DAC FILTER RESPONSE PLOTS Figures 18 through 23 show the overall fre- quency response, passband ripple, and transition band for the CS4231A ADCs and DACs. Fig- ure 24 shows the DACs’ deviation from linear phase. Since the CS4231A scales filter response based on sample frequency selected, all fre- quency response plots x-axis’ ...

Page 46

... Input Frequency ( Fs) Figure 21. DAC Filter Response. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0.40 0.43 0.46 0.49 0.52 0.55 0.58 0.61 0.64 0.67 0.70 Input Frequency ( Fs) Figure 23. DAC Transition Band. 46 CS4231A 0.2 0.1 -0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Input Frequency ( Fs) Figure 22. DAC Passband Ripple. 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Input Frequency ( Fs) Figure 24. DAC Phase Response. DS139PP2 ...

Page 47

... PIN DESCRIPTIONS A0 1 CDAK 6 CDRQ 7 PDAK 8 PDRQ 9 VD3 10 DGND3 11 XTAL1I 12 XTAL1O 13 14 VD4 DGND4 15 XTAL2I 16 XTAL2O 17 PDWN 18 RFILT 25 DS139PP2 CS4231A 100-pin TQFP (Q) Top View CS4231A XCTL1 72 IRQ 71 XCTL0 70 TEST 69 DGND7 SDOUT 62 61 SCLK 60 FSYNC 59 SDIN 57 MOUT 56 MIN 47 ...

Page 48

... CS4231A 13 57 68-pin 15 55 PLCC Top View see Power Supply section CS4231A DGND8 DBEN DBDIR XCTL1 IRQ XCTL0 TEST * DGND7 SDOUT SCLK FSYNC SDIN NC MOUT MIN * ...

Page 49

... DBDIR - Data Bus Direction, Output Pin 62, (L), Pin 77 (Q). This pin indicates the direction of the data bus transceiver. High points to the CS4231A, low points to the host bus. This signal is normally high. IRQ - Host Interrupt Pin, Output, Pin 57 (L), Pin 72 (Q). ...

Page 50

... DACs for conversion to analog. The serial port supports three serial formats and supports all audio data formats of the CS4231A. The serial audio data is always 16 bits wherein the MSB of the different audio (16 bit) is aligned with zero padding after the LSB ...

Page 51

... XTAL1O - Crystal #1 Output, Pin 18 (L), Pin 13 (Q). This pin is used for a crystal placed between this pin and XTAL1I. DS139PP2 max analog input, centered around VREF, that goes through a max analog output, centered around VREF. RMS CS4231A max centered around RMS max centered around RMS . This output is a ...

Page 52

... VREF. VREFI - Voltage Reference Internal, Input, Pin 33 (L), Pin 38 (Q). Voltage reference used internal to the CS4231A must have a 0 capacitor with short fat traces to attach to this pin. No other connections should be made to this pin. LFILT - Left Channel Antialias Filter Input, Pin 31 (L), Pin 33 (Q). ...

Page 53

... No Connect, Pins 24, 45, 54 (L) DD These pins are no connects for the CS4231A. When compatibility with the AD1848 is desired, these pins should be connected to the digital power supply. For other compatibility issues, see the Compatibility with AD1848 section of the data sheet. *NC (GNDD Connect, Pins 25, 44 (L) These pins are no connects for the CS4231A ...

Page 54

... For the DACs, the difference in output voltages for each channel with a full scale digital input. Units in dB. Offset Error For the ADCs, the deviation in LSBs of the output from mid-scale with the selected input grounded. For the DACs, the deviation in volts of the output from VREF with mid-scale input code. 54 CS4231A DS139PP2 ...

Page 55

... These bits were added to enhance full-duplex operation. The serial audio data port and associated bits - SF1, SF0, SPE - do not exist on the CS4231. The serial audio data port was added to the CS4231A to allow DSP’s and ASIC’s to act as an audio coprocessor to the CS4231A. ...

Page 56

... The "lead width with plating" dimension does not include a total allowable dambar protrusion of 0.08 mm (at maximum material condition Ejector pin marks in molding are present on every package. A CS4231A 1.067 (0.042) Min 1.219 (0.048) Max x 45deg. Nom 1.27 (0.050) Description MIN Lead Count ...

Page 57

... Fax: (512) 445 7581 CDB4231/4248 General Description The CDB4231/4248 evaluation board supports all the features of the CS4231A, CS4231, and CS4248. The DMA, IRQ, and base address are all selectable via on- board jumpers. Four stereo jacks provide MIC in, AUX1 in, LINE in, and Line/Headphone out. In addi- ...

Page 58

... GENERAL INFORMATION The CDB4231/4248 is designed to provide an easy platform for evaluating the performance of the CS4231A, CS4231, or CS4248 Parallel Inter- face, Multimedia Audio Codecs environment. This board is not a reference de- sign, although many aspects of the design should be incorporated in reference designs. The board is optimized for performance and ease of modifi- cation for testing purposes ...

Page 59

... ISA bus. The CDB4231 supports the CS4231A by providing a header, labeled J34, that is connected to the se- rial audio data port on the CS4231A. The even pins are connected to ground and the rest of the header pins are defined as follows not used ...

Page 60

The second four addresses are used by the codec. The default for the evaluation board and the software is 530h - no jumpers. The following table lists the available base addresses (along with the associated codec address), with a "1" ...

Page 61

SOFTWARE COMPATIBILITY The CDB4231/4248 comes with two sets of soft- ware: diagnostics and Windows 3.1 drivers. The diagnostics will support all hardware jumper set- tings. The Windows software will support all hardware settings when configured for generic hardware. When the ...

Page 62

The Crystal Windows 3.1 software (version 1.04) supports a "generic hardware" switch that forces the software to use the DMA and IRQ set- tings in the SYSTEM.INI file and assume no Auto-Select register exists. With this switch on, all combinations ...

Page 63

DS111DB7 CDB4231/4248 63 ...

Page 64

Figure 2. Microphone In Figure 3. Mono Speaker Out CDB4231/4248 DS111DB7 ...

Page 65

Figure 4. Line In & CDROM In (Aux2) DS111DB7 CDB4231/4248 65 ...

Page 66

Figure 5. Line/Headphone Out CDB4231/4248 DS111DB7 ...

Page 67

DS111DB7 CDB4231/4248 67 ...

Page 68

CDB4231/4248 DS111DB7 ...

Page 69

Design Description ; CDB4231 Rev. D ;---------------------------------- Declaration Segment ------------ TITLE Address Decode for CS4231 and Read ID PATTERN AD31.PDS REVISION 2.0 AUTHOR Clif Sanchez COMPANY Crystal Semiconductor DATE 10/15/93 CHIP _AD31 PAL20V8 ;---------------------------------- PIN Declarations --------------- PIN 1 ...

Page 70

Design Description ;---------------------------------- Declaration Segment ------------ TITLE Read ID + relay enable PATTERN ID31.PDS REVISION 2.0 AUTHOR Clif Sanchez COMPANY Crystal Semiconductor DATE 10/28/93 CHIP _ID31 PAL22V10 ;---------------------------------- PIN Declarations --------------- PIN 1 MUTE PIN 2 /BIOR PIN 3 ...

Page 71

ACCESS = ACCESS * /CRES + CCS * BIOR * /CRES RLYEN = ACCESS * /MUTE DS111DB7 Board ID PLD - ID31 (continued) CDB4231/4248 71 ...

Page 72

CDB4231/4248 DS111DB7 ...

Page 73

DS111DB7 CDB4231/4248 73 ...

Page 74

CDB4231/4248 DS111DB7 ...

Page 75

DS111DB7 CDB4231/4248 75 ...

Page 76

CDB4231/4248 DS111DB7 ...

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