BC41B143A05-IRK-E4 ETC ETC, BC41B143A05-IRK-E4 Datasheet - Page 5

• Manufacturer Part Number: BC41B143A05-IRK-E4
• Description: BC41B143A05-IRK-E4BlueCpre 4-ROM Single Chip Bluetooth v2.0 System with EDR
• Manufacturer: ETC ETC

Status Information
List of Figures
Figure 2.1: BlueCore4-ROM Device Pinout ............................................................................................................ 9
Figure 6.1: BlueCore4-ROM Device Diagram ....................................................................................................... 37
Figure 8.1: BlueCore HCI Stack ............................................................................................................................ 41
Figure 8.2: BlueCore RFCOMM Stack .................................................................................................................. 44
Figure 8.3: Virtual Machine ................................................................................................................................... 46
Figure 9.1: Basic Data Rate and Enhanced Data Rate Packet Structure.............................................................. 48
Figure 9.2: π/4 DQPSK Constellation Pattern ....................................................................................................... 49
Figure 9.3: 8DPSK Constellation Pattern .............................................................................................................. 50
Figure 10.1: Circuit TX/RX_A and TX/RX_B ......................................................................................................... 51
Figure 10.2: Circuit RF_IN .................................................................................................................................... 52
Figure 10.3: Internal Power Ramping.................................................................................................................... 53
Figure 10.4: TCXO Clock Accuracy ...................................................................................................................... 54
Figure 10.5: Actual Allowable Clock Presence Delay on XTAL_IN vs. PS Key Setting......................................... 55
Figure 10.6: Crystal Driver Circuit ......................................................................................................................... 57
Figure 10.7: Crystal Equivalent Circuit .................................................................................................................. 57
Figure 10.8: Crystal Load Capacitance and Series Resistance Limits with Crystal Frequency............................. 60
Figure 10.9: Crystal Driver Transconductance vs. Driver Level Register Setting .................................................. 61
Figure 10.10: Crystal Driver Negative Resistance as a Function of Drive Level Setting ....................................... 62
Figure 10.11: Universal Asynchronous Receiver .................................................................................................. 63
Figure 10.12: Break Signal.................................................................................................................................... 64
Figure 10.13: UART Bypass Architecture ............................................................................................................. 65
Figure 10.14: USB Connections for Self Powered Mode ...................................................................................... 67
Figure 10.15: USB Connections for Bus Powered Mode ...................................................................................... 68
Figure 10.16: USB_DETACH and USB_WAKE_UP Signal .................................................................................. 69
Figure 10.17: Write Operation ............................................................................................................................... 71
Figure 10.18: Read Operation............................................................................................................................... 71
Figure 10.19: BlueCore4-ROM as PCM Interface Master ..................................................................................... 73
Figure 10.20: BlueCore4-ROM as PCM Interface Slave ....................................................................................... 73
Figure 10.21: Long Frame Sync (Shown with 8-bit Companded Sample)............................................................. 74
Figure 10.22: Short Frame Sync (Shown with 16-bit Sample) .............................................................................. 74
Figure 10.23: Multi Slot Operation with Two Slots and 8-bit Companded Samples .............................................. 75
Figure 10.24: GCI Interface................................................................................................................................... 75
Figure 10.25: 16-Bit Slot Length and Sample Formats ......................................................................................... 76
Figure 10.26: PCM Master Timing Long Frame Sync ........................................................................................... 78
Figure 10.27: PCM Master Timing Short Frame Sync........................................................................................... 78
Figure 10.28: PCM Slave Timing Long Frame Sync ............................................................................................. 80
Figure 10.29: PCM Slave Timing Short Frame Sync............................................................................................. 80
Figure 10.30: Example EEPROM Connection ...................................................................................................... 84
Figure 10.31: Example TXCO Enable OR Function .............................................................................................. 84
Figure 13.1: Application Circuit for Radio Characteristics Specification with 6 x 6mm VFBGA Package .............. 88
Figure 14.1: BlueCore4-ROM 84-Ball VFBGA Package Dimensions.................................................................... 89
Figure 15.1: Typical Lead-Free Re-flow Solder Profile.......................................................................................... 90
Figure 17.1: Tape and Reel Orientation ................................................................................................................ 93
Figure 17.2: Tape Dimensions .............................................................................................................................. 94
This material is subject to CSR’s non-disclosure agreement
BC41B143A-ds-001Pe
Page 5 of 102
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© Cambridge Silicon Radio Limited 2005