AX88790L ASIX, AX88790L Datasheet
AX88790L
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AX88790L Summary of contents
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... Always contact ASIX for possible updates before starting a design. This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product. ...
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... MR4 – Autonegotiation Advertisement Registers Bit Descriptions............................................................ 30 4.4.5 MR5 – Autonegotiation Link Partner Ability (Base Page) Register Bit Descriptions................................. 30 3-in-1 PCMCIA Fast Ethernet Controller CONTENTS ............................................................................................................... 6 IAGRAM G ......................................................................................................... 7 ROUP .......................................................................................................................... 8 ........................................................................................... 9 ....................................................................................................... 9 .......................................................................................................................... 9 .................................................................................................................. 10 .......................................................................................................................... 13 ........................................................................................................................ LAN........................................................................... 15 EGISTER MODEM .................................................................... 18 EGISTER ET OF ..................................................................................................................... 27 2 ................................................................ 12 ASIX ELECTRONICS CORPORATION ...
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... PACKAGE INFORMATION........................................................................................................................... 48 APPENDIX A: APPLICATION NOTE 1 ............................................................................................................. 49 A 25MH ................................................................................................................................. 49 SING RYSTAL Z A 25MH ............................................................................................................................ 49 SING SCILLATOR Z APPENDIX B: POWER CONSUMPTION REFERENCE DATA...................................................................... 50 ERRATA OF AX88790 .......................................................................................................................................... 51 DEMONSTRATION CIRCUIT (A) : AX88790 + HOMEPNA 1M8 PHY.......................................................... 52 DEMONSTRATION CIRCUIT (B) : AX88790 ONLY ....................................................................................... 57 3-in-1 PCMCIA Fast Ethernet Controller .......................................................................................................... 38 . ......................................................................................................... 39 ........................................................................................................................ 40 ................................................................................................................... 40 ....................................................................................................................... 41 3 ASIX ELECTRONICS CORPORATION ...
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... F AB ANAGEMENT RAMES 3-in-1 PCMCIA Fast Ethernet Controller FIGURES .............................................................................................................. 6 IAGRAM TABLES ........................................................................................................ 7 ....................................................................................................... 8 ....................................................................................................................... 8 I ......................................................................................... 9 NTERFACE PINS GROUP .................................................................................................... 9 ............................................................................................................... 10 ............................................................................................................. 10 ........................................................................................................................ ..................................................................................................... 12 ETUP ABLE .................................................................................................................... 13 ................................................................................................................... 13 .......................................................................................................................... LAN ............................................................. 15 EGISTER APPING MODEM ...................................................... 18 EGISTER APPING OF M ................................................................................................ 20 APPING M ................................................................................................ 21 APPING ................................................................................................................ 27 F ............................................................................................................ 39 ORMAT - D ......................................................................................... 39 FIELD ESCRIPTION 4 ASIX ELECTRONICS CORPORATION ...
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... SEEPROM EECK LOADER I/F EEDI EEDO NE2000/GPI Registers GPI Fig - 1 AX88790 Block Diagram 3-in-1 PCMCIA Fast Ethernet Controller 8K* 16 SRAM I/F and Memory Arbiter Remote DMA FIFOs PCMCIA Interface Ctl BUS SA[9:0] 5 SMDC SMDIO STA MAC TPI, TPO Core & PHY MII I/F SD[15:0] ASIX ELECTRONICS CORPORATION ...
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... MRESET# 121 MRDY 122 IOIS16# 123 STSCHG# 124 SPKR# 125 VDD 126 VSS 127 REG# 128 Fig - 2 AX88790 Pin Connection Diagram 3-in-1 PCMCIA Fast Ethernet Controller AX88790 6 ASIX ELECTRONICS CORPORATION VSS 64 VSS 63 I_ACT 62 I_SPEED 61 I_LINK 60 59 FAST_MODE# EEPROM_SIZE 58 VDD 57 VDDA 56 VSSA 55 ...
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... I/O read cycle at the address on the address bus. Card Enable : The CE1# enables even numbered address bytes and CE2# enables odd numbered address bytes 124 Battery Voltage Detect 1 / Status Change 125 Battery Voltage Detect 2 / Audio speaker out 7 Pull Up Pull Down Power Pin DESCRIPTION ASIX ELECTRONICS CORPORATION ...
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... MDIO are synchronized to the rising edge of this clock. MDC is a 2.5MHz frequency clock output. 66 Station Management Data Input / Output: Serial data input/output transfers from/to the PHYs. The transfer protocol conforms to the IEEE 802.3u MII specification. 8 DESCRIPTION DESCRIPTION ASIX ELECTRONICS CORPORATION ...
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... Link Status/Active: When I_OP is logic 0. If this signal is low, it indicates link, and high, then the link is fail. When in link status and line activity occurrence, the output will be driven low for 0.67 sec and driven high at least 0.67 sec. 9 ASIX ELECTRONICS CORPORATION ...
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... Modem Audio: This signal is passed to PCMCIA interface via SPKR. 113 Read register offset 17h bit 6 value reflects this input value. 106 Read register offset 17h bit 5 value reflects this input value. 103 Read register offset 17h bit 4 value reflects this input value. 10 Description Description ASIX ELECTRONICS CORPORATION ...
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... The Phase Detector (or PLL) power. This should be isolated with other power: +3.3V DC. 81 The Phase Detector (or PLL) power. This should be isolated with other power: + Ground. 91 Power Supply for Transceiver Output Driver: +3.3V DC. Power Supply for Transceiver Output Driver: + Ground. 11 DESCRIPTION ASIX ELECTRONICS CORPORATION ...
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... MPD_SET = 1: MPWDN pin active low. (default) PPD_SET = 0: Internal PHY in normal mode. (default) PPD_SET = 1: Internal PHY in power down mode. LED Indicator Option: Selection of LED display mode. I_OP = 0: I_LK/ACT, I_SPEED and I_FULL/COL LED display mode. I_OP = 1: I_LINK, I_SPEED and I_ACT LED display mode. (default) 12 ASIX ELECTRONICS CORPORATION ...
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... HIGH BYTE RESERVED CFH NODE-ID1 NODE ID 3 NODE ID 5 CHECKSUM RESERVED CIS CONTENTS CIS LCOR LCCSR - - LIOBASE0 LIOBASE1 RESERVED MCOR MCCSR - - MIOBASE0 MIOBASE1 RESERVED 13 ASIX ELECTRONICS CORPORATION LOW BYTE WORD COUNT CFL NODE ID 0 NODE ID 2 NODE ID 4 RESERVED RESERVED CIS ...
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... Tab – 13 Local Memory Mapping 3-in-1 PCMCIA Fast Ethernet Controller FUNCTION MAC CORE REGISTER FUNCTION CIS *1 LCOR *1 LCCSR * LIOBASE0 *1 LIOBASE1 *1 RESERVED MCOR *1 MCCSR * MIOBASE0 *1 MIOBASE1 *1 RESERVED NODE ID 0 NODE ID 1 NODE ID 2 NODE ID 3 NODE ID 4 NODE ID 5 RESERVED SRAM BUFFER 14 ASIX ELECTRONICS CORPORATION ...
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... PCMCIA Function Configuration Register Set of LAN REGISTER LCOR CONFIGURATION OPTION REGISTER LCSR CONFIGURATION AND STATUS REGISTER LIOBASE0 I/O BASED REGISTER 0 LIOBASE1 I/O BASED REGISTER 1 Tab – 14 PCMCIA Function Configuration Register Mapping of LAN 3-in-1 PCMCIA Fast Ethernet Controller NAME 15 ASIX ELECTRONICS CORPORATION OFFSET 3C0H 3C2H 3CAH 3CCH ...
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... If this bit is set to 1, the LAN function is enabled. 3-in-1 PCMCIA Fast Ethernet Controller DESCRIPTION Bit 3 LAN I/O base MODEM I/O base 0 300H Decided by MIOBASE registers 1 320H 2f8H 0 340H 3e8H 1 360H 2e8H 0 380H Decided by MIOBASE registers 1 200H 2f8H 0 220H 3e8H 1 240H 2e8H 16 ASIX ELECTRONICS CORPORATION ...
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... The I/O Base registers (LIOBASE0 and LIOBASE1) determine the base address of the I/O range used to access the LAN specific registers (MAC Core Registers). I/O Base Register 0 FIELD R/W/C 7:0 R/W Base I/O address bit 7 – 0. I/O Base Register 1 FIELD R/W/C 7:0 R/W Base I/O address bit 15 – 8. 3-in-1 PCMCIA Fast Ethernet Controller DESCRIPTION DESCRIPTION DESCRIPTION 17 ASIX ELECTRONICS CORPORATION ...
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... Base and Limit registers are passed to MODEM function. If this bit is set to 0,all I/O addresses are passed to LAN function. Bit 0 : Enable Function If this bit is set to 0, the MODEM function is disabled. If this bit is set to 1, the MODEM function is enabled. 3-in-1 PCMCIA Fast Ethernet Controller NAME DESCRIPTION 18 ASIX ELECTRONICS CORPORATION OFFSET 3E0H 3E2H 3EAH 3ECH ...
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... The I/O Base registers (MIOBASE0 and MIOBASE1) determine the base address of the I/O range used to access the MODEM specific registers. I/O Base Register 0 FIELD R/W/C 7:0 R/W Base I/O address bit 7 – 0. I/O Base Register 1 FIELD R/W/C 7:0 R/W Base I/O address bit 15 – 8. 3-in-1 PCMCIA Fast Ethernet Controller DESCRIPTION DESCRIPTION DESCRIPTION 19 ASIX ELECTRONICS CORPORATION ...
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... Remote Byte Count 0 ( RBCR0 ) Remote Byte Count 1 ( RBCR1 0 Receive Configuration Register ( RCR ) Transmit Configuration Register ( TCR ) Data Configuration Register ( DCR ) Interrupt Mask Register ( IMR ) Data Port IFGS1 IFGS2 MII/EEPROM Access Test Register Inter-frame Gap (IFG) GPOC Reserved Reserved 20 ASIX ELECTRONICS CORPORATION WRITE ...
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... MAR3 ) Multicast Address Register 4 ( MAR4 ) Multicast Address Register 5 ( MAR5 ) Multicast Address Register 6 ( MAR6 ) Multicast Address Register 7 ( MAR7 ) Data Port Inter-frame Gap Segment 1 IFGS1 Inter-frame Gap Segment 2 IFGS2 MII/EEPROM Access Test Register Inter-frame Gap (IFG) GPOC Reserved Reserved 21 ASIX ELECTRONICS CORPORATION WRITE ...
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... Packet Transmitted Indicates packet transmitted with no error 0 PRX Packet Received Indicates packet received with no error. 3-in-1 PCMCIA Fast Ethernet Controller DESCRIPTION PS0 0 page 0 1 page 1 0 Not allowed 1 Remote Read 0 Remote Write 1 Not allowed X Abort / Complete Remote DMA DESCRIPTION 22 ASIX ELECTRONICS CORPORATION ...
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... These encoded configuration bits set the type of loop-back that performed. LB1 LB0 Mode 0 0 Mode 1 0 Mode CRC Inhibit CRC 0 : CRC appended by transmitter CRC inhibited by transmitter. 3-in-1 PCMCIA Fast Ethernet Controller DESCRIPTION DESCRIPTION DESCRIPTION 0 Normal operation 1 Internal NIC loop-back 0 PHYcevisor loop-back 23 ASIX ELECTRONICS CORPORATION ...
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... Missed Packet 3 FO FIFO Overrun 2 FAE Frame alignment error CRC error. 0 PRX Packet Received Intact 4.3.9 Inter-frame gap (IFG) Offset 16H (Read/Write) FIELD NAME 7 - Reserved 6:0 IFG Inter-frame Gap. Default value 15H. 3-in-1 PCMCIA Fast Ethernet Controller DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 24 ASIX ELECTRONICS CORPORATION ...
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... RST_B Reset Busy: This signal indicates that internal PHY is in reset. 0 AUTOD Autonegotiation Done: This signal goes high whenever internal PHY autonegotiation has completed. It will go low if autonegotiation has to restart. 3-in-1 PCMCIA Fast Ethernet Controller DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 25 ASIX ELECTRONICS CORPORATION ...
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... When MPSET is logic 1, external MII PHY is selected. 4 MPSEL Media Priority Select : MPSEL I_LINK 3:0 - Reserved 3-in-1 PCMCIA Fast Ethernet Controller DESCRIPTION DESCRIPTION GPI0 Media Selected 1 0 Internal PHY 1 1 Internal PHY 0 0 External MII PHY 0 1 Internal PHY X X Depend on MPSET bit 26 ASIX ELECTRONICS CORPORATION ...
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... Device Specific 1 29 MR29 Device Specific 2 30 MR30 Device Specific 3 31 MR31 Quick Status Register Tab – 18 The Embedded PHY Registers 3-in-1 PCMCIA Fast Ethernet Controller DESCRIPTION 27 ASIX ELECTRONICS CORPORATION DEFAULT(Hex Code) 3000h 7849h 0180h BB10h 01E1h 0000 0000 0000 - 0000 0000 0000 ...
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... This bit is ignored when the autonegotiation enable bit (register 0, bit 12) is enabled. The default state This bit is ORed with the F_DUP pin. Collision Test. When this bit is set the PHY will assert the MCOL signal in response to MTX_EN. Reserved. All bits will read 0. 28 ASIX ELECTRONICS CORPORATION ...
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... Jabber Detect. This bit will whenever a jabber condition is detected. It will remain set until it is read, and the jabber condition no longer exists. Extended Capability. This bit indicates that the PHY supports the extended register set (MR2 and beyond). It will always read ASIX ELECTRONICS CORPORATION ...
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... These bits are similar to the bits defined for the MR4 register (see Table 16). Selector Field. This field contains the type of message sent by the link partner. For IEEE 802.3 compliant link partners, this field should read 00001. 30 ASIX ELECTRONICS CORPORATION ...
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... Next Page Able. This bit is set to 1, indicating that this device supports the NEXT_PAGE function. Page Received. When this bit is set indicates that a NEXT_PAGE has been received. Link Partner Autonegotiation Capable. When this bit is set indicates that the link partner is autonegotiation capable. 31 ASIX ELECTRONICS CORPORATION ...
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... PCS macro. When this bit is low, only the collision pin is disabled in loopback. Scan Test Mode. Force Loopback. Force a loopback without forcing idle on the transmit side or disabling the collision pin. Speedup Counters. Reduce link monitor counter from 620 us. (Same as FASTTEST = 1.) 32 ASIX ELECTRONICS CORPORATION ...
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... Transmit Count Ack (FLP Xmit). Transmit Data Bit (FLP Xmit). Transmit Clock Bit (FLP Xmit). Transmit ability (FLP Xmit). Transmit Remaining Acknowledge (FLP Xmit). Idle (FLP Xmit). DESCRIPTION The data written into this user-defined register appears on the REG20_OUT[15:0] bus. 33 ASIX ELECTRONICS CORPORATION ...
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... Force Jam. This bit will latch high until read. This bit is only valid in 100Mbits/s mode. Link Up 100. This bit, when set indicates a 100Mbits/s transceiver is up and operational. Link Up 10. This bit, when set indicates a 10Mbits/s transceiver is up and operational. 34 ASIX ELECTRONICS CORPORATION ...
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... Setting this bit to 1 enables far-end fault detection and logic 0 will disable the function. Default state is 0. Fiber-Optic Mode. When this bit the PHY is in fiber-optic mode. This bit is ORed with FX_MODE. 35 ASIX ELECTRONICS CORPORATION ...
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... Selected. When the PHY is in 100Mbits/s mode, this bit will be ignored. No Link Pulse Mode. Setting this bit will allow 10Mbits/s operation with link pulses disabled. If the PHY is configured for 100Mbits/s operation, setting this bit will not affect operation. 36 ASIX ELECTRONICS CORPORATION ...
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... Complete acknowledge. 101: FLP link good check. 110: Next page wait. 111: FLP link good. Highest Autonegotiation State. These 3 bits report the state of the highest autonegotiation state reached since the last register read, as defined above for bit [31.5:3]. 37 ASIX ELECTRONICS CORPORATION ...
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... Not Valid H Not Valid Even-Byte H Not Valid High-Z WE# SD[15:8] SD[7: Even-Byte Even-Byte WE# SD[15:8] SD[7:0] X High-Z High-Z H High-Z Even-Byte H High-Z Odd-Byte H Odd-Byte Even-Byte H High-Z High-Z H Odd-Byte High-Z SD[15:8] SD[7: Even-Byte L X Odd-Byte L Odd-Byte Even-Byte Odd-Byte X ASIX ELECTRONICS CORPORATION ...
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... PHY’s pull-up resistor will pull the MDIO line to logic 1. Tab - 20 MII Management Frames- field Description 3-in-1 PCMCIA Fast Ethernet Controller (Internal PHY) MDC MDIO-OUT MDIO- (MUX (PHY_ID==10h) then S=1 else S=0 PHYAD REGAD TA DATA AAAAA RRRRR Z0 DDDDDDDDDDDDDDDD AAAAA RRRRR 10 DDDDDDDDDDDDDDDD Descriptions 39 ASIX ELECTRONICS CORPORATION Pin67 MDC Pin66 MDIO IDLE Z Z ...
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... Vout -0.3 Tl -55 SYM Min Tpy Vdd +3.14 +3.30 SYM Min Tpy Vil - Vih 1.9 Vol - Voh Vdd-0.4 Iil -1 Iol -1 SYM Min Tpy SPt3v 87 40 ASIX ELECTRONICS CORPORATION Max Units +85 C +150 C +4.6 V 5.5* V Vdd+0.5 V +220 C Max Units +75 C +3.46 V Max Units 0 0 ...
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... Set the PHY register MR0 with 0x800h (1000,0000,0000) -- bit 11 of MR0 to '1' (Power down Mode). 2. Wait for 2.5 sec 3-in-1 PCMCIA Fast Ethernet Controller Thigh Tf Tlow Tcyc Min Min 100 41 Typ. Max Units Typ. Max Units - - LClk ASIX ELECTRONICS CORPORATION ...
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... AX88790 L 3. Set the PHY register MR0 with 0x1200h(0001,0010,0000,0000) -- bit 12,9 of MR0 to '1' (auto negotiation enable and restart auto negotiation) 3-in-1 PCMCIA Fast Ethernet Controller 42 ASIX ELECTRONICS CORPORATION ...
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... Tv(WT-OE) WAIT# VALID FROM OE# Tw(WT) WAIT# PULSE WIDTH Tv(WT) DATA SETUP FOR WAIT# RELEASED 3-in-1 PCMCIA Fast Ethernet Controller TcR Ta(A) Th(A) Ta(CE) Tsu(CE) Ta(OE) Th(CE) Tw(WT) Tv(WT) Tdis(OE) DATA Valid Min 300 - - - 0 100 43 Tv(A) Tdis(CE) Typ. Max Units - - ns - 120 ns - 100 ns - 100 100 200 ASIX ELECTRONICS CORPORATION ...
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... Tsu(CE) Tsu(A-WEH) Th(CE) Tw(WE) Trec(WE) Tv(WT-WE) Tv(WT) Tw(WT) Tsu(D-WEH) DATA Input Establish Tdis(WE) Tdis(OE) Min 250 150 30 180 180 Th(OE-WE) Th(D) Ten(OE) Ten(WE) Typ. Max Units - - 200 ASIX ELECTRONICS CORPORATION ...
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... Note : The address includes REG# and CE1# signal 3-in-1 PCMCIA Fast Ethernet Controller ThA TsuREG ThREG TsuCE ThCE Tw TdrINPACK TdfINPACK Td Tdr(WT) TdfWT Tw(WT) Th DATA Valid Min - 0.5 165 ASIX ELECTRONICS CORPORATION TdrIOIS16 Typ. Max Units - ...
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... The address includes REG# and CE1# signal ** Note : There is no wait state while I/O Write operation 3-in-1 PCMCIA Fast Ethernet Controller ThA TsuREG ThREG TsuCE ThCE Tw TdrIOWR TdfWT Tw(WT) Th Tsu DATA Min 60 30 165 ASIX ELECTRONICS CORPORATION TdrIOIS16 Typ. Max Units - - ...
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... RXER data setup time 3-in-1 PCMCIA Fast Ethernet Controller Ttclk Ttch Ttcl Ttv Trclk Trch Trcl Trs Trs1 Min - - 14 140 14 140 - 140 14 140 ASIX ELECTRONICS CORPORATION Tth Trh Typ. Max Units 400 - 260 260 ...
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... AX88790 L 7.0 Package Information pin 1 b SYMBOL 3-in-1 PCMCIA Fast Ethernet Controller MILIMETER MIN. NOM 0.05 0.1 1.35 1.40 0.17 0.22 13.90 14.00 19.90 20.00 0.5 15.60 16.00 21.00 22.00 0.45 0.60 1.00 0° 48 ASIX ELECTRONICS CORPORATION MAX 0.15 1.45 1.6 0.27 14.10 20.10 16.40 23.00 0.75 7° ...
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... Note: The capacitors (33pf) may be various depend on the specification of crystal. While designing, please refer to the suggest circuit provided by crystal supplier. A.2 Using Oscillator 25MHz AX88790 XTALIN 3.3V Power OSC 25MHz 3-in-1 PCMCIA Fast Ethernet Controller CLKO25M 25MHz XTALOUT 33pf CLKO25M 25MHz XTALOUT NC 49 ASIX ELECTRONICS CORPORATION ...
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... Full traffic with 10Mbps at half-duplex mode, no LED drive 14 Full traffic with 10Mbps at full-duplex mode, no LED drive 15 Full traffic with 100Mbps at half-duplex mode, no LED drive 16 Full traffic with 100Mbps at full-duplex mode, no LED drive 3-in-1 PCMCIA Fast Ethernet Controller Test Conditions 50 ASIX ELECTRONICS CORPORATION Typical Value Units – ...
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... Solution: The defect will not affect single media application that is using embedded PHY. When using MII interface connects to external media (for example HomePNA) to come out with combo solution. Care must be taken, be sure which media is the current selected when you access PHY registers. 3-in-1 PCMCIA Fast Ethernet Controller 51 ASIX ELECTRONICS CORPORATION ...
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... STSCHG# CE1# CE1# OE# OE# WE# WE# CE2# CE2# IORD# IORD# IOWR# IOWR# RESET RESET REG# REG# SD[0..15] SA[0..9] 3.3V 3.3V GND GND VDD C33 0.01u GND ASIX ELECTRONICS CORPORATION Title PCMCIA INTERFACE Size Document Number A4 790NS2A.SCH Date: Monday, July 10, 2000 Sheet 1 of ASIX ELECTRONICS CORPORATION Rev 1.1 5 ...
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... DI NC 0.01u EEDO GND 93C56 L2 3.3V F. 1206 + 0.01u 4.7uF/16V ASIX ELECTRONICS CORPORATION Title AX88790 Size Document Number A3 790NS2A1.SCH Date: Monday, July 10, 2000 ASIX ELECTRONICS CORPORATION 3.3V C49 0.1u U1B 74LV04 3 4 U1D 74LV04 9 8 U1F 74LV04 13 12 3.3V C21 GND 0.1u Rev 1.1 Sheet ...
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... ACTLED R44 4.7K 8 RING COLLED R42 4.7K SPDLED R40 4.7K 4 PWRLED R4 4.7K R45 9.31K 1% 17 COLLED 18 ACTLED 16 SPDLED 15 PWRLED 44 RESET ASIX ELECTRONICS CORPORATION Title DP83851B Size Document Number A4 790NS2A2.SCH Date: Monday, July 10, 2000 Sheet ASIX ELECTRONICS CORPORATION HACTLED HCOLLED HSPDLED 3.3V GND Rev 1 ...
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... PCMCIA Fast Ethernet Controller C12 0.01u/2KV J5 RX- 15 RX+ 14 HACTLED 13 12 HCOLLED 11 FULLED 10 LNKLED 9 HSPDLED 8 7 SPDLED 6 LTIP 5 LRING 4 GND 3 TX- 2 TX+ 1 PCMCIA15 R27 75 ASIX ELECTRONICS CORPORATION Title 16ST009P & LHR002 Size Document Number A4 790NS2A3.SCH Date: Monday, July 10, 2000 Sheet ASIX ELECTRONICS CORPORATION Rev 1 ...
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... BLINK : Collision ON : Link BLINK : Activity OFF : 0. Full DPX BLINK : Activity ON : Link OK OFF : Link fail ON : 100M OFF : 10M ASIX ELECTRONICS CORPORATION Title RJ45 / RJ11 CONNECT & LED Size Document Number A4 790NS2A4.SCH Date: Monday, July 10, 2000 Sheet ASIX ELECTRONICS CORPORATION Rev 1 ...
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... WE# WE# CE2# CE2# IORD# IORD# IOWR# IOWR# RESET RESET REG# REG# SD[0..15] SA[0..9] 3.3V 3.3V GND GND R33 : 3.3V card tpye be used. VDD C33 0.01u GND ASIX ELECTRONICS CORPORATION Title PCMCIA INTERFACE Size Document Number A4 790TX1A.SCH Date: Monday , July 10, 2000 Sheet ASIX ELECTRONICS CORPORATION Rev 1 ...
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... 1206 EEDI EEDO 4 DO GND 0.01u 4.7uF/16V 93C56 ASIX ELECTRONICS CORPORATION Title AX88790 Size Document Number A3 790TX1A1.SCH Date: Thursday, August 31, 2000 ASIX ELECTRONICS CORPORATION 3.3V C48 0.1u U1D 74LV04 9 8 U1E 74LV04 11 10 U1F 74LV04 3. C21 NC GND 0.1u ...
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... C24 0.01u C1 0.01u/2KV C16 0.01u CHASSIS C50 0.01u 59 J5 RX 3.3V_Out 11 FULLED 10 LNKLED SPDLED GND 3 TX- 2 TX+ 1 PCMCIA15 ASIX ELECTRONICS CORPORATION Title 16ST009P Size Document Number A4 790TX1A2.SCH Date: Monday, July 10, 2000 Sheet ASIX ELECTRONICS CORPORATION Rev 1.1 ...
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... LNKLED 6 LED SPDLED 7 8 LED RJ45N Title Size A4 Date Full DPX BLINK : Activity ON : Link OK OFF : Link fail ON : 100M OFF : 10M ASIX ELECTRONICS CORPORATION RJ45 CONNECT & LED Document Number 790TX1A3.SCH Monday, July 10, 2000 Sheet ASIX ELECTRONICS CORPORATION Rev 1.1 ...