EM635327Q-10 Etron Technology, Inc., EM635327Q-10 Datasheet

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EM635327Q-10

Manufacturer Part Number
EM635327Q-10
Description
DRAM Chip, SGRAM, 1MByte, 3.3V Supply, Commercial, QFP, 100-Pin
Manufacturer
Etron Technology, Inc.
Datasheet

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Part Number:
EM635327Q-10
Manufacturer:
ETRONTECH
Quantity:
221
Features
Overview
CMOS synchronous graphics DRAM containing 8
Mbits. It is internally configured as a dual 128K x
32 DRAM with a synchronous interface (all signals
are registered on the positive edge of the clock
signal, CLK). Each of the 128K x 32 bit banks is
organized as 512 rows by 256 columns by 32 bits.
Read and write accesses to the SGRAM are burst
oriented; accesses start at a selected location and
continue for a programmed number of locations in
a programmed sequence. Accesses begin with the
registration of a BankActivate command which is
then followed by a Read or Write command.
Read or Write burst lengths of 1, 2, 4, 8, or full
Etron Technology, Inc.
1F, No. 1, Prosperity Rd. 1, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C
TEL: (886)-3-5782345 FAX: (886)-3-5779001
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
Fast access time from clock: 6.5/7.0/7.5/8.5ns
Fast clock rate: 125/110/100/83MHz
Fully synchronous operation
Internal pipelined architecture
Dual internal banks(128K x 32-bit x 2-bank)
Programmable Mode and Special Mode registers
- CAS# Latency: 1, 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst-Read-Single-Write
- Load Color or Mask register
Burst stop function
Individual byte controlled by DQM0-3
Block write and write-per-bit capability
Auto Refresh and Self Refresh
1024 refresh cycles/16ms
Single +3.3V 0.3V power supply
Interface: LVTTL compatible
JEDEC 100-pin Plastic package
- QFP (body thickness = 2.8mm)
- TQFP1.4 (body thickness = 1.4mm)
256K x 32 High Speed Synchronous Graphics DRAM(SGRAM)
The EM635327 SGRAM is a high-speed
The EM635327 provides for programmable
Key Specifications
t
t
t
t
t
Ordering Information
page, with a burst termination option. An auto
precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end
of the burst sequence. The refresh functions,
either Auto or Self Refresh are easy to use. In
addition, the EM635327 features the write-per-bit
and the masked block write functions.
and special mode register, the system can choose
the most
performance. These devices are well suited for
applications requiring high memory bandwidth,
and
functions result in a device particularly well suited
to high performance graphics applications.
CK3
RAS
AC1
AC3
RC
EM635327Q-12
EM635327R-12
EM635327TQ-12
EM636327TR-12
EM635327Q-10
EM635327R-10
EM635327TQ-10
EM635327TR-10
EM635327Q-9
EM635327R-9
EM635327TQ-9
EM635327TR-9
EM635327Q-8
EM635327R-8
EM635327TQ-8
EM635327TR-8
Part Number
Clock Cycle time(min.)
Row Active time(max.)
Access time from Read command
Access time from CLK(max.)
Row Cycle time(min.)
when
By having a programmable mode register
EM635327
suitable
combined
Frequency
100MHz
100MHz
100MHz
100MHz
110MHz
110MHz
110MHz
110MHz
125MHz
125MHz
125MHz
125MHz
83MHz
83MHz
83MHz
83MHz
modes to
with
Preliminary (10/'97)
EM635327
TQFP1.4(Forward)
TQFP1.4(Reverse)
TQFP1.4(Forward)
TQFP1.4(Reverse)
TQFP1.4(Forward)
TQFP1.4(Reverse)
TQFP1.4(Forward)
TQFP1.4(Reverse)
special
QFP(Reverse)
QFP(Reverse)
QFP(Reverse)
QFP(Reverse)
QFP(Forward)
QFP(Forward)
QFP(Forward)
QFP(Forward)
maximize
Package
6.5/7.0/7.5/8.5ns
22/24.5/27/32ns
72/81/90/108ns
48/54/60/72ns
- 8/9/10/12
8/9/10/12ns
graphics
its

EM635327Q-10 Summary of contents

Page 1

... AC1 t Access time from CLK(max.) AC3 t Row Cycle time(min.) RC Ordering Information Part Number Frequency EM635327Q-12 83MHz EM635327R-12 83MHz EM635327TQ-12 83MHz EM636327TR-12 83MHz EM635327Q-10 100MHz EM635327R-10 100MHz EM635327TQ-10 100MHz EM635327TR-10 100MHz EM635327Q-9 110MHz EM635327R-9 110MHz EM635327TQ-9 110MHz EM635327TR-9 110MHz EM635327Q-8 125MHz EM635327R-8 ...

Page 2

Block Diagram CLK CLOCK BUFFER CKE CS# RAS# COMMAND CAS# DECODER WE# DSF COLUMN COUNTER A 8 ADDRESS A 0 BUFFER REFRESH COUNTER Pin Assignment (Top View) Forward Type DQ3 DDQ DQ4 3 DQ5 ...

Page 3

Pin Descriptions Table 1 shows the details for pin number, symbol, type, and description. Pin Number Symbol Type Description 55 CLK Input Clock: CLK is driven by the system clock. All SGRAM input signals are sampled on the positive edge ...

Page 4

DSF Input Define Special Function: The DSF signal defines the operation commands in conjunction with the RAS# and CAS# and WE# signals and is latched at the positive edges of CLK. The DSF input is used to select the ...

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Operation Mode Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2 shows the truth table for the operation commands. Command BankActivate & Masked Write Disable BankActivate & Masked Write Enable BankPrecharge PrechargeAll ...

Page 6

Commands 1 BankActivate & Masked Write Disable command (RAS# = "L", CAS# = "H", WE# = "H", DSF = "L" Bank, A0-A8 = Row Address) The BankActivate command activates the idle bank designated by the BS (Bank Select) ...

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The DQs go into high-impedance at the end of the burst unless other command is initiated. The burst length, burst sequence, and CAS# latency ...

Page 8

CLK DQM COM MAND NOP READ A DQ's : "H" or "L" Read to Write Interval CLK DQM COM MAND NOP NOP CAS# latency=1 t CK1 , DQ's CAS# latency=2 t CK2 , DQ's ...

Page 9

CLK Bank, ADDRESS Col A COM M AND READ A NO CAS# latency=1 DOUT CK1 , DQ's CAS# latency=2 t CK2 , DQ's CAS# latency=3 t CK3 , DQ's Read to Precharge 6 Read ...

Page 10

DSF BankActivate command MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 Note: Only the lower byte is shown. The operation is identical for other bytes. Write Per Bit (I/O Mask) Block Diagram A write burst without auto ...

Page 11

Once the Read command is registered, the data inputs will be ignored and writes will not be executed CLK COM MAND NOP WRITE A CAS# ...

Page 12

Block Write command is used to mask specific column/byte combinations within the block. The mapping of the DQ inputs to the column/byte combinations is shown in following table. The overall Block Write mask consists of a ...

Page 13

DQ Column Address DQ Planes Inputs A2 A1 DQ0 0 0 DQ1 0 0 DQ2 0 1 DQ3 0 1 DQ4 1 0 DQ5 1 0 DQ6 1 1 DQ7 1 1 DQ8 0 0 DQ9 0 0 DQ10 0 ...

Page 14

Block Write and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "H", DSF = "H" Bank "H", A3-A7 = Column Address, DQ0-DQ31 = Column Mask) The Block Write and AutoPrecharge command performs the ...

Page 15

The mode register is divided into various fields depending on functionality. Burst Length Field (A2~A0) This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length ...

Page 16

This field specifies the number of clock cycles from the assertion of the Read command to the first read data. The minimum whole value of CAS# Latency depends on the frequency of CLK. The minimum whole value satisfying the following ...

Page 17

CAS# = "H", WE# = "L", DSF = "L") The Burst Stop command is used to terminate either fixed-length or full-page bursts. This command is only effective in a read/write burst without the auto precharge function. The ...

Page 18

CAS# = "L", WE# = "H", DSF = "L", CKE = "L", BS, A0-A8 = Don't care) The SelfRefresh is another refresh mode available in the SGRAM the preferred refresh mode for data retention and ...

Page 19

Absolute Maximum Rating Symbol Input, Output Voltage IN OUT Power Supply Voltage DD DDQ T Operating Temperature OPR T Storage Temperature STG T Soldering Temperature (10s) SOLDER P Power Dissipation D I Short Circuit ...

Page 20

Recommended D.C. Operating Conditions (V Description/Test condition Operating Current ¡Ù (min), Outputs Open Address changed once during CK Burst Length = 1 Precharge Standby Current in non-power down mode (min), CS# ¡Ù CKE ...

Page 21

Electrical Characteristics and Recommended A.C. Operating Conditions (V = 3.3V¡Ó0.3V 0~70¢J ) (Note Symbol A.C. Parameter t Row cycle time RC (same bank) t RAS# to CAS# delay RCD (same bank) t Precharge ...

Page 22

Note: 1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. 2. All voltages are referenced These parameters depend on the cycle rate and these values are measured by the ...

Page 23

Latency relationship to frequency (Unit: clock cycles) -8 Version (Calculation with t CK Clock period 72ns CK 24ns 3 12ns 6 8ns 9 -10 Version (Calculation with t CK Clock period 90ns ...

Page 24

Timing Waveforms Figure 1. AC Parameters for Write Timing CLK CK2 CKE CS# RAS WE# DSF ...

Page 25

Figure 2. AC Parameters for Read Timing CLK t t CK2 CKE CS WE# DSF RAx ...

Page 26

Figure 3. Auto Refresh (CBR CLK t CK2 CKE CS# RAS WE# DSF A0~ DQM DQ PrechargeAll AutoRefresh Command Command Preliminary (Burst Length=4, CAS# Latency=2) T6 ...

Page 27

Figure 4. Power on Sequene and Auto Refresh (CBR CLK t CK2 High level CKE is reauired CS# RAS# CAS# WE# DSF Address Key A0-A7 DQM Hi-Z ...

Page 28

Figure 5. Self Refresh Entry & Exit Cycle Clock *Note 2 *Note 1 CKE t IS CS# RAS# *Note DSF DQM Hi-Z DQ Self Refresh ...

Page 29

Figure 6.1. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency= CLK t CK1 CKE CS# RAS WE# DSF RAx A0- A7 RAx CAx DQM Hi-Z DQ ...

Page 30

Figure 6.2. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency= CLK t CK2 CKE CS# RAS WE# DSF RAx A0 -A7 CAx RAx DQM Hi-Z DQ ...

Page 31

Figure 6.3. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency= CLK t CK3 CKE CS# RAS WE# DSF RAx A0 -A7 RAx CAx DQM Hi-Z ...

Page 32

Figure 7.1. Clock Suspension During Burst Write (Using CKE) (Burst Length = 4, CAS# Latency = CLK t CK1 CKE CS# RAS WE# DSF RAx A0- A7 RAx ...

Page 33

Figure 7.2. Clock Suspension During Burst Write (Using CKE) (Burst Length=4, CAS# Latency= CLK t CK2 CKE CS# RAS WE# DSF RAx A0 -A7 RAx CAx DQM Hi-Z DQ ...

Page 34

Figure 7.3. Clock Suspension During Burst Write (Using CKE) (Burst Length=4, CAS# Latency= CLK t CK3 CKE CS# RAS WE# DSF RAx A0- A7 RAx CAx DQM DQ Hi-Z ...

Page 35

Figure 8. Power Down Mode and Clock Mask CLK t CK2 t IS CKE CS# RAS WE# BS RAx A 8 RAx A0~A7 DQM Hi-Z DQ ACTIVE STANDBY Activate Command Bank A ...

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Figure 9.1. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency= CLK t CK1 CKE CS# RAS WE# DSF RAw RAw CAw A0~ Hi-Z DQ ...

Page 37

Figure 9.2. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency= CLK t CK2 CKE CS# RAS WE# DSF RAw CAw RAw A0~ Hi-Z DQ ...

Page 38

Figure 9.3. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency= CLK t CK3 CKE CS# RAS WE# DSF RAw RAw CAw A0~ Hi-Z DQ ...

Page 39

Figure 10.1. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency= CLK t CK1 CKE CS# RAS WE# DSF RBw RBw CBw A0~ Hi-Z DQ ...

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Figure 10.2. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency= CLK t CK2 CKE CS# RAS WE# DSF RBw A0~A7 CBw RBw DQ M Hi-Z DQ ...

Page 41

Figure 10.3. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency= CLK t CK3 CKE CS# RAS WE# DSF RBw CBw A0~A7 RBw DQ M Hi-Z DQ ...

Page 42

Figure 11.1. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency= CLK t CK1 CKE High CS# RAS WE# DSF RBx RBx A0~A7 CBx t RCD t AC1 DQ ...

Page 43

Figure 11.2. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency= CLK t CK2 High CKE CS# RAS WE# DSF RBx RBx CBx A0~ RCD AC2 DQ ...

Page 44

Figure 11.3. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency= CLK t CK3 High CKE CS# RAS WE# DSF RBx CBx RBx A0~ RCD AC3 DQ ...

Page 45

Figure 12.1. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency= CLK t CK1 High CKE CS# RAS WE# DSF RAx A0~A7 RAx CAx t RCD DQ M Hi-Z ...

Page 46

Figure 12.2. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency= CLK t CK2 High CKE CS# RAS WE# DSF RAx A0~A7 RAx CAx t RCD DQ M Hi-Z ...

Page 47

Figure 12.3. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency= CLK t CK3 High CKE CS# RAS WE# DSF RAx RAx CAx A0~A7 t RCD DQ M Hi-Z ...

Page 48

Figure 13.1. Read and Write Cycle CLK t CK1 CKE CS# RAS WE# DSF RAx RAx CAx A0~ Hi-Z DQ Ax0 Ax1 Ax2 Activate Command Bank A ...

Page 49

Figure 13.2. Read and Write Cycle CLK t CK2 CKE CS# RAS WE# DSF RAx RAx CAx A0~ Hi-Z DQ Ax0 Activate Read Command Command Bank A ...

Page 50

Figure 13.3. Read and Write Cycle CLK t CK3 CKE CS# RAS WE# DSF RAx RAx CAx A0~ Hi-Z DQ Read Activate Command Command Bank A Bank ...

Page 51

Figure 14.1. Interleaving Column Read Cycle CLK t CK1 CKE CS# RAS WE# DSF RAx RBw RAx RAx RBw A0~ RCD AC1 DQM Hi-Z DQ Ax0 ...

Page 52

Figure 14.2. Interleaving Column Read Cycle CLK t CK2 CKE CS# RAS WE# DSF RAx RAx RAx CAy RAx A0~ RCD AC2 DQ M Hi-Z DQ Ax0 ...

Page 53

Figure 14.3. Interleaved Column Read Cycle CLK t CK3 CKE CS# RAS WE# DSF RAx RBx RAx CAx RBx A0~A7 t RCD DQ M Hi-Z DQ Activate Read Command ...

Page 54

Figure 15.1. Interleaved Column Write Cycle CLK t CK1 CKE CS# RAS WE# DSF RAx RBw RAx CAx RBw A0~A7 t RCD DQM t RRD Hi-Z DQ DAx0 ...

Page 55

Figure 15.2. Interleaved Column Write Cycle CLK t CK2 CKE CS WE# DSF RAx RBw RAx CAx RBw A0~A7 t RCD DQM t RRD Hi-Z DQ ...

Page 56

Figure 15.3. Interleaved Column Write Cycle CLK t CK3 CKE CS# RAS WE# DSF RAx RBw RAx CAx RBw A0~A7 t RCD > t RRD RRD(min) ...

Page 57

Figure 16.1. Auto Precharge after Read Burst CLK t CK1 High CKE CS# RAS WE# DSF RAx RBx RAx CAx RBx CBx A0~ Hi-Z DQ Ax1 Ax2 ...

Page 58

Figure 16.2. Auto Precharge after Read Burst CLK t CK2 High CKE CS# RAS DSF WE RAx RBx RAx RBx CAx A0~A7 DQM Hi-Z DQ Ax1 Ax0 Activate Read ...

Page 59

Figure 16.3. Auto Precharge after Read Burst CLK t CK3 High CKE CS# RAS WE# DSF RAx RBx CAx A0~A7 RAx RBx DQ M Hi-Z DQ Activate Activate Command ...

Page 60

Figure 17.1. Auto Precharge after Write Burst CLK t CK1 High CKE CS# RAS WE# DSF RAx RBx RAx CAx RBx CBx A0~ Hi-Z DQ DAx0 DAx1 ...

Page 61

Figure 17.2. Auto Precharge after Write Burst CLK t CK2 High CKE CS# RAS WE# DSF RAx RBx RAx CAx RBx A0~ Hi-Z DQ DAx0 DAx1 DAx2 ...

Page 62

Figure 17.3. Auto Precharge after Write Burst CLK t CK3 High CKE CS# RAS WE# DSF RAx RBx CAx A0~A7 RAx RBx DQM Hi-Z DQ DAx0 DAx1 DAx2 ...

Page 63

Figure 18.1. Full Page Read Cycle CLK t CK1 High CKE CS# RAS WE# DSF RAx RBx RAx CAx RBx A0~A7 t RRD DQ M Hi-Z DQ Ax+1 Ax+2 ...

Page 64

Figure 18.2. Full Page Read Cycle CLK t CK2 High CKE CS# RAS WE# DSF RAx RBx RAx CAx RBx A0~A7 DQM Hi Ax+1 Ax+2 Ax-2 ...

Page 65

Figure 18.3. Full Page Read Cycle CLK t CK3 High CKE CS# RAS WE# DSF RAx RBx RAx CAx RBx A0~ Hi-Z DQ Activate Read Activate Command ...

Page 66

Figure 19.1. Full Page Write Cycle CLK t CK1 High CKE CS# RAS WE# DSF RAx RBx CAx RBx RAx A0~ Hi-Z DQ DAx DAx+ 1 DAx+ ...

Page 67

Figure 19.2. Full Page Write Cycle CLK t CK2 High CKE CS# RAS WE# DSF RAx RBx RAx CAx A0~A7 RBx DQ M Hi-Z DQ DAx DAx+ 1 DAx+ ...

Page 68

Figure 19.3. Full Page Write Cycle CLK t CK3 High CKE CS# RAS WE# DSF RAx RBx RAx CAx RBx A0~ Hi-Z DQ DAx DAx+ 1 DAx+ ...

Page 69

Figure 20. Byte Write Operation CLK t CK2 High CKE C S# RAS DSF RAx A0 ~A7 CAx RAx DQM0 DQM1~3 DQ0 - DQ7 DQ8 - DQ31 ...

Page 70

Figure 21. Burst Read and Single Write Operation CLK t CK2 High CKE CS# RAS WE# DSF RAx RAx CAx A0~A7 DQM0 DQM1~3 Hi-Z DQ0 - DQ7 Ax0 Hi-Z DQ8 ...

Page 71

Figure 22. Full Page Burst Read and Single Write Operation (Burst Length=Full Page, CAS# Latency= CLK t CK3 High CKE CS# RAS WE# DSF RAv RAv CAv A0~A7 DQM0 DQM1~3 ...

Page 72

Figure 23. Random Row Read (Interleaving Banks) (Burst Length=2, CAS# Latency= CLK t CK1 High CKE Begin Auto Begin Auto Precharge Precharge Bank B Bank A CS# RAS WE# DSF BS A ...

Page 73

Figure 24. Full Page Random Column Read CLK t CK2 CKE CS# RAS WE# DSF RAx RBx RAx RBx CAx CBx A0~A7 DQM t t RRD RCD DQ Activate ...

Page 74

Figure 25. Full Page Random Column Write CLK t CK2 CKE CS# RAS WE# DSF RAx RBx RAx RBx CAx A0~A7 CBx RRD RCD DQ ...

Page 75

Figure 26.1. Precharge Termination of a Burst CLK t CK1 CKE CS# RAS WE# DSF RAx RAx CAx A0~ DAx0 DAx1 DAx2 DAx3 DAx4 Activate Precharge ...

Page 76

Figure 26.2. Precharge Termination of a Burst (Burst Length=8 or Full Page, CAS# Latency= CLK t CK2 High CKE CS# RAS WE# DSF RAx RAx CAx A0~ ...

Page 77

Figure 26.3. Precharge Termination of a Burst (Burst Length= Full Page, CAS# Latency= CLK t CK3 High CKE CS# RAS WE# DSF RAx RAx CAx A0~A7 t ...

Page 78

EtronTech 100 Pin 14x20 mm TQFP & QFP Package Outline Drawing Information PIN #1 L (L1) SECTION Symbol Definition A Overall Height A1 Stand Off A2 Body Thickness b Lead Width C Lead Thickness ...

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