PPC403GC-JA25C1 IBM Microelectronics, PPC403GC-JA25C1 Datasheet
PPC403GC-JA25C1
Related parts for PPC403GC-JA25C1
PPC403GC-JA25C1 Summary of contents
Page 1
PowerPC 403GC 32-Bit RISC Embedded Controller Features • PowerPC RISC CPU and instruction set architecture • Glueless interfaces to DRAM, SRAM, ROM, and peripherals, including byte and half-word devices • Separate instruction cache and write-back data cache, both two-way set-associative ...
Page 2
IBM PowerPC 403GC The 403GC RISC controller consists of a pipelined RISC processor core and several peripheral interface units: BIU, DMA controller, asynchronous interrupt controller, serial port, and JTAG debug port. The RISC processor core includes the internal 2KB instruction ...
Page 3
Control functions for direct-connect I/O devices and for DRAM, SRAM, or ROM banks are provided by the BIU. Burst access for SRAM, ROM, and page-mode DRAM devices is supported for cache fill and flush operations. The BIU controls the transfer ...
Page 4
IBM PowerPC 403GC Instruction Cache Unit The instruction cache unit (ICU two-way set- associative 2KB cache memory unit with enhancements to support branch prediction and folding. The ICU is organized as 64 sets of 2 lines, each line ...
Page 5
Asynchronous imprecise exceptions include system resets and machine checks. Synchronous precise exceptions include most debug exceptions, program exceptions, data storage violations, TLB misses, system calls, and alignment error exceptions. Asynchronous precise exceptions include the critical interrupt exception, external interrupts, and ...
Page 6
... The trace status signals provide trace information while in real- time trace debug mode. This mode does not alter the performance of the processor. P/N Code Table 3. PPC403GC Part Numbers MHz Part Number 25 PPC403GC-JA25C1 403GC-3BA25C1 33 PPC403GC-JA33C1 403GC-3BA33C1 40 PPC403GC-JA40C1 403GC-3BA40C1 Notes: 1 ...
Page 7
... INT4 READY BUSERROR ERROR RESET BOOTW TESTC/ [HOLDPRI] TS0 TS1 TS2 TS3 TS4 TS5 TS6 A6 • • • A29 PPC403GC RISC Controller Serial DMA Port Controls External SRAM Master Controls Interrupts SRAM/DRAM Controls DRAM Controls Trace JTAG Status Data Address Bus ...
Page 8
IBM PowerPC 403GC Pin Functional Descriptions Active-low signals are shown with overbars: DMAR0. Multiplexed signals are alphabetized under the first (unmultiplexed) signal names on the same pins. The logic symbol on the preceding page shows all 403GC signals arranged by ...
Page 9
Signal I/O Pin Ball Name Type A29 119 C13 I/O AMuxCAS 139 A8 O BootW BusError BusReq/ 135 A9 O DMADXFER CAS0 142 C8 O CAS1 143 A7 O CAS2 144 B7 O CAS3 ...
Page 10
IBM PowerPC 403GC Signal I/O Pin Ball Name Type CS2 153 D5 O CS3 152 B5 O CS4/RAS3 151 C5 O CS5/RAS2 148 B6 O CS6/RAS1 147 C6 O CS7/RAS0 146 I ...
Page 11
Signal I/O Pin Ball Name Type D22 71 M10 I/O D23 72 N10 I/O D24 73 L10 I/O D25 74 P11 I/O D26 75 M11 I/O D27 76 N11 I/O D28 77 P12 I/O D29 78 M12 I/O D30 79 ...
Page 12
IBM PowerPC 403GC Signal I/O Pin Ball Name Type DSR/CTS DTR/RTS 88 L14 O EOT0/TC0 128 A11 I/O EOT1/TC1 131 A10 I/O EOT2/TC2 132 C10 I/O EOT3/TC3/ 133 D10 I/O XSize0 Error 136 ...
Page 13
Signal I/O Pin Ball Name Type 90 K13 101 G12 102 H12 111 E12 GND 121 G8 130 B10 141 C7 150 A5 Halt HoldAck 134 B9 O HoldReq INT0 INT1 ...
Page 14
IBM PowerPC 403GC Signal I/O Pin Ball Name Type Reset 91 I/O R/W 127 C11 I/O SerClk SysClk TCK TDI TDO TestA ...
Page 15
Signal I/O Pin Ball Name Type TMS TS0 TS1 TS2 TS3 86 L13 O/I TS4 85 M14 O/I TS5 84 M13 O/I TS6 83 N14 O ...
Page 16
IBM PowerPC 403GC Signal I/O Pin Ball Name Type WBE0/A4/ 122 B13 O/I/O BE0 WBE1/A5/ 123 A13 O/I/O BE1 WBE2/A30/ 124 B12 O/I/O BE2 WBE3/A31/ 125 A12 O/I/O BE3 XmitD 87 L12 O 16 Table 4. 403GC Signal Descriptions Write ...
Page 17
Table 5. Signals Ordered by PQFP Pin Number Pin Signal Name Pin Signal Name Pin Signal Name Pin 1 GND 33 INT2 2 DMAR0 34 INT3 3 DMAR1 35 INT4 4 DMAR2 36 CINT 5 DMAR3/XREQ 37 TestC/HoldPri 69 V ...
Page 18
IBM PowerPC 403GC PQFP Mechanical Drawing (Top View) 120 121 31.2 0.25 1.228 0.01 28 0.2 1.102 0.008 160 1 0.25 Min 0.01 0.65 Basic 0.0256 0.012 18 mm Dimensions: inches Note: English dimensions are for reference only. Index Mark ...
Page 19
Table 6. Signals Ordered by PBGA Ball Assignment Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name Ball GND DD A3 DMAA1 C8 CAS0 A4 CS1 C9 Error A5 GND C10 EOT2/TC2 A6 CS7/RAS0 ...
Page 20
IBM PowerPC 403GC PBGA Mechanical Drawing (Top View) Corner shape is chamferred or rounded Dimensions: Index mark Gold gate release corresponds to A1 ball location 0. 13.5 Ref A 15.0 13.0 1.0 ...
Page 21
... F Clock frequency C PPC403GC-JA25/3BA25 31.6 29.8 PPC403GC-JA33/3BA33 PPC403GC-JA40/3BA40 Tm Case temperature C under bias: PPC403GC-JA25/33/40 is ambient A 403GC-3BA25/33/40 is Note: JMax 1. These frequencies do not account for T Table 12. Power Considerations Power dissipation is determined by operating frequency, temperature, and supply voltage, as well as external source/sink current requirements. Typical power dissipation is 0 MHz, 0. MHz ...
Page 22
IBM PowerPC 403GC DC Specifications Symbol V Input low voltage (except for SysClk Input low voltage for SysClk ILC V Input high voltage (except for SysClk Input high voltage for SysClk IHC V Output low voltage ...
Page 23
SysClk Timing Symbol Parameter F SysClk clock input frequency C T SysClk clock period Clock edge stability CS T Clock input high time CH T Clock input low time CL T Clock input ...
Page 24
IBM PowerPC 403GC Table 14. 403GC Serial Port Output Timings Symbol Parameter T T Output hold, output valid time , DTR/RTS OH1 , OV1 T T XmitD , OH2 OV2 Note: 1. Output times are measured ...
Page 25
Table 15. 403GC Synchronous Input Timings Symbol Parameter T Input setup IS1 T IS2 T D0:31 (to SysClk) IS3 T ISCAS T IS4 T IS5 T IS6 T IS7 T IS8 T IS9 T Input hold ...
Page 26
IBM PowerPC 403GC Table 16. 403GC Asynchronous Input Timings Symbol Parameter T Input hold time IH T CINT IH10 T DMAR0:3 IH11 T EOT0:3 IH12 T HALT IH13 T INT0:4 IH14 T Reset IH15 Notes: 1. During a system-initiated reset, ...
Page 27
Table 17. 403GC Synchronous Output Timings Symbol Parameter Output hold, output valid time A6:31 , OH1 OV1 T T AMuxCAS , OH2 OV2 T T BusReq , OH3 OV3 T T CAS0:3 , ...
Page 28
IBM PowerPC 403GC Output Derating for Capacitance and Voltage Derating Equations for Output Delays ...
Page 29
Output Rise and Fall Time Derating Derating Equations for Output Rise and Fall Times 2ns + 2.5ns + Output Voltage ...
Page 30
IBM PowerPC 403GC Receiver Input Voltage vs DC Input Current 100 Note: 1. Applies to receivers for asynchronous inputs on pins 2-9, 11,13, 23, 25-28, 31-38, and 91, and synchronous inputs on pins 5, ...
Page 31
Reset and HoldAck The following table summarizes the states of signals on output pins when Reset or HoldAck is active. Table 18. Signal States During Reset or Hold Acknowledge Signal Names State When Reset Active A6:29 Floating AMuxCAS Inactive (low) ...
Page 32
IBM PowerPC 403GC Transfer Size Byte 8-Bit Bus Byte Width Byte Byte Transfer Size Half-word Half-word 16-Bit Bus Byte Width Byte Byte Byte Transfer Size Word Half-word Half-word 32-Bit Bus Width Byte Byte Byte Byte Address Bus Multiplexing To support ...
Page 33
SRAM Read-Write-Read with Zero Wait and One Hold 1 SysClk 1 A6:29, WBE2[A30], WBE3[A31] R/W CSx OE 2 WBE0:3 3 WBE0:3 D0:31 BusError Bank Register Bit Settings Burst Bus SLF Mode Width Bit 13 Bit 14 Bits 15: ...
Page 34
IBM PowerPC 403GC SRAM, ROM, or I/O Write Request with Wait and Hold 1 SysClk 1 A6:29, WBE2[A30], WBE3[A31] R/W 5 CSx 4,5 OE 2,3,5 WBE0:3 D0:31 BusError Bank Register Bit Settings Burst Bus SLF Mode Width Bit 13 Bit ...
Page 35
SRAM, ROM, or I/O Read Request, Wait Extended with Ready 1 SysClk 1 A6:29, WBE2[A30], WBE3[A31] R/W 5 CSx 4,5 OE 2,3 WBE0:3 D0:31 7 Ready BusError Bank Register Bit Settings Burst Bus SLF Mode Width Bit 13 Bit 14 ...
Page 36
IBM PowerPC 403GC SRAM, ROM or I/O Burst Read with Wait and Hold 1 SysClk 1 A6:29, WBE2[A30], WBE3[A31] R/W 5 CSx 4 BLast 2,3 WBE0:3 3 BE0:3 D0:31 BusError Bank Register Bit Settings Burst Bus Ready SLF ...
Page 37
SRAM, ROM or I/O Burst Write with Wait, Burst Wait, and Hold SysClk 1 A6:29, WBE2[A30], WBE3[A31] R/W 5 CSx 4,5 OE 2,3 WBE0:3 3 BE0:3 D0:31 BusError Bank Register Bit Settings Burst Bus Ready SLF Mode Width Enable Bit ...
Page 38
IBM PowerPC 403GC DRAM 2-1-1-1 Page Mode Read 1 SysClk RAS A11:29, WBE2[A30], Row WBE3[A31] AMuxCAS R/W RAS CAS0:3 DRAMOE DRAMWE D0:31 BusError Bank Register Bit Settings Bus Ext RAS-to- SLF ERM Width Mux Bit 13 Bit 14 Bits Bit ...
Page 39
DRAM 3-2-2-2 Page Mode Write 1 SysClk RAS CAS A11:29 Row AMuxCAS R/W RAS CAS0:3 DRAMOE DRAMWE D0:31 BusError Bank Register Bit Settings Bus Ext RAS-to- SLF ERM Width Mux Bit 13 Bit 14 Bits Bit 17 15: ...
Page 40
IBM PowerPC 403GC DRAM Read-Write-Read, One Wait 1 2 SysClk RAS CAS A11:29 Row1 AMuxCAS R/W RAS CAS0:3 DRAMOE DRAMWE D0:31 BusError Bank Register Bit Settings Bus Ext RAS-to- SLF ERM Width Mux Bit 13 Bit 14 Bits Bit 17 ...
Page 41
DMA Buffered Single Transfer from Peripheral to 3-Cycle DRAM 1 2 SysClk Sync DMAR DMAA A11:29 R/W RAS CAS0:3 DRAMOE DRAMWE D0:31 OE WBE0:3 Bank Register Bit Settings Bus Ext RAS-to- SLF ERM Width Mux Bit 13 Bit 14 Bits ...
Page 42
IBM PowerPC 403GC DMA Fly-By Single Transfer, Write to 3-Cycle DRAM 1 2 SysClk Sync Sync DMAR DMAA DMADXFER A11:29 R/W RAS CAS0:3 DRAMOE DRAMWE D0:31 Bank Register Bit Settings Bus Ext RAS-to- SLF ERM Width Mux Bit 13 Bit ...
Page 43
DMA Fly-By Continuous Burst to 3-Cycle DRAM 1 SysClk Sync DMAR DMAA DMADXFER A11:29 R/W RAS CAS0:3 DRAMOE DRAMWE D0:31 Bank Register Bit Settings Bus Ext RAS-to- SLF ERM Width Mux Bit 13 Bit 14 Bits Bit 17 15:16 0 ...
Page 44
IBM PowerPC 403GC External Master Nonburst DRAM Read with HoldReq/HoldAck 1 2 SysClk Ext Bus Master HoldReq HoldAck 1 XReq R/W 1 XSize0:1 1 XAck 2 A4:31 403 Master D0:31 403 Master DRAM Control AMuxCAS RASx CAS0:3 DRAMOE DRAMWE Bank ...
Page 45
External Master DRAM Burst Write, 3-2-2-2 Page Mode SysClk Ext Bus Master XReq BSel HoldReq HoldAck 3 XReq R/W 1,2,3 XSize0:1 XAck 4 A4:31 D0:31 DRAM Control AMuxCAS RASx CAS0:3 DRAMOE DRAMWE Bank Register Bit Settings Bus ...
Page 46
IBM PowerPC 403GC 46 ...
Page 47
IBM PowerPC 403GC 47 ...
Page 48
... Copyright IBM Corporation 1996,1998. All rights reserved. Printed in the USA on recycled paper. 9-98 IBM Microelectronics, PowerPC, PowerPC Architecture, and 403GC are trademarks, IBM and the IBM logo are registered trademarks of IBM Corporation. This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility of liability for any use of the information contained herein ...