82559 Intel Corporation, 82559 Datasheet
82559
Specifications of 82559
Available stocks
Related parts for 82559
82559 Summary of contents
Page 1
... Fast Ethernet* Multifunction PCI/ CardBus Controller Networking Silicon Product Features Optimum Integration for Lowest Cost Solution — Integrated IEEE 802.3 10BASE-T and 100BASE-TX compatible PHY — Glueless 32-bit PCI master interface — Glueless CardBus master interface — Modem interface for combination ...
Page 2
... Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 82559 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. ...
Page 3
... Contents 1.0 Introduction......................................................................................................................... 1 1.1 82559 Overview .................................................................................................... 1 1.2 Features, Enhancements, and Changes to the 82559 from the 82558................. 1 1.3 Enhancements to the 82559 C-Step ..................................................................... 2 2.0 82559 Architectural Overview ............................................................................................3 2.1 Parallel Subsystem Overview................................................................................3 2.2 FIFO Subsystem Overview ................................................................................... 4 2.3 10/100 Mbps Serial CSMA/CD Unit Overview ......................................................5 2.4 10/100 Mbps Physical Layer Unit.......................................................................... 5 3.0 Signal Descriptions............................................................................................................. 7 3.1 Signal Type Definitions ......................................................................................... 7 3 ...
Page 4
... PCI Address Mapping to the Modem .................................................................. 49 6.2 Modem Read and Write Cycles .......................................................................... 49 6.3 Modem and Preboot eXtension Environment Coexistence................................. 49 6.3.1 Programming Details.............................................................................. 49 6.3.2 Support Circuitry .................................................................................... 50 7.0 82559 TCO Functionality ................................................................................................. 51 7.1 System Functionality with a TCO Controller ....................................................... 51 7.2 System Functionality without a TCO Controller .................................................. 53 7.3 TCO Interface...................................................................................................... 53 7.3.1 SMB Alert Signal (SMBALRT#).............................................................. 53 7.3.2 Alert Response Address (ARA) Cycle.................................................... 54 8 ...
Page 5
... Ethernet Card Status Change Registers ................................................ 76 9.2 Statistical Counters ............................................................................................. 79 9.3 Modem Control/Status Registers ........................................................................ 81 9.3.1 Modem Base Memory Addressing ......................................................... 81 9.3.2 Modem Base I/O Addressing ................................................................. 82 9.3.3 Modem CardBus CSTCHG Registers ....................................................82 10.0 PHY Unit Registers .......................................................................................................... 85 10.1 MDI Registers ............................................................................................. 85 10.1.1 Register 0: Control Register Bit Definitions ........................................... 85 10.1.2 Register 1: Status Register Bit Definitions ............................................ 86 Datasheet Networking Silicon — 82559 v ...
Page 6
... Electrical and Timing Specifications................................................................................. 97 12.1 Absolute Maximum Ratings ................................................................................ 97 12.2 DC Specifications ............................................................................................... 97 12.3 AC Specifications .............................................................................................. 101 12.4 Timing Specifications ........................................................................................ 102 12.4.1 Clocks Specifications ........................................................................... 102 12.4.2 Timing Parameters ............................................................................... 103 13.0 Package and Pinout Information .................................................................................... 111 13.1 Package Information ......................................................................................... 111 13.2 Pinout Information ............................................................................................. 112 13.2.1 82559 Pin Assignments ...................................................................... 112 13.2.2 82559 Ball Grid Array Diagram ........................................................... 114 vi Datasheet ...
Page 7
... Flash/Modem Timings for a Write Cycle ........................................................... 106 36 EEPROM Timings ............................................................................................. 107 37 10BASE-T NLP Timings.................................................................................... 108 38 Auto-Negotiation FLP Timings .......................................................................... 108 39 Dimension Diagram for the 82559 196-pin BGA ............................................... 111 40 82559 Ball Grid Array Diagram ......................................................................... 114 Tables 1 EEPROM Words Field Descriptions.................................................................... 35 2 4B/5B Encoder .................................................................................................... 39 3 Magnetics Modules ............................................................................................. 42 4 PCI Command Register Bits ...
Page 8
... ID Fields Programming ............................................................................ 62 8 Power Management Capability Register ............................................................. 63 9 Power Management Control and Status Register ............................................... 64 10 82559 B-step Ethernet Data Register ................................................................. 64 11 82559 C-step Ethernet Data Register ................................................................. 65 12 Power Management Control and Status Register ............................................... 67 13 Modem Status Register....................................................................................... 67 14 Modem Revision Register ................................................................................... 68 15 Ethernet Data Register ...
Page 9
... Power Management Signals"). • Added note to Section 3.3, "Local Memory Interface Signals" to leave unused Flash Address and Data pins floating. • Added Revision ID for the 82559 C-step (09H) in Section 8.1.4, "PCI Revi- sion ID Register" • Corrected values in Table 32 “100BASE-TX Voltage/Current Characteristics” ...
Page 10
... Networking Silicon Note: This page left intentionally blank. x Datasheet ...
Page 11
... This enables the 82559 to transmit data with minimum interframe spacing (IFS). The 82559 can operate in either full duplex or half duplex mode. In full duplex mode the 82559 adheres with the IEEE 802.3x Flow Control specification. Half duplex performance is enhanced by a proprietary collision reduction mechanism ...
Page 12
... PHY-based flow control removed (802.3x flow control was not removed) 1.3 Enhancements to the 82559 C-Step The success of the 82559 B-step in mobile designs has spurred the addition of several new features to the device. These enhancements integrate new capabilities into the 82559 for both CardBus and MiniPCI system designs: • ...
Page 13
... The dual function LAN and modem interface provides a complete glueless connection to the PCI bus and is compliant with the PCI Bus Specification, Revision 2.2. The 82559 provides 32 bits of addressing and data, as well as the complete control interface to operate on a PCI bus PCI target, it follows the PCI configuration format which allows all accesses to the 82559 to be automatically mapped into free memory and I/O space upon initialization of a PCI system ...
Page 14
... Networking Silicon micromachine during the processing of transmit or receive frames by the 82559. A typical micromachine function is to transfer a data buffer pointer field to the 82559 DMA unit for direct access to the data buffer. The micromachine is divided into two units, Receive Unit and Command Unit which includes transmit functions ...
Page 15
... Mbps Serial CSMA/CD Unit Overview The CSMA/CD unit of the 82559 allows connected to either 100 Mbps Ethernet network. The CSMA/CD unit performs all of the functions of the 802.3 protocol such as frame formatting, frame stripping, collision handling, deferral to link traffic, etc. The CSMA/CD unit can also be placed in a full duplex mode which allows simultaneous transmission and reception of frames ...
Page 16
... Networking Silicon Note: This page left intentionally blank. 6 Datasheet ...
Page 17
... For I/O, this is a byte address; for configuration and memory Dword address. The 82559 uses little-endian byte ordering (in other words, AD[31:24] contain the most significant byte and AD[7:0] contain the least significant byte). During the data phases, the address and data lines contain data ...
Page 18
... REQ#. Grant. The grant signal is asserted by the bus arbiter and indicates to the 82559 that access to the bus has been granted. This is a point-to- point signal and every master has its own GNT#. Interrupt A. The interrupt A signal is used to request an interrupt by the 82559 ...
Page 19
... Clockrun protocol. Clockrun. The Clockrun signal is used by the system to pause or slow down the PCI Clock signal used by the 82559 to enable or disable suspension of the PCI Clock signal or restart of the PCI clock. When the Clockrun signal is not used, this pin should be connected to an external pull-down resistor ...
Page 20
... Networking Silicon 3.3 Local Memory Interface Signals Note: All unused Flash Address and Data pins must be left floating. Some of these pins have undocumented test functionality and can cause unpredictable behavior if they are unnecessarily connected to a pull-up or pull-down resistor. Symbol Type ...
Page 21
... Address[0] output signal during nominal operation. If the modem is enabled, this pin carries modem address bit 0. When RST# is active (low), it acts as the input system type. If the 82559 is used in a CardBus system, this pin should be connected to a pull-up resistor (3 otherwise, the 82559 considers the host as a PCI system. ...
Page 22
... V in all cases. CC Name and Function Test Port. If this input pin is high, the 82559 will enable the test port. During nominal operation this pin should be connected to a pull-down resistor. Test Port Clock. This pin is used for the Test Port Clock signal. ...
Page 23
... Voltage Reference. This pin is connected to a 1.25 V ± 1% external voltage reference generator. To use the internal voltage reference source, this pin should be left floating. Under normal circumstances, the internal voltage reference should be used and this pin would be left open. Networking Silicon — 82559 13 ...
Page 24
... Networking Silicon Note: This page left intentionally blank. 14 Datasheet ...
Page 25
... Initialization Effects on 82559 Units The following table shows the effect of each of the different initialization sources on major portions of the 82559. The initialization sources are listed in order of precedence. For example, any resource that is initialized by the Software Reset is also initialized by the transition and ALTRST# and PCI RST# but not necessarily by the selective reset ...
Page 26
... transition Software Reset, Selective Reset transition a. ISOLATE# acts as reset on its trailing edge. While the 82559 is in the D3 power state, the PCI RST# initializes the 82559 on the trailing edge. b. SMB commands in process will be terminated immediately. 4.2 PCI and CardBus Interface 4 ...
Page 27
... I/O space. The 82559 treats accesses to these memory spaces differently. 4.2.1.1.1 Control/Status Register (CSR) Accesses The 82559 supports zero wait state single cycle memory or I/O mapped accesses to its CSR space. Separate BARs request 4 Kbytes of memory space and 64 bytes of I/O space to accomplish this. ...
Page 28
... IRDY#. The 82559 controls the TRDY# signal and asserts it from the data access. The 82559 allows the CPU to issue only one I/O write cycle to the Control/Status Registers, generating a disconnect by asserting the STOP# signal ...
Page 29
... Flash Buffer Accesses The CPU accesses to the Flash buffer are very slow. For this reason the 82559 issues a target- disconnect at the first data access. The 82559 asserts the STOP# signal to indicate a target- disconnect. The figures below illustrate memory CPU read and write accesses to the 128 Kbyte Flash buffer ...
Page 30
... EEPROM read is complete. The 82559 does not enforce the rule that the retried master must attempt to access the same address again in order to complete any delayed transaction. Any master access to the 82559 after the completion of the EEPROM read will be honored. ...
Page 31
... The 82559, when detecting system error, will claim the cycle if it was the target of the transaction and continue the transaction as if the address was correct. Note: The 82559 will report a system error for any parity error during an address phase, whether or not it is involved in the current transaction. ...
Page 32
... For bus master cycles, the 82559 is the initiator and the host main memory (or the PCI host bridge, depending on the configuration of the system) is the target. ...
Page 33
... The 82559, as the initiator, drives the address lines AD[31:0], the command and byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. The 82559 asserts IRDY# to support zero wait state burst cycles. The target signals the 82559 that valid data is ready to be read by asserting the TRDY# signal. ...
Page 34
... The MWI Enable bit in the 82559 Configure command should is set to 1b. If any one of the above conditions does not hold, the 82559 will use the MW command MWI cycle has started and one of the conditions is no longer valid (for example, the data space in the memory buffer is now less than CLS), then the 82559 terminates the MWI cycle at the end of the cache line ...
Page 35
... PERR# and sets the Data Parity Detected bit (PCI Configuration Status register, bit 8). In addition, if the error was detected by the 82559 during read cycles, it sets the Detected Parity Error bit (PCI Configuration Status register, bit 15). ...
Page 36
... These added power management enhancements enable the 82559 to adhere to emerging standards. The 82559 enables the host system sleep state and remain virtually connected to the network. After a power management event or link status change is detected, the 82559 will wake the host system ...
Page 37
... The 82559 can be connected to an auxiliary power source (V 1. For a topology of two 82559 devices connected by a crossed twisted-pair Ethernet cable, the deep power-down mode should be disabled enabled, the two devices may not detect each other if the operating system places them into a low power state before both nodes become active ...
Page 38
... PCI power source’s stable power signal (power good). Whenever the PCI Bus is in the B3 state, the PCI power good signal becomes inactive and the 82559 isolates itself from the PCI bus. During this state, the 82559 ignores all PCI signals including the RST# and CLK signals ...
Page 39
... While the 82559 is in the D0, D1 power state initialized by the RST# level. When the 82559 is in the D3 power state, the system bus may be in the B3 bus power state. In the B3 power state, the PCI RST# signal is undefined; however, the auxiliary power source proposal for the PCI Specification, Revision 2 ...
Page 40
... Networking Silicon The behavior of the PCI RST# signal and the internal 82559 initialization signal are shown in the figure below. PCI RST# Internal hardware reset PCI RST# Internal hardware reset ISOLATE# Internal hardware reset Figure 10. 82559 Initialization Upon PCI RST# and ISOLATE# The tables below summarizes the 82559’ ...
Page 41
... NetBIOS over TCP/IP (NBT) Query Packet (under IPv4) • Internetwork Package Exchange* (IPX) Diagnostic Packet • TCO Packet This allows the 82559 to handle various packet types. In general, the 82559 supports programmable filtering of any packet in the first 128 bytes. Datasheet Power Link State • ...
Page 42
... The 82559 link status indication circuit is capable of issuing a PME on a link status change from a valid link to an invalid link condition or vice versa. The 82559 reports a PME link status event in all power states. The PME# signal is gated by the PME Enable bit in the PMCSR and the CSMA Configure command ...
Page 43
... I/O Base Address Registers in the PCI Configuration space. While the 82559 is in the D0u, D1, D2 power state, if the 82559 receives a Magic packet, it issues a positive pulse for approximately the CSTSCHG pin. For PCI systems and in designs that support the 3-pin header standard, the CSTSCHG pin acts as the WOL signal ...
Page 44
... During these time windows, the 82559 will respond with a PCI Retry to both EEPROM and Flash accesses. The 82559 performs an automatic read of five words (0H, 1H, 2H, AH, and DH) of the EEPROM after the de-assertion of Reset. It may read six more words (BH, CH, FBH, FCH, FDH, and FEH) if the modem bit is set in the EEPROM (word AH, bit 0) ...
Page 45
... HB Packet Pointer Modem Vendor ID Modem Device ID The Signature field is a signature of 01b, indicating to the 82559 that there is a valid EEPROM present. If the Signature field is not 01b, the other bits are ignored and the default values are used. The ID bit indicates how the Subsystem ID and Subsystem Vendor ID fields are used as described in Section 8.1.12, “ ...
Page 46
... Configuration FEH Parameters Note: The IA read from the EEPROM is used by the 82559 until an IA Setup command is issued by software. The IA defined by the IA Setup command overrides the IA read from the EEPROM. 4.8 10/100 Mbps CSMA/CD Unit The 82559 CSMA/CD unit implements both the IEEE 802.3 Ethernet 10 Mbps and IEEE 802.3u Fast Ethernet 100 Mbps standards ...
Page 47
... The address bit, known as the Upper/Lower (U/L) bit, is the second least significant bit of the first byte of the IA. This bit may be used, in some cases priority indication bit. When configured to do so, the 82559 passes any frame that matches all other 47 address bits of its IA, regardless of the U/L bit value. ...
Page 48
... This structure allows the 82559 to query the PHY unit for status of the link. This register is the MDI Control Register and resides at offset 10H in the 82559 CSR. (The MDI registers are ...
Page 49
... Physical Layer Functional Description 5.1 100BASE-TX PHY Unit 5.1.1 100BASE-TX Transmit Clock Generation A 25 MHz crystal MHz oscillator is used to drive the PHY unit’s X1 and X2 pins. The PHY unit derives its internal transmit digital clocks from this crystal or oscillator input. The internal Transmit Clock signal is a derivative of the 25 MHz internal clock. The accuracy of the external crystal or oscillator must be ± ...
Page 50
... Networking Silicon Table 2. 4B/5B Encoder 5.1.2.2 100BASE-TX Scrambler and MLT-3 Encoder Data is scrambled in 100BASE-TX in order to reduce electromagnetic emissions during long transmissions of high-frequency data codes. The scrambler logic accepts 5 bits from the 4B/5B encoder block and presents the scrambled data to the MLT-3 encoder. The PHY unit implements the 11-bit stream cipher scrambler as adopted by the ANSI XT3T9 ...
Page 51
... TDN pins. The conceptual transmit differential waveform for 100 Mbps is illustrated in the following figure. (V TDP +1V 0V -1V Figure 14. Conceptual Transmit Differential Waveform Datasheet TDN Networking Silicon — 82559 ...
Page 52
... Networking Silicon The magnetics module that is external to the PHY unit converts I required by the TP-PMD specification. The same magnetics used for 100BASE-TX mode should also work in 10BASE-T mode. The following is a list of current magnetics modules available from several vendors: Table 3. ...
Page 53
... Link Integrity and Auto-Negotiation Solution The 82559 Auto-Negotiation function automatically configures the device to the technology, media, and speed to operate with its link partner. Auto-Negotiation is widely described in IEEE specification 802.3u, clause 28. The PHY unit supports 10BASE-T half duplex, 10BASE-T full duplex, 100BASE-TX half duplex, and 100BASE-TX full duplex ...
Page 54
... Networking Silicon The PHY unit auto-select function determines the operation speed of the media based on the link integrity pulses it receives Fast Link Pulses (FLPs) are detected and Normal Link Pulses (NLPs) are detected, the PHY unit defaults to 10 Mbps operation. If the PHY unit detects a speed change, it dynamically changes its transmit clock and receive clock frequencies to the appropriate value ...
Page 55
... If the PHY unit detects continuous transmission that is greater than this time period, it prevents further transmissions from onto the wire until it detects that the MAC transmit enable signal has been inactive for at least 314 ms. Datasheet and a frequency of at least 2 MHz and not more than 16 MHz. PP Networking Silicon — 82559 and frequency less than ...
Page 56
... Each bit in this table is set according to what the PHY is capable of supporting. In the case of the 82559’s PHY unit, bits and 5 (10BASE-T, 10BASE-T full duplex, 100BASE-TX, 100BASE-TX full duplex and pause [frame based flow control], respectively) are set ...
Page 57
... Ability detect either by parallel detect or auto- negotiation. Parallel Detection 10Base-T or 100Base-TX Link Ready Look at Link Pulse; LINK PASS Auto-Negotiation Complete bit set Section 10.3.12, “Register 27: PHY Unit Special Control Bit Definitions” on Networking Silicon — 82559 Auto-Negotiation FLP capable Auto-Negotiation capable = 1 Ability Match 47 ...
Page 58
... Networking Silicon Figure 16 provides possible schematic diagrams for configurations using two and three LEDs. 82559ER SpeedLED Figure 16. Two and Three LED Schematic Diagram 48 LILED ACTLED SpeedLED LILED ACTLED VCC VCC Datasheet ...
Page 59
... Flash Chip Select (FLCS#) signal to enable the target device. 6.3.1 Programming Details For designs that use both Flash and modem devices, the 82559 C-step supports the coexistence of BootROM accesses (for Preboot eXtension Environment [PXE] code) and modem: 1. Set the EEPROM’s MDM bit. ...
Page 60
... BAR to select which external device (modem or Flash) is active on the local bus through the use of the CFCS# pin. After initialization, the 82559 C-step enables the Flash on the local bus (in other words, the Boot Enable bit in the BAR equals 1b) and the modem is disabled. Following the execution of the boot code from the Flash device, the enable bit is cleared, and the modem is enabled ...
Page 61
... TCO Functionality The 82559 supports management communication to reduce Total Cost of Ownership (TCO). It has a System Management Bus (SMB) on which the 82559 is a slave device. The SMB is used as an interface between the 82559 and a TCO “entity”. The TCO entity may be a dedicated TCO controller may be direct connection to a future integrated host controller ...
Page 62
... Dx (x>0): When the 82559 low power state (D1, D2, or D3), it may receive TCO packets directly to the TCO controller. TCO packet reception is enabled by setting the receive enable command from the TCO controller. Although TCO packets can match other wake-up filters, once it is identified as a TCO packet, no further matching is performed ...
Page 63
... SMB Alert Signal (SMBALRT#) The 82559 operates in slave mode on the SMB during both read and write cycles. When the 82559 transmits data on the SMB (receive packet), it issues the SMBALRT# signal. In response to the SMBALRT# activation, the host processes the interrupt. It accesses all SMB devices simultaneously by an Alert Response Address (ARA) cycle ...
Page 64
... This forces the TCO controller to stop the session and restart it the 82559’s PHY unit is in nominal mode, the 82559 will pull-down the SMBCLK until it is ready. If the 82559 forces the SMBCLK for more then 25 ms, the TCO controller should stop the transmission and restart it ...
Page 65
... PCI and CardBus Configuration Registers The 82559 acts as both a master and a slave on the PCI bus master, the 82559 interacts with the system main memory to access data for transmission or deposit received data slave, some 82559 control structures are accessed by the host CPU to read or write information to the on-chip registers ...
Page 66
... This bit controls a device’s ability to act as a master on the PCI bus. A value of 0b disables the device from generating PCI accesses. A value of 1b allows the device to behave as a bus master. In the 82559, this bit is configurable and has a default value of 0b. This bit controls a device’s response to the memory space accesses. A value of 0b disables the device response ...
Page 67
... PCI Status Register The 82559 Status register is used to record status information for PCI bus related events. The format of this register is shown in the figure below. Detected Parity Error Signaled System Error Received Master Abort Received Target Abort Signaled Target Abort Devsel Timing ...
Page 68
... Dwords. Any value other than that is written to the register is ignored and the 82559 does not use the MWI command value other than written into the CLS register, the 82559 returns all zeroes when the CLS register is read. The figure below illustrates the format of this register ...
Page 69
... This register is expected to be written by the BIOS and the 82559 driver should not write to it. 8.1.7 PCI Latency Timer The Latency Timer register is a byte wide register. When the 82559 is acting as a bus master, this register defines the amount of time, in PCI clock cycles, that it may own the bus. 8.1.8 PCI Header Type The Header Type register is a byte read only register ...
Page 70
... Kbyte memory via the 82559 local bus. The Expansion ROM BAR can be disabled by setting the Boot Disable bit of the EEPROM (word AH, bit 11). If the Boot Disable bit is set, the 82559 returns a 0b for all bits in this address register, avoiding request of memory allocation for this space ...
Page 71
... The 82559 provides support for configurable Subsystem Vendor ID and Subsystem ID fields. After hardware reset is de-asserted, the 82559 automatically reads addresses AH through CH of the EEPROM. The first of these 16-bit values is used for controlling various 82559 functions. The second is the Subsystem ID value, and the third is the Subsystem Vendor ID value. Again, the default values for the Subsystem ID and Subsystem Vendor ID are 0H and 0H, respectively ...
Page 72
... The Revision ID is subject to change according to the silicon stepping bit 15 equals 1b, the EEPROM is invalid and the default values are used. The above table implies that if the 82559 detects the presence of an EEPROM (as indicated by a value of 01b in bits 15 and 14), then bit number 13 determines whether the values read from the EEPROM, words BH and CH, will be loaded into the Subsystem ID (word BH) and Subsystem Vendor ID (word CH) fields ...
Page 73
... The 82559 is fully compliant with the PCI Power Management Specification, Revision 2.2. 8.1.19 Next Item Pointer The Next Item Pointer is a byte register. It describes the location of the next item in the 82559’s capability list. Since power management is the last item in the list, this register is set to 0b. 8.1.20 Power Management Capabilities Register The Power Management Capabilities register is a word read only register ...
Page 74
... Data Register The data register is an 8-bit read only register that provides a mechanism for the 82559 to report state dependent maximum power consumption and heat dissipation. The value reported in this register depends on the value written to the Data Select field in the PMCSR register. The power measurements defined in this register have a dynamic range ...
Page 75
... Table 10. 82559 B-step Ethernet Data Register Data Select Table 11. 82559 C-step Ethernet Data Register Data Select Datasheet Data Scale Power Consumption = 40 (400 mW Power Dissipated = 58 (580 mW Power Dissipated = 40 (400 mW Power Dissipated = 40 (400 mW Power Dissipated = 40 (400 mW) ...
Page 76
... Networking Silicon 8.2 Function 1: Modem PCI Configuration Space In PCI systems and CardBus systems, the 82559 supports a dual function device: LAN/modem. The LAN is defined as function zero, and the modem is defined as function one. The modem function is active depending on the EEPROM setup. Modem Status ...
Page 77
... Data Parity Detect. Read Only Fast Back-to-Back Capable. Read Only Reserved. These bits are reserved and should be set to 00b. Read Only New Capability. Read Only Reserved. These bits are reserved and should be set to 0000b. Networking Silicon — 82559 Description Description 67 ...
Page 78
... Modem Memory Base Address Register The Modem Memory BAR is a Dword register that specifies the memory base address for accessing the 82559’s modem port. The required memory space is 512 bytes. The memory space is used for both control registers and CIS mapping. ...
Page 79
... Modem Power Management Capabilities Register The Modem Power Management Capabilities register is a Dword field that indicates if this function has power management capability, as well as identifying which power management capabilities are supported. The 82559 reports a value of FE31H connected to an auxiliary power source and 7E21H otherwise. 8.2.14 Modem Power Management Control/Status Register The Modem Power Management Control/Status Register is a word register ...
Page 80
... Modem Support in PCI Mode The 82559 C-step supports modem interface in PCI mode. The Modem Enable (MDM) bit in the EEPROM can be activated in PCI systems without the loss of BootROM support. In addition, BootROM support has been simplified. The 82559 C-step supports the co-existence of a BootRom Flash device and a modem device (using CFCS# with external glue logic) ...
Page 81
... EEPROM Control Register PMDR Reserved Figure 28. 82559 Control/Status Register NOTE: In Figure 28 above, SCB is defined as the System Control Block of the 82559, and PMDR is defined as the Power Management Driver Register. SCB Status Word: SCB Command Word: SCB General Pointer: PORT Interface: Flash Control Register: ...
Page 82
... I/O space that a wake-up interrupt has occurred. The PMDR is described in further detail in Management Driver Register” on page The General Control register allows the 82559 to enter the deep power-down state and provides the ability to disable the Clockrun functionality. The General Control register is described in further detail in Section 9.1.12, “ ...
Page 83
... RNR 11 MDI 10 SWI FCP 7:6 CUS 5:2 RUS 1:0 Reserved 9.1.2 System Control Block Command Word Commands for the 82559’s Command and Receive units are placed in this register by the CPU. Bits Name Specific 31:26 Interrupt Mask 23:20 CUC 19 Reserved 18:16 RUC Datasheet Description Command Unit (CU) Executed. The CX bit indicates that the CU has completed executing a command with its interrupt bit set ...
Page 84
... Interrupt Enable. When this bit is set software, the 82559 asserts an interrupt to 29 indicate the end of an MDI cycle. Ready. This bit is set the 82559 at the end of an MDI transaction. It should be reset software at the same time the command is written. ...
Page 85
... Receive FIFO). 9.1.11 Power Management Driver Register The 82559 provides an indication in memory and I/O space that a wake-up event has occurred located in the Power Management Driver (PMDR). The PMDR is used for CardBus mode only. Table 16. Power Management Driver Register Bits ...
Page 86
... In this state, the 82559 does not keep link integrity. This state is not supported for point-to-point connection of two end stations. Read/Write Clockrun Signal Disable. If this bit is set to 1b, then the 82559 will always request the PCI clock signal. This mode can be used to overcome potential receive overruns caused by Clockrun signal latencies over 5 s ...
Page 87
... The 82559 supports only the interrupt and general wake-up event bits in the card status change registers. These registers compliment the PCI Power Management registers in a non-ACPI compliant OS. They are initialized by a power-up reset on the ALTRST# pin. The location of these registers should be specified within the configuration space pointing to offset address 30H of the CSR ...
Page 88
... Default This bit is the general wake-up mask. When this bit equals 0b, it masks the Ethernet function wake-up events towards the CSTSCHG signal. It has no effect on the LAN Function Event register. The 82559 can 0b assert the CSTSCHG signal in the following configuration of masked bits: wake-up bit AND general wake-up bit, or PME Enable bit in the PMCSR register only ...
Page 89
... The 82559 provides information for network management statistics by providing on-chip statistical counters that count a variety of events associated with both transmit and receive. The counters are updated by the 82559 when it completes the processing of a frame (that is, when it has completed transmitting a frame on the link or when it has completed receiving a frame). The Statistical ...
Page 90
... Frames intended for a host whose Receive Unit is in the No Resources state fall into this category. If the 82559 is configured to Save Bad Frames and the status of the received frame indicates that bad frame, the Receive Resource Errors counter is not updated. ...
Page 91
... Transmit TCO Frames The Statistical Counters are initially set to zero by the 82559 after reset. They cannot be preset to anything other than zero. The 82559 increments the counters by internally reading them, incrementing them and writing them back. This process is invisible to the CPU and PCI bus. In addition, the counters adhere to the following rules: • ...
Page 92
... The CardBus software uses the registers to determine which event has occurred and manage the event and to control the CSTSCHG signal. The 82559 supports only the interrupt and general wake-up event bits in the CSTSCHG registers. These registers compliment the PCI Power Management registers for the use with non-ACPI compliant OS ...
Page 93
... BAM). This bit is the general wake-up mask. When this bit equals 0b, it masks the modem function wake-up events towards the CSTSCHG signal. It has no effect on the Modem Function Event register. The 82559 can 0b assert the CSTSCHG signal in the following configuration of masked bits: wake-up bit AND general wake-up bit, or PME Enable bit in the PMCSR register only ...
Page 94
... Networking Silicon Table 25. Modem Function Present State Register Bits Function 2 BVD RDY 1 BVD WP 0 Reserved 9.3.3.4 Modem Force Event Register The Modem Force Event register simulates status change events for troubleshooting purposes identical to the Ethernet Force Event register described in Register” ...
Page 95
... PHY Unit Registers The 82559 provides status and accepts management information via the Management Data Interface (MDI) within the CSR space. Acronyms mentioned in the registers are defined as follows: SC: Self cleared. RO: Read only. E: EEPROM setting affects content. LL: Latch low. LH: Latch high. 10.1 MDI Registers ...
Page 96
... Networking Silicon Bit(s) Name 9 Restart Auto- Negotiation 8 Duplex Mode 7 Collision Test 6:0 Reserved 10.1.2 Register 1: Status Register Bit Definitions Bit(s) Name 15 Reserved 14 100BASE-TX Full Duplex 13 100 Mbps Half Duplex 12 10 Mbps Full Duplex 11 10 Mbps Half Duplex 10:7 Reserved 6 Management Frames Preamble ...
Page 97
... Description This bit reflects the PHY’s link partner’s Auto- Negotiation ability. This bit is used to indicate that the 82559’s PHY unit has successfully received its link partner’s Auto- Negotiation advertising ability. This bit reflects the PHY’s link partner’s Auto- Negotiation ability. This bit reflects the PHY’ ...
Page 98
... Networking Silicon 10.1.7 Register 6: Auto-Negotiation Expansion Register Bit Definitions Bit(s) Name 15:5 Reserved 4 Parallel Detection Fault 3 Link Partner Next page Able 2 Next Page Able 1 Page Received 0 Link Partner Auto- Negotiation Able 10.2 MDI Registers Registers eight through fifteen are reserved for IEEE. ...
Page 99
... Dynamic Power-Down enabled (normal Auto-Negotiation loopback 0 = Auto-Negotiation normal mode 1 = MDI Tri-state (transmit driver tri-states Normal operation 1 = By-pass filter 0 = Normal filter operation 1 = Auto Polarity disabled 0 = Normal polarity operation 1 = 10BASE-T squelch test disable 0 = Normal squelch operation Networking Silicon — 82559 Default R 000000 ...
Page 100
... Networking Silicon Bit(s) Name 2 Extended Squelch 1 Link Integrity Disable 0 Jabber Function Disable 10.3.3 Register 18: PHY Address Register Bit(s) Name 15:5 Reserved 4:0 PHY Address 10.3.4 Register 19: 100BASE-TX Receive False Carrier Counter Bit Definitions Bit(s) Name 15:0 Receive False Carrier 10.3.5 Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions ...
Page 101
... The counter freezes when full and self-clears on read. Description This is a 16-bit counter that increments for each jabber detection event. The counter freezes when full and self-clears on read. Description Reserved for Future Use Networking Silicon — 82559 Default R Default R/W ...
Page 102
... Networking Silicon 10.3.12 Register 27: PHY Unit Special Control Bit Definitions Bit(s) Name 15:3 Reserved 2:0 LED Switch Control 92 Description These bits are reserved and should be set to 0b. Value ACTLED LILED 000 Activity Link 001 Speed Collision 010 Speed Link 011 Activity Collision ...
Page 103
... Test Port Functionality 11.1 Introduction The 82559’s NAND Tree Test Access Port (TAP) is the access point for test data to and from the device. The port provides the ability to perform basic production level testing. The port provides two functions: • The synchronous IC validation mode is used in the production of the device. This mode gives the signals their names (for example, Testability Port Clock [TCK]). • ...
Page 104
... Networking Silicon TEST = 1 TCK = 0 There are two NAND Tree chains with two separate outputs assigned to FLOE# (Chain 1) and FLWE# (Chain 2). Table 26. NAND Tree Chains (NAND Tree Output) 94 TEXEC = Chain Order Chain 1 (FLOE#) 1 RST# 2 IDSEL 3 REQ# 4 AD23 5 SERR# 6 AD22 ...
Page 105
... Tree Output) Datasheet Chain Order Chain 1 (FLOE#) 34 AD7 35 AD6 36 AD5 37 AD4 37 AD3 39 AD2 40 AD1 41 AD0 42 EECS Networking Silicon — 82559 Chain 2 (FLWE#) FLA5 FLA6 FLA7 FLA8 FLA9 FLA10 FLA11 FLA12 FLA13/EEDI FLA14/EEDO FLA15/EESK FLA16 FLCS# CFCLK CFCS# 95 ...
Page 106
... Networking Silicon Note: This page left intentionally blank. 96 Datasheet ...
Page 107
... Typical current consumption is in nominal operating conditions (V Maximum current consumption is in maximum V The 82559 supports both the PCI and CardBus interface standards. In the PCI mode, the 82559 is five volts tolerant and supports both 5 V and 3.3 V signaling environments. Table 28. PCI/CardBus Interface DC Specifications ...
Page 108
... Networking Silicon Table 28. PCI/CardBus Interface DC Specifications V Output High Voltage OHP V Output Low Voltage OLP C Input Pin Capacitance INP C CLK Pin Capacitance CLKP C IDSEL Pin Capacitance IDSEL L Pin Inductance PINP NOTES: 1. These values are only applicable in 3.3 V signaling environments (PCI or CardBus). Outside of this limit the input buffer must consume its minimum current ...
Page 109
... Figure 29. RBIAS100 Resistance Versus Transmitter Current Datasheet Condition I = -10 mA out out Condition DC ±500 RBIAS100 = 619 pins (V = 3.3 V Rbias100 585 0hm 619 Ohm 650 Ohm 20 mA 19mA Networking Silicon — 82559 Min Typical Max Units Notes 2.4 V 0.7 V Min Typical Max Units Notes ±100 ...
Page 110
... Networking Silicon Table 33. 10BASE-T Voltage/Current Characteristics Symbol Parameter Input Differential R ID10 Impedance Input Differential V IDA10 Accept Peak Voltage Input Differential V IDR10 Reject Peak Voltage Input Common Mode V ICM10 Voltage Output Differential V OD10 Peak Voltage Line Driver Supply I CCT10 Peak Current NOTES: 1 ...
Page 111
... CC * out CC * out CC = (256 for 0 < out * CC out out Condition Min 0.2V to 0.6V 0. 0.6V to 0.2V 0. Condition Networking Silicon — 82559 Max Units Notes out Eqn -32V /0.023 mA 1 Eqn 38V 1 ...
Page 112
... T4 T slew NOTES: 1. The 82559 will work with any PCI clock frequency MHz. 2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate is met across the minimum peak-to-peak portion of the clock waveform as shown in 12.4.1.2 X1 Specifications X1 serves as a signal input from an external crystal or oscillator ...
Page 113
... V_test T_val V_step V_test V_test T_on T_off V_test T_su T_h V_th inputs V_test valid V_tl Symbol PCI Level CardBus Level V 0.6V 0. 0.2V 0. Networking Silicon — 82559 V_th V_tl V_th V_tl V_test V_max Units Notes 103 ...
Page 114
... Networking Silicon Table 39. Measure and Test Condition Parameters V step V step Input Signal Edge NOTE: Input test is done with 0.1V for testing input timing. 12.4.2.2 PCI/CardBus Timings Table 40. PCI/CardBus Timing Parameters Symbol PCI CLK to Signal Valid Delay T14 t val CardBus CLK to Signal Valid Delay ...
Page 115
... Flash/Modem Interface Timings The 82559 is designed to support up to 150 nanoseconds of Flash access time. The V the Flash implementation should be connected permanently Thus, writing to the Flash is controlled only by the FLWE# pin. Table 41 provides the timing parameters for the Flash interface signals. The timing parameters are ...
Page 116
... Networking Silicon NOTES: 1. These timing specifications apply to Flash read cycles. The Flash timings referenced are 28F020-150 timings. 2. These timing specifications apply to Flash write cycles. The Flash timings referenced are 28F020-150 timings. FLADDR FLCS# FLOE# FLDATA-R IOCHRDY Figure 34. Flash/Modem Timings for a Read Cycle ...
Page 117
... EEPROM Interface Timings The 82559 is designed to support a standard 64x16 or 256x16 serial EEPROM. the timing parameters for the EEPROM interface signals. The timing parameters are illustrated in Figure 36. Table 42. EEPROM Timing Parameters Symbol T50 t Serial Clock Frequency EFSK T51 t Delay from EECS High to EESK High ...
Page 118
... Networking Silicon 12.4.2.5 PHY Timings Table 43. 10BASE-T NLP Timing Parameters Symbol T56 T NLP Width nlp_wid T57 T NLP Period nlp_per Normal Link Pulse Figure 37. 10BASE-T NLP Timings Table 44. Auto-Negotiation FLP Timing Parameters Symbol T58 T FLP Width (clock/data) flp_wid T59 T Clock Pulse to Clock Pulse Period ...
Page 119
... Table 46. Flash Timing Parameters Symbol f SMB Operating Frequency smb T84 t Data Hold Time dhs T85 t Data Setup Time dsus Datasheet Parameter Condition Min HLS Data Parameter Min 300 250 Networking Silicon — 82559 Typ Max Units 1400 ps Max Units Notes 1 MHz ns ns 109 ...
Page 120
... Networking Silicon Note: This page left intentionally blank. 110 Datasheet ...
Page 121
... Package and Pinout Information 13.1 Package Information The 82559 is a 196-pin Ball Grid Array (BGA) package. Package dimensions are shown in 39. More information on Intel device packaging is available in the Intel Packaging Handbook, which is available from the Intel Literature Center or your local Intel sales office. ...
Page 122
... Networking Silicon 13.2 Pinout Information 13.2.1 82559 Pin Assignments Table 47. 82559 Pin Assignments Pin A10 A13 B10 B13 C10 C13 D10 D13 E10 E13 F10 F13 G10 112 Name Pin NC A2 SERR# IDSEL A5 VCC ...
Page 123
... Table 47. 82559 Pin Assignments Pin G13 H10 H13 J10 J13 K10 K13 L10 L13 M10 FLA15/EESK M13 N10 FLA14/EEDO N13 P10 FLA13/EEDI P13 Datasheet Name Pin Name VCC G14 VSSPL STOP# H2 INTA VCC ...
Page 124
... CLK VIO H STOP# INTA# J PAR PERR# K AD16 VSSPP L AD14 AD15 M AD11 AD12 N VSSPP AD10 P NC VCCPP Figure 40. 82559 Ball Grid Array Diagram 114 VCCPP IDSEL AD25 PME# VCCPP AD30 VSSPP AD24 AD26 AD27 VSSPP AD31 CSTSC CLKRU REQ# ...