NH82801DBM Intel Corporation, NH82801DBM Datasheet

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NH82801DBM

Manufacturer Part Number
NH82801DBM
Description
Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M), Pb-Free SLI
Manufacturer
Intel Corporation
Datasheet

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Intel
82801DBM I/O Controller
Hub 4 Mobile (ICH4-M)
Datasheet
January 2003
Order Number: 252337-001

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NH82801DBM Summary of contents

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Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M) Datasheet January 2003 Order Number: 252337-001 ...

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... Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. Intel, Intel SpeedStep, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. ...

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Intel 82801DBM ICH4 Features PCI Bus Interface — Supports PCI Revision 2.2 Specification at 33 MHz — 133 MB/sec maximum throughput — Supports master devices on PCI — One PCI REQ/GNT pair can be given higher ...

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System Configuration 4 Processor Host Controller AGP USB (Supports 6 USB 2.0 ports) IDE-Primary IDE-Secondary Intel ® 82801DBM AC’97 Codec(s) ICH4-M LAN Connect GPIO Firmware Hub(s) LPC Interface Firmware Hubs (1-8) Super I/O Super I/O Othe ASIC Other ASICs r ...

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Contents 1 Introduction 1.1 About This Datasheet .................................................................................... 33 1.2 Overview ........................................................................................................ 36 2 Signal Description 2.1 Hub Interface to Host Controller .................................................................... 45 2.2 Link to LAN Connect ...................................................................................... 45 2.3 EEPROM Interface ........................................................................................ 46 2.4 Firmware Hub Interface ...

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LAN Controller (B1:D8:F0)............................................................................. 78 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.3 LPC Bridge (with System and Management Functions) (D31:F0) ................. 92 5.3.1 5.4 DMA Operation (D31:F0) ............................................................................... 98 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.5 PCI DMA ...................................................................................................... 102 5.5.1 ...

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General Flow of DMA Transfers .....................................................106 5.5.11 Terminal Count ...............................................................................107 5.5.12 Verify Mode.....................................................................................107 5.5.13 DMA Request Deassertion .............................................................107 5.5.14 SYNC Field / LDRQ# Rules ............................................................108 5.6 8254 Timers (D31:F0)..................................................................................109 5.6.1 5.6.2 ...

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Serial Interrupt (D31:F0) .............................................................................. 130 5.9.1 5.9.2 5.9.3 5.9.4 5.9.5 5.10 Real Time Clock (D31:F0) ........................................................................... 133 5.10.1 Update Cycles ................................................................................ 133 5.10.2 Interrupts......................................................................................... 134 5.10.3 Lockable RAM Ranges ................................................................... 134 5.10.4 Century Rollover ............................................................................. 134 5.10.5 Clearing ...

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Intel 5.12.10 Event Input Signals and Their Usage .............................................157 5.12.11 ALT Access Mode...........................................................................159 5.12.12 System Power Supplies, Planes, and Signals ................................163 5.12.13 Clock Generators ............................................................................165 5.12.14 Legacy Power Management Theory of Operation ..........................166 5.13 System Management (D31:F0)....................................................................167 5.13.1 Theory ...

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Bus Master Function ....................................................................... 178 5.15.3 Ultra ATA/33 Protocol ..................................................................... 182 5.15.4 Ultra ATA/66 Protocol ..................................................................... 184 5.15.5 Ultra ATA/100 Protocol ................................................................... 184 5.15.6 Ultra ATA/33/66/100 Timing ........................................................... 185 5.15.7 IDE Swap Bay................................................................................. 185 5.16 USB UHCI Controllers (D29:F0, ...

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Data Structures in Main Memory ....................................................210 5.17.3 USB 2.0 Enhanced Host Controller DMA .......................................210 5.17.4 Data Encoding and Bit Stuffing .......................................................213 5.17.5 Packet Formats...............................................................................213 5.17.6 USB EHCI Interrupts and Error Conditions.....................................214 5.17.7 USB EHCI Power Management......................................................214 5.17.8 Interaction with ...

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AC-Link Low Power Mode .............................................................. 253 5.19.4 AC ‘97 Cold Reset .......................................................................... 254 5.19.5 AC ‘97 Warm Reset ........................................................................ 254 5.19.6 System Reset ................................................................................. 255 5.19.7 Hardware Assist to Determine AC_SDIN Used Per Codec ............ 256 5.19.8 Software Mapping ...

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MIN_GNT — Minimum Grant Register 7.1.19 MAX_LAT — Maximum Latency Register 7.1.20 CAP_ID — Capability ID Register (LAN Controller—B1:D8:F0) .....273 7.1.21 NXT_PTR — Next Item Pointer (LAN Controller—B1:D8:F0) ........273 7.1.22 PM_CAP — Power Management Capabilities 7.1.23 PMCSR — Power ...

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MEMLIM—Memory Limit Register (HUB-PCI—D30:F0) ................ 297 8.1.19 PREF_MEM_BASE—Prefetchable Memory Base Register 8.1.20 PREF_MEM_MLT—Prefetchable Memory Limit Register 8.1.21 IOBASE_HI—I/O Base Upper 16 Bits Register 8.1.22 IOLIM_HI—I/O Limit Upper 16 Bits Register 8.1.23 INT_LINE—Interrupt Line Register (HUB-PCI—D30:F0) ............... 298 8.1.24 BRIDGE_CNT—Bridge ...

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RTC_CONF—RTC Configuration Register (LPC I/F—D31:F0)......320 9.1.26 COM_DEC—LPC I/F Communication Port Decode Ranges 9.1.27 FDD/LPT_DEC—LPC I/F FDD & LPT Decode Ranges 9.1.28 SND_DEC—LPC I/F Sound Decode Ranges 9.1.29 FWH_DEC_EN1—FWH Decode Enable 1 Register 9.1.30 GEN1_DEC—LPC I/F Generic Decode Range 1 ...

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Redirection Table............................................................................ 351 9.6 Real Time Clock Registers .......................................................................... 353 9.6.1 9.6.2 9.7 Processor Interface Registers ..................................................................... 358 9.7.1 9.7.2 9.7.3 9.7.4 9.7.5 9.8 Power Management Registers (D31:F0) ..................................................... 361 9.8.1 9.8.2 ...

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System Management TCO Registers (D31:F0) ...........................................389 9.9.1 9.9.2 9.9.3 9.9.4 9.9.5 9.9.6 9.9.7 9.9.8 9.9.9 9.9.10 TCO_WDSTATUS—TCO2 Control Register ..................................395 9.9.11 SW_IRQ_GEN—Software IRQ Generation Register......................395 9.10 General Purpose I/O Registers (D31:F0).....................................................396 9.10.1 GPIO_USE_SEL—GPIO Use Select Register ...............................397 9.10.2 GP_IO_SEL—GPIO ...

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BM_BASE — Bus Master Base Address Register 10.1.15 EXBAR — Expansion Base Address Register (IDE—D31:F1)....... 407 10.1.16 IDE_SVID — Subsystem Vendor ID Register (IDE—D31:F1)........ 407 10.1.17 IDE_SID — Subsystem ID Register (IDE—D31:F1)....................... 407 10.1.18 INTR_LN—Interrupt Line Register (IDE—D31:F1) ......................... ...

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EHCI Controller Registers (D29:F7) 12.1 USB EHCI Configuration Registers (D29:F7) ..............................................437 12.1.1 VID—Vendor ID Register (USB EHCI—D29:F7) ............................438 12.1.2 DID—Device ID Register (USB EHCI—D29:F7) ............................438 12.1.3 PCICMD—PCI Command Register (USB EHCI—D29:F7) ............439 12.1.4 PCISTS—PCI Device Status Register (USB EHCI—D29:F7) ...

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HS_Ref_V—USB HS Reference Voltage Register 12.2 Memory-Mapped I/O Registers.................................................................... 453 12.2.1 Host Controller Capability Registers ............................................... 453 12.2.2 Host Controller Operational Registers ............................................ 456 12.2.3 USB 2.0-Based Debug Port Register.............................................. 468 13 SMBus Controller Registers (D31:F3) 13.1 PCI Configuration ...

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Host_BLOCK_DB—Host Block Data Byte Register .......................482 13.2.8 PEC—Packet Error Check (PEC) Register.....................................482 13.2.9 RCV_SLVA—Receive Slave Address Register ..............................483 13.2.10 SLV_DATA—Receive Slave Data Register ....................................483 13.2.11 AUX_STS—Auxiliary Status Register.............................................483 13.2.12 AUX_CTL—Auxiliary Control Register............................................484 13.2.13 SMLINK_PIN_CTL—SMLink Pin Control Register .........................484 13.2.14 ...

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Register ................................................................. 508 14.2.8 GLOB_CNT—Global Control Register............................................ 509 14.2.9 GLOB_STA—Global Status Register ............................................. 510 14.2.10 CAS—Codec Access Semaphore Register .................................... 512 14.2.11 SDM—SDATA_IN Map Register .................................................... 513 15 AC ’97 Modem Controller Registers (D31:F6) 15.1 AC ’97 Modem ...

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Package Information 19 Testability 19.1 Test Mode Description .................................................................................579 19.2 Tri-State Mode .............................................................................................580 19.3 XOR Chain Mode.........................................................................................580 19.3.1 XOR Chain Testability Algorithm Example .....................................580 A Register Index B Register Bit Index ® Intel 82801DBM ICH4-M Datasheet .......................................................................................577 .............................................................................................................579 .............................................................................................589 ...

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Figures n System Configuration ...................................................................................... 4 2-1 Intel 2-2 Example External RTC Circuit ....................................................................... 61 2-3 Example V5REF Sequencing Circuit ............................................................. 62 4-1 Conceptual System Clock Diagram ............................................................... 72 5-1 Primary Device Status Register Error Reporting Logic.................................. 75 5-2 Secondary ...

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Power Sequencing and Reset Signal Timings.............................................571 17-19 G3 (Mechanical Off Timings..............................................................572 17- S1 Timing..............................................................................573 17- Timings ................................................................................574 17- Timings................................................................................574 17- ...

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Tables 1-1 Industry Specifications ................................................................................... 33 1-2 PCI Devices and Functions ........................................................................... 36 2-1 Hub Interface Signals .................................................................................... 45 2-2 LAN Connect Interface Signals...................................................................... 45 2-3 EEPROM Interface Signals ........................................................................... 46 2-4 Firmware Hub Interface Signals .................................................................... 46 2-5 PCI ...

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Short Message.............................................................................................123 5-22 APIC Bus Status Cycle Definition ................................................................124 5-23 Lowest Priority Message (Without Focus Processor) ..................................125 5-24 Remote Read Message ...............................................................................126 5-25 Interrupt Message Address Format .............................................................129 5-26 Interrupt Message Data Format ...................................................................130 5-27 Stop Frame Explanation ..............................................................................131 ...

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SOF Packet ................................................................................................. 202 5-73 Data Packet Format ..................................................................................... 202 5-74 Bits Maintained in Low Power States .......................................................... 206 5-75 USB Legacy Keyboard State Transitions .................................................... 208 5-76 UHCI vs. EHCI............................................................................................. 209 5-77 Debug Port Behavior ................................................................................... 221 5-78 ...

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RTC (Standard) RAM Bank .........................................................................354 9-8 PCI Configuration Map (PM—D31:F0) ........................................................361 9-9 APM Register Map.......................................................................................368 9-10 ACPI and Legacy I/O Register Map.............................................................369 9-11 TCO I/O Register Map .................................................................................389 9-12 Registers to Control GPIO ...........................................................................396 10-1 PCI Configuration Register Address ...

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XOR Chain 3 ............................................................................................... 583 19-6 XOR Chain 4-1 ............................................................................................ 584 19-7 XOR Chain 4-2 ........................................................................................... 585 19-8 XOR Chain 6 ............................................................................................... 585 19-9 LONG XOR Chain ....................................................................................... 586 A-1 Intel A-2 Intel A-3 Intel 30 ® ICH4 PCI ...

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Revision History Document Number 252337 ® Intel 82801DBM ICH4-M Datasheet Revision Description 001 Initial release Date January 2003 31 ...

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This page is intentionally left blank. ® Intel 82801DBM ICH4-M Datasheet ...

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Introduction 1.1 About This Datasheet This datasheet is intended for Original Equipment Manufacturers and BIOS vendors creating ICH4-based products. All references to ICH4 in this document refer to the ICH4-M component. This datasheet assumes a working knowledge of the ...

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Introduction Chapter 5. Functional Description Chapter 5 provides a detailed description of the functions in the ICH4. All PCI buses, devices, and functions in this datasheet are abbreviated using the following nomenclature; Bus:Device:Function. This datasheet abbreviates buses as B0 and ...

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Chapter 16. Pinout Definition Chapter 16 provides a table of each signal and its ball assignment in the 421 BGA package. Chapter 17. Electrical Characteristics Chapter 17 provides all AC and DC characteristics including detailed timing diagrams. Chapter 18. Package ...

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Introduction 1.2 Overview The ICH4 provides extensive I/O support. Functions and capabilities include: • PCI Local Bus Specification, Revision 2.2-compliant with support for 33-MHz PCI operations. • PCI slots ( supports Req/Gnt pairs) • ACPI Power Management ...

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The following sub-sections provide an overview of the ICH4 capabilities. Hub Architecture As I/O speeds increase, the demand placed on the PCI bus by the I/O bridge has become significant. With AC ’97, USB 2.0, and Ultra ATA/100, coupled with ...

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Introduction Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller) The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by-byte transfers, and channels 5–7 are hardwired to 16-bit, count-by-word ...

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LAN Controller The ICH4’s integrated LAN Controller includes a 32-bit PCI controller that provides enhanced scatter-gather bus mastering capabilities and enables the LAN Controller to perform high speed data transfers over the PCI bus. Its bus master capabilities enable the ...

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Introduction the SMBus interface (see System Management Bus (SMBus) Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Host Notify. Manageability The ICH4 integrates several functions designed to manage the system ...

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AC ’97 2.3 Controller The Audio Codec ’97, Revision 2.3 specification defines a digital interface that can be used to attach an audio codec (AC), a modem codec (MC), an audio/modem codec (AMC combination of ACs and MC. ...

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Introduction 42 This page is intentionally left blank. ® Intel 82801DBM ICH4-M Datasheet ...

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Signal Description This section provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. The “#” symbol at the end of the signal name indicates that the active, or asserted ...

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Signal Description ® Figure 2-1. Intel ICH4 Interface Signals Block Diagram AD[31:0] C/BE[3:0]# DEVSEL# FRAME# REQ[4:0]# REQ5# / REQB# / GPIO1 REQA# / GPIO0 GNT[4:0]# GNT5# / GNTB# / GPIO17 GNTA# / GPIO[16] PCICLK PCIRST# PLOCK# GPIO[24]/CLKRUN# CPUSLP# IGNNE# STPCLK# ...

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Hub Interface to Host Controller Table 2-1. Hub Interface Signals Name Type HI[11:0] I/O HI_STB / I/O HI_STBS HI_STB# / I/O HI_STBF HICOMP I/O HI_VSWING I 2.2 Link to LAN Connect Table 2-2. LAN Connect Interface Signals Name LAN_CLK ...

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Signal Description 2.3 EEPROM Interface Table 2-3. EEPROM Interface Signals Name Type EE_SHCLK EE_DIN EE_DOUT EE_CS 2.4 Firmware Hub Interface Table 2-4. Firmware Hub Interface Signals Name Type FWH[3:0] / I/O LAD[3:0] FWH[4] / I/O LFRAME# 2.5 PCI Interface Table ...

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Table 2-5. PCI Interface Signals (Sheet Name Type DEVSEL# I/O FRAME# I/O IRDY# I/O TRDY# I/O STOP# I/O PAR I/O PERR# I/O REQ[0:4]# REQ[5]# / REQ[B]# / GPIO[1] ® Intel 82801DBM ICH4-M Datasheet Device Select: The ICH4 ...

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Signal Description Table 2-5. PCI Interface Signals (Sheet Name Type GNT[0:4]# GNT[5]# / GNT[B]# / GPIO[17]# PCICLK PCIRST# PLOCK# I/O SERR# I/OD PME# I/OD CLKRUN# I/O REQ[A]# / GPIO[0] REQ[B]# / REQ[5]# / GPIO[1] GNT[A]# / GPIO[16] ...

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IDE Interface Table 2-6. IDE Interface Signals Name PDCS1#, SDCS1# PDCS3#, SDCS3# PDA[2:0], SDA[2:0] PDD[15:0], SDD[15:0] PDDREQ, SDDREQ PDDACK#, SDDACK# PDIOR# / (PDWSTB / PRDMARDY#) SDIOR# / (SDWSTB / SRDMARDY#) PDIOW# / (PDSTOP) SDIOW# / (SDSTOP) PIORDY / (PDRSTB ...

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Signal Description 2.7 LPC Interface Table 2-7. LPC Interface Signals Name Type LAD[3:0] / I/O FWH[3:0] LFRAME FWH[4] LDRQ[1:0]# I 2.8 Interrupt Interface Table 2-8. Interrupt Signals Name SERIRQ PIRQ[D:A]# PIRQ[H:E]# / GPIO[5:2] IRQ[14:15] APICCLK APICD[1:0] 50 Description ...

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USB Interface Table 2-9. USB Interface Signals Name USBP0P, USBP0N, USBP1P, USBP1N USBP2P, USBP2N, USBP3P, USBP3N USBP4P, USBP4N, USBP5P, USBP5N OC[5:0]# USBRBIAS USBRBIAS# ® Intel 82801DBM ICH4-M Datasheet Type Universal Serial Bus Port 1:0 Differential: These differential pairs are ...

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Signal Description 2.10 Power Management Interface Table 2-10. Power Management Interface Signals (Sheet Name Type THRM# THRMTRIP# SLP_S1# SLP_S3# SLP_S4# SLP_S5# PWROK PWRBTN# RI# SYS_RESET# RSMRST# LAN_RST# SUS_STAT# / LPCPD# 52 Thermal Alarm: This is an active ...

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Table 2-10. Power Management Interface Signals (Sheet Name Type C3_STAT# SUSCLK AGPBUSY# STP_PCI# STP_CPU# BATLOW# CPUPERF# SSMUXSEL VGATE / VRMPWRGD DPRSLPVR ® Intel 82801DBM ICH4-M Datasheet C3_STAT#: This signal will typically be configured as C3_STAT ...

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Signal Description 2.11 Processor Interface Table 2-11. Processor Interface Signals (Sheet Name Type A20M# CPUSLP# FERR# IGNNE# INIT# INTR NMI SMI# STPCLK# 54 Mask A20: A20M# will go active based on either setting the appropriate bit in ...

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Table 2-11. Processor Interface Signals (Sheet Name Type RCIN# A20GATE CPUPWRGD DPSLP# 2.12 SMBus Interface Table 2-12. SM Bus Interface Signals Name Type SMBDATA I/OD SMBCLK I/OD SMBALERT#/ GPIO[11] 2.13 System Management Interface Table 2-13. System Management ...

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Signal Description 2.14 Real Time Clock Interface Table 2-14. Real Time Clock Interface Name Type RTCX1 Special RTCX2 Special 2.15 Other Clocks Table 2-15. Other Clocks Name Type CLK14 CLK48 CLK66 2.16 Miscellaneous Signals Table 2-16. Miscellaneous Signals Name Type ...

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AC’97 Link Table 2-17. AC’97 Link Signals Name AC_RST# AC_SYNC AC_BIT_CLK AC_SDOUT AC_SDIN[2:0] NOTE: An integrated pull-down resistor on AC_BIT_CLK is enabled when either: - The ACLINK Shutoff bit in the AC’97 Global Control Register is set to 1, ...

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Signal Description 2.18 General Purpose I/O Table 2-18. General Purpose I/O Signals Name GPIO[43:32] GPIO[31:29] GPIO[28:27] GPIO[26] GPIO[25] GPIO[24:18] GPIO[17:16] GPIO[15:14] GPIO[13:12] GPIO[11] GPIO[10:9] GPIO[8] GPIO[7] GPIO[6] GPIO[5:2] GPIO[1:0] NOTE: Main power well GPIO will be 5-V tolerant, except for ...

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Power and Ground Table 2-19. Power and Ground Signals Name Vcc3_3 Vcc1_5 VccHI V5REF HIREF VccSus3_3 VccSus1_5 V5REF_Sus VccLAN3_3 VccLAN1_5 VccRTC VccPLL VBIAS V_CPU_IO Vss ® Intel 82801DBM ICH4-M Datasheet Description 3.3 V supply for core well I/O buffers. ...

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Signal Description 2.20 Pin Straps 2.20.1 Functional Straps The following signals are used for static configuration. They are sampled at the rising edge of PWROK to select configurations, and then revert later to their normal usage. To invoke the associated ...

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External RTC Circuitry To reduce RTC well power consumption, the ICH4 implements an internal oscillator circuit that is sensitive to step voltage changes in VccRTC and VBIAS. the circuitry required to condition these voltages to ensure correct operation of ...

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Signal Description Figure 2-3. Example V5REF Sequencing Circuit Vcc Supply To System 2.20.4 Test Signals 2.20.4.1 Test Mode Selection When PWROK is active (high) for at least 76 PCI clocks, driving RTCRST# active (low) for a number of PCI clocks ...

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Intel ICH4-M Power Planes and Pin States This chapter describes the describes the system power planes for the ICH4. In addition, the ICH4 power planes and reset pin states for various signals are presented. 3.1 Power Planes ® ...

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Intel ICH4-M Power Planes and Pin States 3.2 Integrated Pull-Ups and Pull-Downs Table 3-2. Integrated Pull-Up and Pull-Down Resistors Signal AC_BITCLK AC_RST# AC_SDIN[2:0] AC_SDOUT AC_SYNC DPRSLPVR EE_DIN EE_DOUT GNT[B:A]# / GNT[5]# / GPIO[17:16] LAD[3:0]# / FWH[3:0]# LDRQ[1:0] LAN_RXD[2:0] LAN_CLK ...

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Output and I/O Signals Planes and States Table 3-4 shows the power plane associated with the output and I/O signals, as well as the state at various times. Within the table, the following terms are used: “High-Z” “High” “Low” ...

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Intel ICH4-M Power Planes and Pin States Table 3-4. Power Plane and States for Output and I/O Signals (Sheet Power Signal Name Plane AD[31:0] Main I/O C/BE[3:0]# Main I/O CLKRUN# Main I/O DEVSEL# Main I/O FRAME# ...

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Table 3-4. Power Plane and States for Output and I/O Signals (Sheet Power Signal Name Plane PIRQ[A:H]# Main I/O SERIRQ Main I/O APICD[1:0] Main I/O USBP[5:0][P,N] Resume I/O USBRBIAS Resume I/O CPUPERF# Main I/O C3_STAT# / Main ...

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Intel ICH4-M Power Planes and Pin States Table 3-4. Power Plane and States for Output and I/O Signals (Sheet Power Signal Name Plane SMLINK[1:0] Resume I/O SPKR Main I/O AC_RST# Resume I/O AC_SDOUT Main I/O AC_SYNC ...

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Power Planes for Input Signals Table 3-5 shows the power plane associated with each input signal, as well as what device drives the signal at various times. Valid states include: • High • Low • Static: Will be high ...

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Intel ICH4-M Power Planes and Pin States Table 3-5. Power Plane for Input Signals (Sheet Signal Name Power Well RI# Resume I/O RSMRST# RTCRST# SDDREQ SERR# SIORDY SMBALERT# Resume I/O SYS_RESET# Resume I/O THRM# THRMTRIP# USBRBIAS# ...

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Intel ICH4-M System Clock Domains Table 4-1 shows the system clock domains. various system components, including the clock generator. For complete details of the system clocking solution refer to the system’s clock generator component specification. ® Table 4-1. ...

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Intel ICH4-M System Clock Domains Figure 4-1. Conceptual System Clock Diagram ICH4 32 kHz XTAL 72 66 MHz 33 MHz APIC CLK Clock 14.31818 MHz Gen. 48 MHz STP_CPU# STP_PCI# SLP_S1# 12.288 MHz AC’97 Codec(s) 50 MHz LAN Connect ...

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Functional Description This chapter describes the functions and interfaces of the ICH4. 5.1 Hub Interface to PCI Bridge (D30:F0) The hub interface to PCI Bridge resides in PCI Device 30, Function 0 on bus #0. This portion of the ...

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Functional Description Note: If the processor issues a locked cycle to a resource that is too slow (e.g., PCI), the ICH4 will not allow upstream requests to be performed until the cycle completion. This may be critical for isochronous buses ...

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Figure 5-1. Primary Device Status Register Error Reporting Logic D30:F0 BRIDGE_CNT [Parity Error Response Enable] PCI Address Parity Error Delayed Transaction Timeout Received Target Abort Figure 5-2. Secondary Status Register Error Reporting Logic PCI Delayed Transaction Timeout D31:F0 D31_ERR_CFG [SERR_DTT_EN] ...

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Functional Description Figure 5-3. NMI# Generation Logic IOCHK From SERIRQ Logic [IOCHK_NMI_EN] NMI_SC [PCI_SERR_EN] D30:F0 SECSTS [SSE] D30:F0 PDSTS [SSE] Hub Interface Parity Error Detected D30:F0 CMD [Parity Error Response] PCI Parity Error detected during AC'97, IDE or USB Master ...

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Standard PCI Bus Configuration Mechanism The PCI Bus defines a slot based “configuration space” that allows each device to contain up to eight functions with each function containing up to 256, 8-bit configuration registers. The PCI specification defines two ...

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Functional Description 5.2 LAN Controller (B1:D8:F0) The ICH4’s integrated LAN Controller includes a 32-bit PCI controller that provides enhanced scatter-gather bus mastering capabilities and enables the LAN Controller to perform high-speed data transfers over the PCI bus. Its bus master ...

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Figure 5-4. Integrated LAN Controller Block Diagram PCI Interface 5.2.1.1 Parallel Subsystem Overview The parallel subsystem is broken down into several functional blocks: a PCI bus master interface, a micromachine processing unit and its corresponding microcode ROM, and a PCI ...

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Functional Description The LAN Controller contains an interface to an external serial EEPROM. The EEPROM is used to store relevant information for a LAN connection such as node address, as well as board manufacturing and configuration information. Both read and ...

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LAN Controller PCI Bus Interface As a Fast Ethernet Controller, the role of the ICH4 integrated LAN Controller is to access transmitted data or deposit received data. The LAN Controller bus master device, will initiate memory cycles ...

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Functional Description Write Accesses: The processor, as the initiator, drives the address lines AD[31:0], the command and byte enable lines C/BE[3:0]# and the control lines IRDY# and FRAME#. It also provides the LAN Controller with valid data on each data ...

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Bus Master Operation As a PCI Bus Master, the ICH4 integrated LAN Controller initiates memory cycles to fetch data for transmission or deposit received data and for accessing the memory resident control structures. The LAN Controller performs zero wait-state ...

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Functional Description Cycle Completion: The LAN Controller completes (terminates) its initiated memory burst cycles in the following cases: • Normal Completion: All transaction data has been transferred to or from the target device (for example, host main memory). • Backoff: ...

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If any one of the above conditions does not hold, the LAN Controller will use the MW command MWI cycle has started and one of the conditions is no longer valid (for example, the data space in the ...

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Functional Description 5.2.2.3 CLOCKRUN# Signal The ICH4 receives a free-running 33-MHz clock. It does not stop based on the CLKRUN# signal and protocol. When the LAN controller runs cycles on the PCI bus, the ICH4 makes sure that the STP_PCI# ...

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D1 Power State In order for a device to meet the D1 power state requirements, as specified in the Advanced Configuration and Power Interface (ACPI) Specification, Revision 2.0, it must not allow bus transmission or interrupts; however, bus reception ...

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Functional Description 5.2.2.6 Wake-Up Events There are two types of wake-up events: “Interesting” Packets and Link Status Change. These two events are detailed below. Note: If the Wake on LAN bit in the EEPROM is not set, wake-up events are ...

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Wake on LAN* (Preboot Wake-Up) The LAN Controller enters Wake on LAN mode after reset if the Wake on LAN bit in the EEPROM is set. At this point, the LAN Controller is in the D0u state. When the ...

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Functional Description 5.2.4 CSMA/CD Unit The ICH4 integrated LAN Controller CSMA/CD unit implements both the IEEE 802.3 Ethernet 10 Mbps and IEEE 802.3u Fast Ethernet 100 Mbps standards. It performs all the CSMA/CD protocol functions (e.g., transmission, reception, collision handling, ...

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VLAN Support The LAN Controller supports the IEEE 802.1 standard VLAN. All VLAN flows will be implemented by software. The LAN Controller supports the reception of long frames, specifically frames longer than 1518 bytes, including the CRC, if software ...

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Functional Description 5.3 LPC Bridge (with System and Management Functions) (D31:F0) The LPC Bridge function of the ICH4 resides in PCI Device 31:Function 0. In addition to the LPC bridge function, D31:F0 contains other functional units including DMA, Interrupt Controllers, ...

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LPC Cycle Types The ICH4 implements all of the cycle types described in the Low Pin Count Interface Specification, Revision 1.0. Table 5-2. LPC Cycle Types Supported Cycle Type Memory Read Memory Write I/O Read I/O Write DMA Read ...

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Functional Description 5.3.1.3 Cycle Type / Direction (CYCTYPE + DIR) The ICH4 will always drive bit 0 of this field to 0. Peripherals running bus master cycles must also drive bit Table 5-4 Table 5-4. Cycle Type ...

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SYNC Time-Out There are several error cases that can occur on the LPC interface. case and the ICH4 response. ® Table 5-7. Intel ICH4 Response to Sync Failures ICH4 starts a Memory, I/O, or DMA cycle, but no device ...

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Functional Description 5.3.1.8 LFRAME# Usage Start of Cycle For Memory, I/O, and DMA cycles, the ICH4 asserts LFRAME# for 1 clock at the beginning of the cycle (Figure 5-7). During that clock, the ICH4 drives LAD[3:0] with the proper START ...

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I/O Cycles For I/O cycles targeting registers specified in the ICH4’s decode ranges, the ICH4 performs I/O cycles as defined in the LPC specification. These will be 8-bit transfers. If the processor attempts a 16-bit or 32-bit transfer, the ...

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Functional Description not part of normal system operation, but may be encountered as part of platform validation testing using custom test fixtures. Bus Master Device Mapping and START Fields Bus Masters must have a unique START field. In the case ...

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Channel Priority For priority resolution, the DMA consists of two logical channel groups: channels 0–3 and channels 4–7. Each group may be in either fixed or rotate mode, as determined by the DMA Command Register. DMA I/O slaves normally ...

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Functional Description 5.4.3 Summary of DMA Transfer Sizes Table 5-8 lists each of the DMA device transfer sizes. The column labeled “Current Byte/Word Count Register” indicates that the register contents represents either the number of bytes to transfer or the ...

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Software Commands There are three additional special software commands that the DMA controller can execute. The three software commands are: • Clear Byte Pointer Flip-Flop • Master Clear • Clear Mask Register They do not depend on any specific ...

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Functional Description 5.5 PCI DMA ICH4 provides support for the PC/PCI DMA protocol. PC/PCI DMA uses dedicated REQUEST and GRANT signals to permit PCI devices to request transfers associated with specific DMA channels. Upon receiving a request and getting control ...

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All PCI DMA expansion agents must use the channel passing protocol described above. They must also work as follows: • PCI DMA expansion agent has more than one request active, it must resend the request serial protocol after ...

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Functional Description The I/O portion of the DMA cycle generates a PCI I/O cycle to one of four I/O addresses (Table 5-10). Note that these cycles must be qualified by an active GNT# signal to the requesting device. Table 5-10. ...

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DMA Cycle Termination DMA cycles are terminated when a terminal count is reached in the DMA controller and the channel is not in autoinitialize mode, or when the PC/PCI device deasserts its request. The PC/PCI device must follow explicit ...

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Functional Description 5.5.9 Abandoning DMA Requests DMA Requests can be deasserted in two fashions: on error conditions by sending an LDRQ# message with the ‘ACT’ bit set normally through a SYNC field during the DMA transfer. This ...

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Terminal Count Terminal count is communicated through LAD[3] on the same clock that DMA channel is communicated on LAD[2:0]. This field is the CHANNEL field. Terminal count indicates the last byte of transfer, based upon the size of the ...

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Functional Description The peripheral must not assume that the next START indication from the ICH4 is another grant to the peripheral if it had indicated a SYNC value of 1001b single mode DMA device, the 8237 will re-arbitrate ...

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Timers (D31:F0) The ICH4 contains three counters which have fixed uses. All registers and functions associated with the 8254 timers are in the core well. The 8254 unit is clocked by a 14.31818-MHz clock. Counter 0, System Timer ...

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Functional Description If a counter is programmed to read/write two-byte counts, the following precaution applies: A program must not transfer control between writing the first and second byte to another routine which also writes into that same counter. Otherwise, the ...

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Counter Latch Command The Counter Latch Command, written to port 43h, latches the count of a specific counter at the time the command is received. This command is used to ensure that the count read from the counter is ...

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Functional Description 5.7 8259 Interrupt Controllers (PIC) (D31:F0) The ICH4 incorporates the functionality of two 8259 interrupt controllers that provide system interrupts for the ISA compatible interrupts. These interrupts are: system timer, keyboard controller, serial ports, parallel ports, floppy disk, ...

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Interrupt Handling 5.7.1.1 Generating Interrupts The PIC interrupt sequence involves three bits, from the IRR, ISR, and IMR, for each interrupt level. These bits are used to determine the interrupt vector returned, and status of any other pending interrupts. ...

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Functional Description 5.7.1.3 Hardware/Software Interrupt Sequence 1. One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or seen high in level mode, setting the corresponding IRR bit. 2. The PIC sends INTR active to ...

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ICW2 The second write in the sequence (ICW2) is programmed to provide bits [7:3] of the interrupt vector that will be released during an interrupt acknowledge. A different base is selected for each interrupt controller. 5.7.2.3 ICW3 The third ...

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Functional Description 5.7.4.2 Special Fully-Nested Mode This mode will be used in the case of a system where cascading is used, and the priority has to be conserved within each slave. In this case, the special fully-nested mode will be ...

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Cascade Mode The PIC in the ICH4 has one master 8259 and one slave 8259 cascaded onto the master through IRQ2. This configuration can handle separate priority levels. The master controls the slaves through a three ...

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Functional Description 5.7.5 Masking Interrupts 5.7.5.1 Masking on an Individual Interrupt Request Each interrupt request can be masked individually by the Interrupt Mask Register (IMR). This register is programmed through OCW1. Each bit in the IMR masks one interrupt channel. ...

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Advanced Interrupt Controller (APIC) (D31:F0) In addition to the standard ISA-compatible interrupt controller (PIC) described in ICH4 incorporates the Advanced Programmable Interrupt Controller (APIC). While the standard interrupt controller is intended for use in a uni-processor system, APIC can ...

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Functional Description Table 5-17. APIC Interrupt Mapping (Sheet Via IRQ # SERIRQ Yes 15 Yes 16 PIRQ[A]# 17 PIRQ[B]# 18 PIRQ[C]# 19 PIRQ[D]# 20 N/A 21 N/A 22 N/A 23 N/A NOTES: 1. IRQ ...

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When ICH4 detects a bus idle condition on the APIC Bus, and it has an interrupt to send over the APIC bus, it drives a start cycle to begin arbitration by driving bit APICCLK ...

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Functional Description EOI Message for Level Triggered Interrupts EOI messages are used by local APICs to send an EOI cycle occurring for a level-triggered interrupt to an I/O APIC. This message is needed so that the I/O APIC can differentiate ...

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Short Message Short messages are used for the delivery of Fixed, NMI, SMI, Reset, ExtINT, and Lowest Priority with Focus processor interrupts. The Delivery Mode bits (M2–M0) specify the message. All short messages take 21 cycles including the idle cycle. ...

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Functional Description Table 5-22. APIC Bus Status Cycle Definition Delivery Mode Fixed, EOI NMI, SMM, Reset, ExtINT Lowest Priority Remote Read 124 A Comments 11 Checksum OK 10 Error 01 Error 00 Checksum Error 11 Checksum OK 10 Error 01 ...

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Lowest Priority without Focus Processor (FP) Message This message format is used to deliver an interrupt in the lowest priority mode in which it does not have a Focus Process. Cycles 1 through 21 for this message is same as ...

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Functional Description Remote Read Message Remote read message is used when a local APIC wishes to read the register in another local APIC. The I/O APIC in the ICH4 neither generates or responds to this cycle. The message format is ...

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PCI Message-Based Interrupts 5.8.4.1 Theory of Operation The following scheme is only supported when the internal I/O(x) APIC is used (rather than just the 8259). The ICH4 supports the new method for PCI devices to deliver interrupts as write ...

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Functional Description 5.8.4.2 Registers and Bits Associated with PCI Interrupt Delivery Capabilities Indication The capability to support PCI interrupt delivery is indicated via ACPI configuration techniques. This involves the BIOS creating a data structure that gets reported to the ACPI ...

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Registers Associated with Processor System Bus Interrupt Delivery Capabilities Indication The capability to support Processor System Bus interrupt delivery is indicated via ACPI configuration techniques. This involves the BIOS creating a data structure that gets reported to the ACPI ...

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Functional Description Table 5-26. Interrupt Message Data Format Bit 31:16 Will always be 0000h. Trigger Mode Level Edge. Same as the corresponding bit in the I/O Redirection Table for 15 that interrupt. Delivery Status ...

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Start Frame The serial IRQ protocol has two modes of operation which affect the start frame. These two modes are: Continuous, where the ICH4 is solely responsible for generating the start frame; and Quiet, where a serial IRQ peripheral ...

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Functional Description 5.9.4 Specific Interrupts Not Supported via SERIRQ There are three interrupts seen through the serial stream which are not supported by the ICH4. These interrupts are generated internally and are not sharable with other devices within the system. ...

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Real Time Clock (D31:F0) The Real Time Clock (RTC) module provides a battery backed-up date and time keeping device with two banks of static RAM with 128 bytes each, although the first bank has 114 bytes for general purpose ...

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Functional Description 5.10.2 Interrupts The real-time clock interrupt is internally routed within the ICH4 both to the I/O APIC and the 8259 mapped to interrupt vector 8. This interrupt does not leave the ICH4, nor is it shared ...

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Table 5-29. Configuration Bits Reset By RTCRST# Assertion Bit Name FREQ_STRAP[3:0] AIE AF PWR_FLR AFTERG3_EN RTC_PWR_STS PRBTNOR_STS PME_EN RI_EN NEW_CENTURY_STS INTRD_DET TOP_SWAP RTC_EN BATLOW_EN Using a GPI to Clear CMOS A jumper on a GPI can also be used to ...

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Functional Description 5.11 Processor Interface (D31:F0) The ICH4 interfaces to the processor with a variety of signals • Standard Outputs to processor: A20M#, SMI#, NMI, INIT#, INTR, STPCLK#, IGNNE#, CPUSLP# • Standard Input from processor: FERR# • Intel SpeedStep technology ...

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Table 5-30. INIT# Going Active Cause of INIT# Going Active Shutdown special cycle from processor. PORT92 write, where INIT_NOW (bit 0) transitions from PORTCF9 write, where SYS_RST (bit 1) was a 0 and RST_CPU (bit ...

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Functional Description 5.11.1.4 NMI Non-Maskable Interrupts (NMIs) can be generated by several sources, as described in Table 5-31. NMI Sources Cause of NMI SERR# goes active (either internally, externally via SERR# signal, or via message from the MCH) IOCHK# goes ...

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Speed Strapping for Processor The ICH4 directly sets the speed straps for the processor, saving the external logic that has been needed with prior PCIsets. Refer to processor specification for speed strapping definition. The ICH4 performs the following to ...

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Functional Description 5.12 Power Management (D31:F0) The power management features include: • ACPI Power and Thermal Management Support — ACPI 24-Bit Timer — Software initiated throttling of processor performance for Thermal and Power Reduction — Hardware Override to throttle processor ...

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Intel ICH4 and System Power States Table 5-34 shows the power states defined for ICH4-based platforms. The state names generally match the corresponding ACPI states. Table 5-34. General Power States for Systems Using Intel State/ Substates Full On: ...

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Functional Description Table 5-35 shows the transitions rules among the various states. Note that transitions among the various states may appear to temporarily transition through intermediate states. For example, in going from S0 to S1-M, it may appear to pass ...

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System Power Planes The system has several independent power planes, as described in particular power plane is shut off, it should 0-V level. s Table 5-36. System Power Plane Controlled Plane SLP_S3# Processor signal SLP_S3# MAIN ...

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Functional Description Table 5-37 shows which events can cause an SMI# and SCI. Note that some events can be programmed to cause either an SMI# or SCI. The usage of the event for SCI (instead of SMI#) is typically associated ...

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Table 5-37. Causes of SMI# and SCI (Sheet Cause Device monitors match address in its range SMBus Host Controller SMBus Slave SMI message SMBus SMBALERT# signal active SMBus Host Notify message received BATLOW# assertion Access microcontroller 62h/66h ...

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Functional Description A C1, C2, C3 state ends due to a Break event. Based on the break event, the ICH4 returns the system to C0 state. events from C1 are indicated in the processor’s datasheet. Table 5-38. Break ...

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Throttling Using STPCLK# Throttling is used to lower power consumption or reduce heat. The ICH4 asserts STPCLK# to throttle the processor clock and the processor appears to temporarily enter a C2 state. After a programmable time, the ICH4 deasserts ...

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Functional Description 5.12.6 Dynamic PCI Clock Control The PCI clock can be dynamically controlled independent of any other low-power state. This control is accomplished using the CLKRUN# protocol as described in the PCI Mobile Design Guide, and is transparent to ...

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Conditions for Stopping the PCI Clock Behavioral Description • device re-asserts CLKRUN# once it has been deasserted for 3 clocks, the ICH4 stops the PCI clock by asserting the STP_PCI# signal to the clock synthesizer. 5.12.6.4 Conditions ...

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Functional Description 5.12.6.6 LPC Devices and CLKRUN LPC device (of any type) needs the 33-MHz PCI clock (e.g., for LPC DMA or LPC serial interrupt), then it can assert CLKRUN#. Note that LPC devices running DMA or bus ...

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Initiating Sleep State Sleep states (S1-M–S5) are initiated by: • Masking interrupts, turning off all bus master enable bits, setting the desired type in the SLP_TYP field, and then setting the SLP_EN bit. The hardware will then attempt to ...

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Functional Description Table 5-40. Causes of Wake Events Cause RTC Alarm Power Button GPI[0:n] USB LAN RI# AC ’97 Primary PME# Secondary PME# GST Timeout SMBALERT# SMBus Slave Message SMBus Host Notify message received PME_B0 (internal USB EHCI controller) NOTES: ...

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Sx-G3-Sx, Handling Power Failures A power failure in a mobile system is a rare event, since the power subsystem should provide sufficient warning when the batteries are low. However, if the user removes the battery or leaves the system ...

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Functional Description 5.12.8 Thermal Management The ICH4 has mechanisms to assist with managing thermal problems in the system. 5.12.8.1 THRM# Signal The THRM# signal is used as a status input for a thermal sensor. Based on the THRM# signal going ...

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Processor-Initiated Passive Cooling (Via Programmed Duty Cycle on STPCLK#) Using the THTL_EN and THTL_DTY bits, the ICH4 can force a programmed duty cycle on the STPCLK# signal. This reduces the effective instruction rate of the processor and cut its ...

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Functional Description 5.12.9.1 Intel SpeedStep Technology Processor Requirements Processors without Intel SpeedStep technology use the A20M#, IGNNE#, NMI and INTR input signals to determine the multiplier used by the processor’s PLL for the internal clock. With Intel SpeedStep technology processors, ...

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Normally, this would indicate to the system electronics that a power-on reset be performed, which would invalidate the system context. ICH4 prevents this from occurring by maintaining CPUPWRGOOD during the transition. CPUPWRGOOD must also be ...

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Functional Description Sleep Button The ACPI specification defines an optional Sleep button. It differs from the power button in that it only is a request to go from S0 to S1-M–S4 (not S5). Also state, the Power ...

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THRMTRIP# Signal If THRMTRIP# goes active, the processor is indicating an overheat condition, and the ICH4 immediately transitions state. However, since the processor has overheated, it does not respond to the ICH4’s STPCLK# pin with a ...

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Functional Description • BIOS enters ALT access mode for reading the ICH4 timer related registers. • BIOS exits ALT access mode. • BIOS continues through the execution of other needed steps and passes control to the OS. After getting control ...

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Table 5-45. Write Only Registers with Read Paths in ALT Access Mode (Sheet Restore Data I Access Addr Rds DMA Chan 3 base address 1 low byte 06h 2 DMA Chan 3 base address 2 ...

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Functional Description 5.12.11.2 PIC Reserved Bits Many bits within the PIC are reserved, and must have certain values written in order for the PIC to operate properly. Therefore, there is no need to return these values in ALT access mode. ...

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Read Only Registers with Write Paths in ALT Access Mode The registers described in restores these values after returning from a powered down state. These registers must be handled special by software. When in normal mode, writing to the ...

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Functional Description 5.12.12.4 VRMPWRGD Signal This signal is connected to the processor’s VRM and is internally AND’d with the PWROK signal that comes from the system power supply. This saves the external AND gate found in desktop systems. 5.12.12.5 VGATE ...

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Clock Generators The clock generator is expected to provide the frequencies shown in Table 5-48. Intel ICH4 Clock Inputs Clock Frequency Domain CLK66 66 MHz PCICLK 33 MHz CLK48 48 MHz CLK14 14.318 MHz AC_BIT_CLK 12.288 MHz 16.67 MHz ...

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Functional Description 5.12.14 Legacy Power Management Theory of Operation Instead of relying on ACPI software, legacy power management uses BIOS and various hardware mechanisms. ICH4 has a greatly simplified method for legacy power management compared with previous generations (e.g., the ...

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System Management (D31:F0) The ICH4 provides various functions to make a system easier to manage and to lower the Total Cost of Ownership (TCO) of the system. Features and functions can be augmented via external A/D converters and GPIO, ...

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Functional Description If the INTRUDER# signal goes inactive some point after the INTRD_DET bit is written then the INTRD_DET signal will when INTRUDER# input signal goes inactive. Note that this is slightly different ...

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The following rules/steps apply if the system state and the policy is for the ICH4 to reboot the system after a hardware lockup: 1. Upon detecting the lockup the SECOND_TO_STS bit will be set. The ICH4 ...

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Functional Description 5. After step 4 (power button override), if the user presses the power button again, the system should wake state and the processor should start executing the BIOS step 5 (power button press) ...

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WARNING important that the BIOS clears the SECOND_TO_STS bit, as the alerts will interfere with the LAN device driver from working properly. The alerts reset part of the D110 and would prevent an operating system’s device driver ...

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Functional Description Table 5-49. Alert on LAN* Message Data Field SEQ[3:0] System Power State MESSAGE1 MESSAGE2 WDSTATUS 172 Comment This is a sequence number initially 0, and increments each time the ICH4 sends a new message. Upon reaching ...

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General Purpose I/O 5.14.1 GPIO Mapping Table 5-50. GPIO Implementation (Sheet GPIO Type Input GPI[0] Only Input GPI[1] Only Input GPI[2:5] Only GPIO[6] N/A Input GPI[7] Only Input GPI[8] Only GPIO[10:9] N/A Input GPI[11] Only Input ...

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Functional Description Table 5-50. GPIO Implementation (Sheet GPIO Type Output GPO[17] Only GPIO[18:24] N/A GPIO[25] I/O GPIO[26] N/A GPIO[27:28] I/O GPIO[29:31] N/A GPIO[43:32] I/O NOTES: 1. All GPIOs default to their alternate function. 2. All inputs are ...

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IDE Controller (D31:F1) The ICH4 IDE controller features two sets of interface signals (Primary and Secondary) that can be independently enabled, tri-stated or driven low. The ICH4 IDE controller supports both legacy mode and native mode IDE interface. In ...

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Functional Description The IDE I/O ports involved in PIO transfers are decoded by the ICH4 to the IDE interface when D31:F1 I/O space is enabled and IDE decode is enabled through the IDE_TIMx registers. The IDE registers are implemented in ...

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PIO IDE Timing Modes IDE data port transaction latency consists of startup latency, cycle latency, and shutdown latency. Startup latency is incurred when a PCI master cycle targeting the IDE data port is decoded and the DA[2:0] and CSxx# ...

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Functional Description 5.15.1.6 PIO IDE Data Port Prefetching and Posting The ICH4 can be programmed via the IDETIM registers to allow data to be posted to and prefetched from the IDE data ports. Data prefetching is initiated when a data ...

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Figure 5-15. Physical Region Descriptor Table Entry Byte 3 Memory Region Physical Base Address [31:1] EOT 5.15.2.2 Line Buffer A single line buffer exists for the ICH4 Bus master IDE interface. This buffer is not shared with any other function. ...

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Functional Description Warning: In this mode, the ICH4 does not drive the PCI Interrupt associated with this function. That is only used in native mode. Native Mode In this case both the primary and secondary channels share an interrupt. It ...

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Current Base and Current Count registers. These registers hold the current value of the address and byte count loaded from the PRD table. The value in these registers is only valid when there is an active ...

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Functional Description Table 5-54. Interrupt/Active Bit Interaction Definition Interrupt Active 5.15.2.6 Error Conditions IDE devices are sector-based mass storage devices. The drivers handle errors on a sector basis; either a sector is ...

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Signal Descriptions The Ultra ATA/33 protocol requires no extra signal pins on the IDE connector. It does redefine a number of the standard IDE control signals when in Ultra ATA/33 mode. These redefinitions are shown in Table 5-55. Read ...

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Functional Description The data transfer phase continues the burst transfers with the data transmitter (ICH4 - writes, IDE device - reads) providing data and toggling STROBE. Data is transferred (latched by receiver) on each rising and falling edge of STROBE. ...

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Ultra ATA/33/66/100 Timing The timings for Ultra ATA/33/66/100 modes are programmed via the Synchronous DMA Timing Register and the IDE Configuration Register. Different timings can be programmed for each drive in the system. The Base Clock frequency for each ...

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Functional Description 5.16 USB UHCI Controllers (D29:F0, F1 and F2) The ICH4 contains three USB UHCI Host Controllers. Each Host Controller includes a root hub with two separate USB ports each, for a total of 6 USB ports. The ICH4 ...

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Transfer Descriptor (TD) Transfer Descriptors (TDs) express the characteristics of the transaction requested on USB by a client. TDs are always aligned on 16-byte boundaries, and the elements of the TD are shown in Figure 5-16. The four different ...

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Functional Description Table 5-58. TD Control and Status (Sheet Bit 31:30 Reserved. Short Packet Detect (SPD). When a packet has this bit set to 1 and the packet is an input packet queue; and ...

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Table 5-58. TD Control and Status (Sheet Bit Stalled Set the ICH4 during status updates to indicate that a serious error has occurred at the device/endpoint addressed by this TD. This ...

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Functional Description Table 5-59. TD Token Bit Maximum Length (MAXLEN). The Maximum Length field specifies the maximum number of data bytes allowed for the transfer. The Maximum Length value does not include protocol bytes, such as Packet ID (PID) and ...

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Queue Head (QH) Queue heads are special structures used to support the requirements of Control, Bulk, and Interrupt transfers. Since these TDs are not automatically retired after each use, their maintenance requirements can be reduced by putting them into ...

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Functional Description 5.16.2 Data Transfers to/from Main Memory The following sections describe the details on how HCD and the ICH4 communicate via the Schedule data structures. The discussion is organized in a top-down manner, beginning with the basics of walking ...

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Processing Transfer Descriptors The ICH4 executes a TD using the following generalized algorithm. These basic steps are common across all modes of TDs. Subsequent sections present processing steps unique to each TD mode. 1. ICH4 fetches ...

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Functional Description 5.16.2.3 Command Register, Status Register, and TD Status Bit Interaction Table 5-64. Command Register, Status Register, and TD Status Bit Interaction Condition CRC/Time Out Error Illegal PID, PID Error, Max Length (illegal) PCI Master/Target Abort Suspend Mode Resume ...

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Transfer Queuing Transfer Queues are used to implement a guaranteed data delivery stream to a USB Endpoint. Transfer Queues are composed of two parts: a Queue Header (QH) and a linked list. The linked list of TDs and QHs ...

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Functional Description Transfer Queues are based on the following characteristics: • A QH’s vertical link pointer (Queue Element Link Pointer) references the ‘Top’ queue member. A QH’s horizontal link pointer (Queue Head Link Pointer) references the “next” work element in ...

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Legends: QH.LP = Queue Head Link Pointer (or Horizontal Link Pointer) QE.LP = Queue Element Link Pointer (or Vertical Link Pointer) TD. Link Pointer QH bit bit in QH Table 5-66. ...

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Functional Description 5.16.3 Data Encoding and Bit Stuffing The USB employs NRZI data encoding (Non-Return to Zero Inverted) when transmitting packets. In NRZI encoding represented by no change in level and represented by a ...

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Table 5-67. PID Format Bit Packet Identifier Field A packet identifier (PID) immediately follows the SYNC field of every USB packet. A PID consists of a four bit packet type field followed by a four-bit check ...

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Functional Description 5.16.4.4 Address Fields Function endpoints are addressed using two fields: the function address field and the endpoint field. Table 5-69. Address Field Bit Address Field The function address (ADDR) field specifies the function, via ...

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