LSI53C895 LSI Computer Systems, Inc., LSI53C895 Datasheet
LSI53C895
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LSI53C895 Summary of contents
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... TECHNICAL MANUAL LSI53C895 PCI to Ultra2 SCSI I/O Processor with LVD Link™ Universal Transceivers Version 3 ® S14030.A ...
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... LSI Logic officer is prohibited. Document DB14-000112-01, Second Edition (December 2000) This document describes the LSI Logic LSI53C895 PCI to Ultra2 SCSI I/O Processor with LVD Link Universal Transceivers and will remain the official reference source for all revisions/releases of this product until rescinded by an update ...
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... Preface This book is the primary reference and technical manual for the LSI53C895 PCI to Ultra2 SCSI I/O Processor with LVD Link™ Universal Transceivers. It contains a complete functional description for the product and includes complete physical and electrical specifications. This technical manual assumes the user is familiar with the current and proposed standards for SCSI and PCI ...
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... LSI53C895 operating registers. Chapter 6, SCSI SCRIPTS Instruction Set information about utilizing SCSI SCRIPTS mode. Chapter 7, Electrical Characteristics pertaining to DC and AC Characteristics for the LSI53C895. Appendix A, Register Summary registers used for the LSI53C895. Appendix B, External Memory Interface Diagram Examples contains four diagram examples pertaining to the interface of the external memory ...
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Prentice Hall 113 Sylvan Avenue Englewood Cliffs, NJ 07632 (800) 947-7700 Ask for document number ISBN 0-13-796855-8, SCSI: Understanding the Small Computer System Interface LSI Logic World Wide Web Home Page www.lsilogic.com SCSI SCRIPTS™ Processors Programming Guide, Version 2.2 , ...
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Revision Record Revision Date Remarks 1.0 7/96 Initial release. 2.0 1/97 Added serial EEPROM interface; changed operation of parallel EPROM interface; added information on Ultra2 SCSI termination; added LVD electrical specifications and Ultra2 SCSI timings; added PCI configuration registers for ...
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... SCRIPTS Processor 2.3.1 2.4 Prefetching SCRIPTS Instructions 2.4.1 2.5 Designing an Ultra2 SCSI System 2.5.1 2.6 LSI53C895 Interfaces 2.6.1 2.6.2 2.6.3 Contents New Features in the LSI53C895 ® Technology SCSI Performance PCI Performance Integration Ease of Use Flexibility Reliability Testability DMA FIFO Internal SCRIPTS RAM Op Code Fetch Burst Capability Using the SCSI Clock Quadrupler ...
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... LSI53C895 Modes 2.7.1 2.7.2 2.7.3 2.8 Parity Options 2.8.1 2.8.2 2.8.3 2.9 Synchronous Operation 2.9.1 2.9.2 2.10 Interrupt Handling 2.10.1 2.10.2 2.10.3 2.10.4 2.10.5 2.10.6 2.10.7 2.11 Chained Block Moves 2.11.1 2.11.2 2.11.3 2.11.4 2.11.5 Chapter 3 PCI Functional Description 3.1 PCI Addressing 3.2 PCI Bus Commands and Functions Supported 3.3 PCI Cache Mode 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.4 Configuration Registers viii Contents PCI Cache Mode Big and Little Endian Modes Loopback Mode ...
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... Chapter 4 Signal Descriptions 4.1 Voltage Capabilities and Limitations 4.2 Internal Pull-ups on LSI53C895 Pins 4.3 Pin Descriptions Chapter 5 Registers 5.1 PCI Configuration Registers 5.2 SCSI Registers Chapter 6 SCSI SCRIPTS Instruction Set 6.1 Low-Level Register Interface Mode 6.2 High-Level SCSI SCRIPTS Mode 6.2.1 6.3 Block Move Instruction 6.3.1 6.3.2 6.4 I/O Instruction 6.4.1 6.4.2 6.5 Read/Write Instructions 6.5.1 6.5.2 6.5.3 6.5.4 6.6 Transfer Control Instruction 6 ...
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... External Memory Interface Diagram Examples Appendix C Circuit Board Layout Issues C.1 Signal Separation C.2 Routing Signal Lines C.3 Impedance Matching C.4 Termination and Stub Length C.5 Decoupling C.6 Dielectric C.7 Considerations Specific to the LSI53C895 C.7.1 C.7.2 C.7.3 C.7.4 C.7.5 C.7.6 C.7.7 Index Customer Feedback x Contents Target Timing Initiator Timing External Memory Timing RBIAS +/ Pins ...
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... Figures 1.1 LSI53C895 Chip Block Diagram 2.1 DMA FIFO Sections 2.2 LSI53C895 Host Interface SCSI Datapath 2.3 8-Bit HVD Wiring Diagram for Ultra2 SCSI 2.4 Regulated Termination for Ultra2 SCSI 2.5 Determining the Synchronous Transfer Rate 2.6 Block Move and Chained Block Move Instructions 4.1 LSI53C895 Functional Signal Grouping 6 ...
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... Initiator Asynchronous Receive 7.36 Target Asynchronous Send 7.37 Target Asynchronous Receive 7.38 Initiator and Target Synchronous Transfers 7.39 LSI53C895 Pin Diagram, 272-Ball BGA (Top View) 7.40 LSI53C895 Pin Diagram, 208-Pin QFP 7.41 LSI53C895 Mechanical Drawing, 208-Pin QFP 7.42 LSI53C895 Mechanical Drawing, 272 BGA B.1 16 Kbytes Interface with 200 ns Memory B ...
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Address and Data Signals 4.5 Interface Control Pins 4.6 Arbitration Signals 4.7 Error Reporting Signals 4.8 SCSI Signals, LVD Link Mode 4.9 SCSI Pins, SE Mode 4.10 SCSI Signals, High Voltage Differential Mode 4.11 Additional Signals 4.12 External Memory ...
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Output Signal—MAC/_TESTOUT 7.9 Input Signals—CLK, RST/ 7.10 Bidirectional Signals—AD[31:0], C_BE/[3:0], FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR, REQ/, IRQ/, SERR/ 7.11 Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/, GPIO2, GPIO3, GPIO4, MAD[7:0] 7.12 Bidirectional Signals—MAS/[1:0], MCE/, MOE/, MWE/ 7.13 Input Signal—BIG_LIT/ 7.14 Bidirectional ...
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... Ultra2 SCSI Transfers 40.0 Mbytes/s (8-Bit Transfers) or 80.0 Mbytes/s (16-Bit Transfers), Quadrupled 40 MHz Clock 7.51 BGA Position and Signal Name Alphabetically 7.52 BGA Position Numerically and Signal Name 7.53 Signal Name by Pin Number QFP 7.54 Alphabetical Signal Name and Pin Number QFP A.1 LSI53C895 Register Map Contents 64 Kbytes ROM 7-55 7-56 7-57 7-57 7-58 7-59 7-59 7-60 7-60 ...
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Contents ...
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... SCSI connectivity and cable length with Low Voltage Differential (LVD) signaling for SCSI. The LSI53C895 has a local memory bus for local storage of the device BIOS ROM in flash memory or standard EEPROMs. The LSI53C895 supports big and little endian byte addressing to accommodate a variety of data confi ...
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... Ultra2 SCSI. Some software enhancements, and use of LVD, enable the LSI53C895 to transfer data at Ultra2 SCSI transfer rates. Most of the feature enhancements in the LSI53C895 are included to enable the chip to take advantage of Ultra2 SCSI transfer rates. Optional 816-byte DMA FIFO supports large block transfers at Ultra2 SCSI speeds ...
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... LVD Link transceivers that can switch between LVD and SE SCSI modes. The LVD Link technology also supports high power differential signaling in legacy systems when external transceivers are connected to the LSI53C895. This allows the LSI53C895 to be used in both legacy and Ultra2 SCSI applications. Benefits of LVD Link ...
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... Ultra SCSI. When enabled, Ultra2 SCSI performs 40 megatransfers per second, which results in approximately double the synchronous transfer rates of Ultra SCSI. The LSI53C895 can perform 16 bit, Ultra2 SCSI synchronous transfers as fast as 80 Mbytes/s. This advantage is most noticeable in heavily loaded systems or large-block size applications such as video on-demand and image processing. One advantage of Ultra2 SCSI is that it signifi ...
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... On the LSI53C895, the user can select a filtering period ns, with bit 1 in the The benefits of TolerANT technology include increased immunity to noise when the signal is going HIGH, better performance due to balanced duty cycles, and improved fast SCSI transfer rates. In addition, TolerANT SCSI ...
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... I/O context switching Supports expanded register Move instructions for additional arithmetic capability 1.5.2 PCI Performance To improve PCI performance, the LSI53C895: Complies with PCI 2.1 specification Supports 32-bit 33 MHz PCI interface Bursts 16, 32, 64, or 128 Dwords across the PCI bus Supports 32-bit word data bursts with variable burst lengths ...
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... Memory to Memory Move instructions to allow use as a third-party PCI bus DMA controller High performance SCSI core Integrated SCRIPTS processor 1.5.4 Ease of Use The LSI53C895 provides ease of use by having one megabyte of add-in memory support for BIOS and SCRIPTS storage Direct PCI to SCSI connection Reduced SCSI development effort ...
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... MHz SCSI clock Selectable IRQ pin disable bit Ability to route system clock to SCSI clock 1.5.6 Reliability The LSI53C895 contains these reliability features ESD protection on SCSI signals Protection against bus reflections due to impedance mismatches Controlled bus assertion times (reduces RFI, improves reliability, and eases FCC certifi ...
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... Power and ground isolation of I/O pads and internal chip logic TolerANT technology provides: – – 1.5.7 Testability The LSI53C895 contains these testability features: All SCSI signals accessible through programmed I/O SCSI loopback diagnostics SCSI bus signal continuity checking Support for single-step mode operation Test mode (AND tree) to check pin continuity to the board LSI53C895 Benefi ...
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Introduction ...
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... Section 2.9, “Synchronous Operation,” page 2-28 Section 2.10, “Interrupt Handling,” page 2-32 Section 2.11, “Chained Block Moves,” page 2-39 Note that LSI Logic supplies software that supports the LSI53C895 and the entire LSI Logic product line of SCSI processors and controllers. LSI53C895 PCI to Ultra2 SCSI I/O Processor ...
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... SCRIPTS processor, which supports uninterrupted scatter/gather memory operations. The LSI53C895 supports 32-bit memory and automatically supports misaligned DMA transfers. A 112 or 816 byte FIFO allows the LSI53C895 to support 16, 32, 64, or 128 Dword bursts across the PCI bus interface. ...
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... Transfers Deep 8 Bits Byte Lane 3 2.2.1.1 Data Paths The data path through the LSI53C895 is dependent on whether data is being moved into or out of the chip. It also depends on whether SCSI data is being transferred asynchronously or synchronously. DMA Core Figure 2.1. To assure compatibility with older register. ...
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Figure 2.2 different modes. To determine if any bytes remain in the data path when the chip halts an operation, follow the detailed instructions in the next sections. Asynchronous SCSI Send – Follow these steps for asynchronous SCSI send operations: ...
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Counter (DBC) register from the 7-bit value of the (DFIFO) register. AND the result with 0x7F for a byte count between zero and 112. If the DMA FIFO size is set to ...
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Step 2. To determine if any bytes are left in the Step 3. To determine whether a byte is left in the Follow these steps for synchronous SCSI receive: Step 1. To calculate DMA FIFO size: Step 2. Read bits ...
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... SCSI-2 SCRIPTS Processor Control Two (SCNTL2), bit 0) LSI53C895 Host Interface Data Paths. This applies toward any wide transfers that have been performed using the Chained Move instruction. ...
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... Table Indirect information from the internal RAM, these fetches remain internal to the chip and do not use the PCI bus. Other types of access to the RAM by the LSI53C895 use the PCI bus as if they were external accesses. The MAD5 pin enables the 4 Kbytes internal RAM, when it is connected to V the internal RAM, connect a 4 ...
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... Read Multiple, and Memory Write and Invalidate commands are not used. The LSI53C895 may flush the contents of the prefetch buffer under certain conditions, listed below, to ensure that the chip always operates from the most current version of the software. When one of these conditions apply, the contents of the prefetch buffer are fl ...
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... Op Code Fetch Burst Capability Setting the Burst Op Code Fetch Enable bit in the register (0x38) causes the LSI53C895 to burst in the first two Dwords of all instruction fetches. If the instruction is a Memory to Memory move, the third Dword is accessed in a separate ownership. If the instruction is an indirect type, the additional Dword is accessed in a subsequent bus ownership ...
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... Using the SCSI Clock Quadrupler The LSI53C895 can quadruple the frequency MHz SCSI clock, allowing the system to perform Ultra2 SCSI transfers. This option is user-selectable with bit settings in the Test Three power-on or reset, the quadrupler is disabled and powered down. Follow these steps to use the clock quadrupler: Step 1 ...
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... The memory size and speed is determined by pull-up/pull- down configuration on the 8-bit bidirectional memory bus at power up. The LSI53C895 senses this bus shortly after the release of the Reset signal and configures the ROM Base Address register and the memory cycle state machines for the appropriate conditions ...
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... Kbytes external ROM, use pull-downs on MAD(3) and MAD(2) and a pull-up on MAD(1). Note: The LSI53C895 allows the system to determine the size of the available external memory using the PCI configuration space. For more information on how this works, refer to the PCI specification or the Expansion ROM Base Address register description in MAD(0) is the slow ROM pin ...
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Table 2.2 Byte 0x00 0x01 0x02 0x03 0x04 0x05–0xFF 0x100–EOM 2.6.2.2 Mode B: 4.7 K Pull-down on MAD6, and 4 this mode, GPIO0 and GPIO1 are each defined as either the SDA or the SCL, since both pins ...
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... Pull-up on MAD6, and 4.7 K This is a reserved mode and should not be used. 2.6.3 SCSI Bus Interface The LSI53C895 performs SE and LVD transfers, and supports traditional (high power) differential operation when the chip is connected to external high power differential transceivers. To support LVD SCSI, all SCSI data and control signals have a positive and a negative signal line HVD ...
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... DIF bit, bit 5 of the STEST2 register (0x4E). Setting this bit 3-states the BSY , SEL , and RST pads so they can be used as pure input pins. In addition to the standard SCSI lines, the LSI53C895 uses these signals during HVD operation as shown in Table 2.4: ...
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... These signals control the direction of the channels on the SN75976A2. The SCSI bidirectional control and data pins (SD[7:0] SDP0 , REQ , ACK , MSG , I_O , C_D , and ATN ) of the LSI53C895 connect to the bidirectional data pins (nA) of the SN75976A2 with a pull-up resistor. The pull-up value should be no lower than the transceiver I but not so high as to cause RC timing problems ...
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... LSI53C895 pins (SEL , BSY , and RST ) and the SN75976A2 data pins. Because the SEL , BSY , and RST pins on the LSI53C895 are inputs only, this configuration allows for the SEL , BSY , and RST SCSI signals to be asserted on the SCSI bus ...
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... Float SD[8:15] SDP1 SDP0+ SD7+ SD6+ SD5+ SD4+ SD3+ SD2+ SD1+ SD0+ SDP0 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 DIFFSENS LSI53C895 Interfaces DIFFSENS VDD 1.5 K 1.5 K SSEL SSEL+ SBSY VDD SBSY+ SRST SRST+ 1.5 K REQ/ SACK SMSG VDD SCD 1.5 K SIO SATN 1.5 K DIFFSENS VDD 1 ...
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... The BIG_LIT pin gives the LSI53C895 the flexibility of operating with either big or little endian byte orientation. Internally, in either mode, the actual byte lanes of the DMA FIFO and registers are not modified. The LSI53C895 supports slave accesses in big or little endian mode ...
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... Big and little endian mode selection has the most effect on individual byte access. Internally, the LSI53C895 adjusts the byte control logic of the DMA FIFO and register decodes to enable the appropriate byte lane. The registers always appear on the same byte lane, but the address of the register is repositioned ...
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... When the Loopback Enable bit is set in the LSI53C895 allows control of all SCSI signals, whether the LSI53C895 is operating in initiator or target mode. For more information on this mode of operation, refer to the SCSI SCRIPTS Processors Programming Guide ...
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... Data Latch (SIDL) Enables parity checking during master data phases. Set when the LSI53C895 as a master detects that a target device has signaled a parity error during a data phase. By clearing this bit, a Master Data Parity Error does ...
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... For information on terminators that support LVD, refer to the SPI-2 draft standard. Note: 2-24 Functional Description SCSI Control One (SIEN0)). pull-up to the terminator power supply pull-down to ground. Due to the Figure 2.4 shows a Unitrode active When using the LSI53C895 in a design with an 8-bit SCSI bus, all 16 data lines still must be terminated or pulled HIGH. (SCNTL1)). ...
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... Use additional UCC6350 terminators to connect signals and additional wide SCSI data bytes as needed. 2.8.2 System Engineering Note In the LSI53C895, transmission mode detection for SE, HVD, and LVD is implemented by using the DIFFSENS line. corresponding voltages and what mode they indicate. Table 2.8 ...
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At power-up: Step 1. Set bit 3 in Step 2. Enable the SCSI Bus Mode Change (SBMC) interrupt by Step SCSI bus mode change is detected, then Step 4. Clear the interrupt by reading Step 5. Wait ...
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... SE SCSI bus because the SBMC interrupt is generated after each reset. In particular, this problem occurs with NetWare when control is passed between the NetWare and DOS drivers. After a soft reset, the LSI53C895 defaults to LVD mode devices are on the bus and pull the DIFFSENS line low, a SBMC interrupt is generated and requires a response from the driver ...
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... Set Initiator instruction or the target SCRIPTS should start with a Set Target instruction. The Selection and Reselection Enable bits (SCSI Chip ID (SCID) so that the LSI53C895 may respond as an initiator target. If only selection is enabled, the LSI53C895 cannot be reselected as an initiator. There are also status and interrupt bits in the (SIST0) whether the LSI53C895 has been selected (bit 5) and reselected (bit 4) ...
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... Ultra SCSI. This allows a maximum transfer rate of 80 Mbytes 16-bit, LVD SCSI bus. The LSI53C895 has a SCSI clock quadrupler that must be enabled for the chip to perform Ultra2 SCSI transfers with a 40 MHz oscillator. In addition, the following bit values affect the chip’ ...
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... Ultra2 SCSI Enable bit, Setting this bit enables Ultra2 SCSI synchronous transfers in systems that use the internal SCSI clock quadrupler. TolerANT Enable bit, Active negation must be enabled for the LSI53C895 to perform Ultra2 SCSI transfers. Note: 2-30 Functional Description SCSI Contr0l Three (SCNTL3) register bits [6:4]. These fi ...
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Figure 2.5 Determining the Synchronous Transfer Rate SCF2 SCF1 SCF0 Clock SCLK QCLK Quadrupler CCF2 CCF1 ...
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... A hybrid approach would use hardware interrupts for long waits, and use polling for short waits. 2.10.2 Registers The registers in the LSI53C895 that are used for detecting or defining interrupts are: Interrupt Status (ISTAT) SCSI Interrupt Status Zero (SIST0) ...
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... SCSI-type interrupt, and clears that SCSI interrupt condition. If the LSI53C895 is receiving data from the SCSI bus and a fatal interrupt condition occurs, the LSI53C895 attempts to send the contents of the DMA FIFO to memory before generating the interrupt. ...
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DFE bit in generate an interrupt under any circumstances and is not cleared when read. DMA interrupts flushes neither the DMA nor SCSI FIFOs before generating the interrupt, so the DFE bit in the register should be checked after any ...
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... CPU. SCRIPTS do not stop when: Arbitration is complete (CMP set). The LSI53C895 has been selected or reselected (SEL or RSL set). The initiator has asserted ATN (target mode: SATN/ active). The General Purpose or Handshake-to-Handshake timers expire. ...
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... IRQ/ pin. Masking an interrupt after IRQ/ is asserted does not deassert IRQ/. 2.10.5 Stacked Interrupts The LSI53C895 stacks interrupts if they occur one after the other. If the SIP or DIP bits in the then at least one pending interrupt already exists, and any future ...
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... These locked out SCSI interrupts are posted as soon as the DMA FIFO is empty. 2.10.6 Halting in an Orderly Fashion When an interrupt occurs, the LSI53C895 attempts to halt in an orderly fashion as explained below. If the interrupt occurs in the middle of an instruction fetch, the fetch is completed, except in the case of a Bus Fault. Execution does not begin, but the DSP points to the next instruction since it is updated when the current instruction is fetched ...
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... SCRIPTS Pointer (DSP) is updated to the transfer address before halting. All other instructions may halt before completion. 2.10.7 Sample Interrupt Service Routine A sample of an interrupt service routine for the LSI53C895 is shown below. This routine can be repeated if polling is used, or should be called when the IRQ/ pin is asserted if using hardware interrupts. 1. Read 2 ...
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... This re-enters the system into the interrupt service routine. 2.11 Chained Block Moves Since the LSI53C895 has the capability to transfer 16-bit wide SCSI data, a unique situation occurs when dealing with odd bytes. The Chained Move (CHMOV) SCRIPTS instruction along with the Wide SCSI ...
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Figure 2 Notes: CHMOV 5, 3 when DATA_OUT: Moves five bytes from address 03 in the host MOVE 5, 9 when DATA_OUT: 2.11.1 Wide SCSI Send Bit (WSS) The WSS bit is set whenever the ...
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Block Move instruction (normal or chained). The flag is automatically cleared when the ...
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Chained Block Move SCRIPTS Instruction A chained Block Move SCRIPTS instruction transfers consecutive data send or data receive blocks. Using the chained block move instruction facilitates partial receive transfers and allows correct partial send behavior without additional op code ...
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Regardless of whether a chained Block Move or normal Block Move instruction is used, if the WSS bit is set at the start of a data send command, the first byte of the data send command is assumed to be ...
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Functional Description ...
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... AD[10:8] are to be used for multifunction devices. The host processor uses the PCI configuration space to initialize the LSI53C895. The lower 128 bytes of the LSI53C895 configuration space holds system parameters while the upper 128 bytes map into the LSI53C895 operating LSI53C895 PCI to Ultra2 SCSI I/O Processor 3-1 ...
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... LSI53C895 compares its assigned base addresses with the value on the Address/Data bus during the PCI address phase. If there is a match of the upper 24 bits, the access is for the LSI53C895 and the low order eight bits define the register to be accessed. A decode of C_BE/ [3:0] determines which registers and what type of access performed. PCI defi ...
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The Memory Write and Memory Write and Invalidate commands write data to an agent when mapped in memory address space. All 32 address bits are decoded. Table 3.1 PCI Bus Commands Supported C_BE[3:0] Command Type 0b0000 Special Interrupt Acknowledge 0b0001 ...
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... Note: 3.3.3 Alignment The LSI53C895 uses the calculated line size value to monitor the current address for alignment to the cache line size. When it is not aligned, the chip attempts to align to the cache boundary by using a “smart aligning” scheme. This means that it attempts to use the largest burst size ...
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... So, the LSI53C895 issues a burst this point, the address is 0x20, and the chip evaluates that it is aligned not only to a 4-Dword boundary, but also to an 8-Dword boundary ...
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... The chip must have enough bytes in the DMA FIFO to complete at least one full cache line burst. 4. The chip must be aligned to a cache line boundary. When these conditions have been met, the LSI53C895 issues a Memory Write and Invalidate command instead of a Memory Write command during all PCI write cycles. ...
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... PCI Target Disconnect During a Write and Invalidate transfer, if the target device issues a disconnect the LSI53C895 relinquishes the bus and immediately tries to finish the transfer on another bus ownership. The chip does not issue another Write and Invalidate command on the next ownership unless the address is aligned ...
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... Memory Read Multiple Command This command is identical to the Memory Read command except that it additionally indicates that the master may intend to fetch more than one cache line before disconnecting. The LSI53C895 supports PCI Read Multiple functionality and issues Memory Read Multiple commands on 3-8 ...
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PCI bus when the Read Multiple Mode is enabled. This mode is enabled by setting bit 2 of the cache mode has been enabled, a Memory Read Multiple command is issued on all read cycles, except op code fetches, ...
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... Unsupported PCI Commands The LSI53C895 does not respond to reserved commands, special cycle, dual address cycle, or interrupt acknowledge commands as a slave. It never generates these commands as a master. 3.4 Configuration Registers The Configuration registers are accessible only by the system BIOS during PCI configuration cycles, and are not available to the user at any time. No other cycles, including SCRIPTS operations, can access these registers. The lower 128 bytes hold confi ...
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... Chapter 4 Signal Descriptions This chapter presents the LSI53C895 pin configurations and signal definitions by using tables and illustrations. signal grouping for the LSI53C895. The pin definitions are in through Table 4.12. These definitions are organized into the following functional groups: System, Address/Data, Interface Control, Arbitration, Error Reporting, SCSI, and Optional Interface ...
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... Figure 4.1 LSI53C895 Functional Signal Grouping CLK System RST/ AD[31:0] Address C_BE/[3:0] and Data PAR FRAME/ TRDY/ Interface Control IRDY/ STOP/ DEVSEL/ IDSEL REQ/ Arbitration GNT/ Error SERR/ Reporting PERR/ 4-2 Signal Descriptions SBSY SRST SSEL SREQ SACK SATN/ SMSG SCLK SD[15:0/] SDP[1:0] SCD SIO ...
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... T/S 4. S/T/S 4.1 Voltage Capabilities and Limitations The LSI53C895 uses 5 V biasing pins to allow the device to handle input voltage to the PCI and external memory interface pins. When the LSI53C895 is used PCI system, the biasing pins (V5BIAS(P)) must be supplied with 5 V. When they are used only PCI environment, these biasing pins must be supplied with 3 ...
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... Internal Pull-ups on LSI53C895 Pins Several pins on the LSI53C895 use internal pull-ups. the conditions under which these pull-ups are enabled or disabled. Table 4.1 LSI53C895 Internal Pull-ups Pin Name PCI pins except IRQ, CLK and RST IRQ RST, CLK MAD [7:0] MAS/[1:0], MCE/, MOE/, MWE/ ...
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... Pin Descriptions Table 4.2 Table 4.2 LSI53C895 Power and Ground Signals Pin No. 1 Name Ball No 13, 23, 26, 36, 46, DD- 2 60, 197 (Pins) PCI 18, 31, 41, 56, 193, SS-PCI 200 (Pins) V 86, 96, 115, 125, 134, DD- 2 144, 164, 174 (Pins) SCSI V 91, 110, 120, 128, 131, ...
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... M11 , J12 , K12 , L12 , M12 , D13, U13, D17, H17, N17, U17 1. All V pins must be supplied 3.3 V. The LSI53C895 output signals drive 3 the BGA option, V DD-SCSI V are connected together at package. SS-IO 3. Optional ground pins. Note: Table 4.3 Table 4.3 System Signals Pin No. ...
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Table 4.4 Table 4.4 Address and Data Signals Pin No. Name Ball No. AD[31:0] 199, 201–204 10–12, 14–17, 19, 33–35, 37–40, 42, 44, 45, 47, 48, 50, 51, 57, 58 U2, V1, V2, W1, V3, Y3, V5, ...
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Table 4.5 Table 4.5 Interface Control Pins Pin No. Name Ball No. Type FRAME/ 21 S/T/S V9 TRDY/ 24 S/T/S W10 IRDY/ 22 S/T/S W9 STOP/ 27 S/T/S W11 DEVSEL/ 25 S/T/S Y10 IDSEL 4-8 Signal Descriptions ...
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Table 4.6 Table 4.6 Arbitration Signals Pin No. Name Ball No. Type REQ/ 198 O U1 GNT/ 196 I T2 Table 4.7 Table 4.7 Error Reporting Signals Pin No. Name Ball No. Type PERR/ 28 S/T/S V11 SERR ...
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Table 4.8 Table 4.8 SCSI Signals, LVD Link Mode Pin No. Name Ball No. SCLK 80 J20 SD [15:0], 167, 170, 172, 175, 87, SDP [1:0] 89, 92, 94, 135, 137, 140, 142, 145, 147, 149, 162, 165, 132 F2, ...
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Table 4.8 SCSI Signals, LVD Link Mode (Cont.) Pin No. Name Ball No. SCTRL+ 112, 98, 117, 100, 122, 124, 127, 119, 114 D16, E17, A16, C19, A14, A13, A12, A15, A17 RBIAS+, 130, 129 RBIAS A10, A11 DIFFSENS 84 ...
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Table 4.9 Table 4.9 SCSI Pins, SE Mode Pin No. Name Ball No. SCLK 80 J20 SD [15:0], 167, 170, 172, 175, 87, SDP [1:0] 89, 92, 94, 135, 137, 140, 142, 145, 147, 149, 162, 165, 132 F2, G2, ...
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Table 4.9 SCSI Pins, SE Mode (Cont.) Pin No. Name Ball No. SCTRL+ 112, 98, 117, 100, 122, 124, 127, 119, 114 D16, E17, A16, C19, A14, A13, A12, A15, A17 DIFFSENS 84 H20 Table 4.10 Table 4.10 SCSI Signals, ...
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Table 4.10 SCSI Signals, High Voltage Differential Mode (Cont.) Pin No. Name Ball No. SD+[15:0] 168, 171, 173, 176, 88, SDP+[1:0] 90, 93, 95, 136, 138, 141, 143, 146, 148, 150, 163, 166, 133 F1, G1, H1, J2, G19, F19, ...
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... LOW, internal pull-ups are enabled on all input, output, and bidirectional pins, all outputs and bidirectional signals are 3-stated, and the MAC/_TESTOUT pin is enabled. Connectivity can be tested by driving one of the LSI53C895 pins LOW. The MAC/_TESTOUT pin should respond by also driving LOW. I/O General Purpose I/O pin ...
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... PCI byte lane zero onto the SCSI bus first, and transfers ascending byte lanes in order. When this pin is driven HIGH, the LSI53C895 routes the first byte of an aligned SCSI to PCI transfer to byte lane three of the PCI bus and subsequent bytes received are routed to descending lanes. An aligned PCI to SCSI transfer routes PCI byte lane three onto the SCSI bus fi ...
Page 97
... Memory Address Strobe 0. This pin latches in the least significant address byte of an external EEPROM or flash memory. Since the LSI53C895 moves addresses eight bits at a time, this pin connects to the clock of an external bank of flip-flops that assemble 20-bit address for the external memory. ...
Page 98
... The MAD4 pin is reserved and should be pulled up. It may be used by LSI Logic in future devices. The MAD[3:1] pins set the size of the external parallel ROM device attached to the LSI53C895. Encoding for these pins is listed below (0 indicates a pull-down resistor is attached, 1 indicates a pull-up resistor is attached). ...
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... Registers This chapter contains descriptions of the PCI registers and the LSI53C895 operating registers. The terms “set” and “assert” refer to bits that are programmed to a binary one. Similarly, the terms “deassert,” “clear,” and “reset” refer to bits that are programmed to a binary zero. ...
Page 100
Table 5.1 PCI Configuration Register Map 31 Device ID Status Class Code Not Supported Header Type Subsystem ID Max_Lat Min_Gnt 1. I/O Base is supported. 2. Memory Base is supported. 3. This register powers up enabled and can be disabled ...
Page 101
... The SCSI Command register provides coarse control over a device’s ability to generate and respond to PCI cycles. When a zero is written to this register, the LSI53C895 is logically disconnected from the PCI bus for all accesses except configuration accesses. PCI Configuration Registers VID[15:0] ...
Page 102
... Memory Write and Invalidate commands. Reserved Enable Bus Mastering This bit controls the ability of the LSI53C895 to act as a master on the PCI bus. A value of zero disables this device from generating PCI bus master accesses. A value of one allows the LSI53C895 to behave as a bus master ...
Page 103
... DPE Detected Parity Error (from Slave) This bit is set by the LSI53C895 whenever it detects a data parity error, even if data parity error handling is disabled. SSE Signaled System Error This bit is set whenever the device asserts the SERR/ signal ...
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... These bits are read-only and should indicate the slowest time that a device asserts DEVSEL/ for any bus command except Configuration Read and Configuration Write. The LSI53C895 supports a value of 0b01. Data Parity Error Reported This bit is set when the following conditions are met: The bus agent asserted PERR/ itself or observed PERR/ asserted ...
Page 105
... Cache Line Size Enable (CLSE) bit, bit 7 in the Control (DCNTL) register. Setting this bit causes the LSI53C895 to align to cache line boundaries before allowing any bursting, except during memory moves in which the read and write addresses are not aligned to a burst size boundary. For more information on this register, see Section 3.3.1, “ ...
Page 106
... PCI bus clocks, the value of the Latency Timer for this PCI bus master. The SCSI functions of the LSI53C895 support this timer. All eight bits are writable, allowing latency values of 0–255 PCI clocks. Use the following equation to calculate an optimum latency value for the SCSI functions of the LSI53C895 ...
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Register: 0x10–0x13 Base Address Register Zero (I/O) Read/Write BARZ[31:0] Register: 0x14–0x17 Base Address One (Memory) Read/Write BARO[31:0] PCI ...
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Register: 0x18–0x1B RAM Base Address Read/Write RAMBA[31:0] RAM Base Address Register: 0x1C–0x1F Not Supported Register: 0x20–0x23 Not Supported Register: 0x24–0x27 Not Supported Register: 0x28–0x31 Reserved Register: 0x2C–0x2D Subsystem Vendor ...
Page 109
... SID[15:0] Subsystem ID This 16-bit register uniquely identifies the add-in board or subsystem where the LSI53C895 resides. It provides a mechanism for an add-in card vendor to distinguish between its cards that use the same PCI controller installed on them (and therefore the same Vendor ID and Device ID). ...
Page 110
... Expansion ROM Base Address with all ones and then reading back the register. The SCSI functions of the LSI53C895 respond with zeros in all don’t care locations. The ones in the remaining bits represent the binary version of the external memory size. ...
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Register: 0x34–0x3B Reserved Register: 0x3C Interrupt Line Read/Write IL[7:0] Interrupt Line This register communicates interrupt line routing information. POST software writes the routing information into this register as it configures the system. The value in this ...
Page 112
... Min_Gnt This register specifies the desired settings for latency timer values. Min_Gnt specifies how long a burst period the device needs. The value specified in these registers is in units of 0.25 microseconds. The LSI53C895 sets this register to 0x11. ML[7: Max_Lat This register specifi ...
Page 113
... However, all operating registers are accessible with SCRIPTS. All read data is synchronized and stable when presented to the PCI bus. The LSI53C895 cannot fetch SCRIPTS instructions from the operating register space. Instructions must be fetched from system memory or the internal SCRIPTS RAM. Interrupt Status ...
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Table 5.2 SCSI Register Map SCNTL3 SCNTL2 GPREG SDID SBCL SSID SSTAT2 SSTAT1 RESERVED CTEST3 CTEST2 CTEST6 CTEST5 DCMD DCNTL SBR SIST1 SIST0 GPCNTL MACNTL RPID1 RPID0 STEST3 STEST2 RESERVED STEST4 RESERVED RESERVED 5-16 Registers SCNTL1 SXFER SOCL SSTAT0 DSA ...
Page 115
... ARB0 Simple Arbitration 1. The LSI53C895 waits for a bus free condition to occur asserts SBSY/ and its SCSI ID (contained in the SCSI Chip ID (SCID) the SSEL/ signal is asserted by another SCSI device, the LSI53C895 deasserts SBSY/, deasserts its ID and sets the Lost Arbitration bit (bit 3) in the SCSI Status Zero (SSTAT0) 3 ...
Page 116
... LSI53C895 is already connected to the SCSI bus. This bit is automatically cleared when the arbitration sequence is complete sequence is aborted, bit 4 in the SCSI Control One (SCNTL1) checked to verify that the LSI53C895 did not connect to the SCSI bus. register) onto SCSI Status Zero register), ...
Page 117
... The SATN/ signal is asserted before deasserting SACK/ during the byte transfer with the parity error. The Enable Parity Checking bit must also be set for the LSI53C895 to assert SATN/ in this manner. A parity error is detected on data received from the SCSI bus. ...
Page 118
... When the LSI53C895 is an initiator, the SCSI I/O signal must be inactive to assert the Data Latch (SODL) contents onto the SCSI bus. When the LSI53C895 is a target, the SCSI I/O signal must be active for the SCSI Output Data Latch (SODL asserted onto the SCSI bus. The contents of the ...
Page 119
... LSI53C895 transfers data until there are no outstanding synchronous offsets. If the LSI53C895 is receiving data, any data residing in the DMA FIFO is sent to memory before halting. When this bit is set, the LSI53C895 does not halt the SCSI transfer when SATN parity error is received. CON Connected This bit is automatically set any time the LSI53C895 is connected to the SCSI bus as an initiator target ...
Page 120
... Status Zero bit 2) is set. In this case, the Immediate Arbitration bit needs to be reset. This completes the abort sequence and disconnects the LSI53C895 from the SCSI bus not acceptable Bus Free phase immediately following the arbitration phase, a low-level selection may be performed instead. ...
Page 121
SCSI Output Control Latch (SOCL) This bit is self-clearing. It should not be set for low-level operation. Caution: Writing to this register while not connected may cause the loss of a selection/reselection by clearing the Connected bit. ...
Page 122
... SLPMD SLPHBEN WSS VUE0 5-24 Registers boundary, the LSI53C895 stores the last byte in the Wide Residue (SWIDE) register during a receive operation the SCSI Output Data Latch (SODL) register during a send operation. This byte is combined with the first byte from the subsequent transfer so that a wide transfer can be completed ...
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... Ultra Enable Setting this bit enables Ultra SCSI or Ultra2 SCSI synchronous transfer rates. The default value of this bit is 0. This bit should remain cleared if the LSI53C895 is not operating in Ultra SCSI mode or faster. Set this bit to achieve Ultra SCSI transfer rates in legacy systems that use an 80 MHz clock ...
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SCF[2:0] EWS 5-26 Registers When this bit is set, the signal filtering period for SREQ/ and SACK/ automatically changes for Ultra2 SCSI for Ultra SCSI, regardless of the value of the Extend REQ/ACK Filtering ...
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SD[7:0]/, SDP/ and the most significant byte on SD[15:8]/, SDP1/. Command, Status, and Message phases are not affected by this bit. Clearing this bit also clears the ...
Page 126
... Response ID One (RESPID1) registers. Note that the LSI53C895 does not automatically reconfigure itself to initiator mode as a result of being reselected. Enable Response to Selection When this bit is set, the LSI53C895 is able to respond to bus-initiated selection at the chip ID in the Zero (RESPID0) and Response ID One (RESPID1) registers. Note that the LSI53C895 does not automatically reconfi ...
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... TP[2:0] SCSI Synchronous Transfer Period These bits determine the SCSI synchronous transfer period (XFERP) used by the LSI53C895 when sending synchronous SCSI data in either initiator or target mode. These bits control the programmable dividers in the chip. For Ultra SCSI transfers, the ideal transfer period is 4, and 5 is acceptable ...
Page 128
Table 5.5 Examples of Synchronous Transfer Periods and Rates for SCSI-1 SCF (SCNTL3 SCLK (MHz) Bits [6:4 66.67 3 66. 37.50 1.5 33.33 1 16.67 ...
Page 129
... SCSI data in either initiator or target mode. Table 5.7 describes the possible combinations and their relationship to the synchronous data offset used by the LSI53C895. These bits determine the LSI53C895 method of transfer for Data In and Data Out phases only; all other information transfers occur asynchronously. Sync ...
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Registers Table 5.7 Maximum Synchronous Offset MO4 MO3 MO2 MO1 ...
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Register: 0x06 SCSI Destination ID (SDID) Read/Write Reserved ENC Encoded SCSI Destination ID Writing these bits sets the SCSI ID of the intended initiator or target during SCSI reselection or selection phases. When executing ...
Page 132
... Memory Move. The Load instruction may not be used to write to this register. However, it can be loaded by using SCRIPTS Read/Write operations. To load the SFBR with a byte stored in system memory, the byte must first be moved to an intermediate LSI53C895 register (such as the SCRATCH register), and then to the SFBR. 5-34 ...
Page 133
... The SCRIPTS processor controls this register when executing SCSI SCRIPTS. SOCL should only be used when transferring data through programmed I/O. Some bits are set (1) or reset (0) when executing SCSI SCRIPTS. Do not write to the register once the LSI53C895 starts executing normal SCSI SCRIPTS. SCSI Registers 4 3 ...
Page 134
... Reserved Encoded SCSI Destination ID Reading the SCSI Selector ID (SSID) immediately after the LSI53C895 has been selected or reselected returns the binary-encoded SCSI ID of the device that performed the operation. These bits are invalid for targets that are selected under the single initiator option of the SCSI-1 specification. This condition can be detected by examining the VAL bit above ...
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Register: 0x0B SCSI Bus Control Lines (SBCL) Read Only REQ ACK BSY REQ SREQ/ Status ACK SACK/ Status BSY SBSY/ Status SEL SSEL/ Status ATN SATN/ Status MSG SMSG/ Status C/D SC_D/ Status I/O ...
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... Chip Test Four this MDPE, bit 6. Bus Fault This bit is set when a PCI bus fault condition is detected. A PCI bus fault can only occur when the LSI53C895 is bus master, and is defined as a cycle that ends with a Bad address or Target Abort Condition. Aborted This bit is set when an abort condition occurs ...
Page 137
... Reserved IID Illegal Instruction Detected This status bit is set any time an illegal or Reserved instruction op code is detected, whether the LSI53C895 is operating in single-step mode or automatically executing SCSI SCRIPTS. Any of the following conditions during instruction execution also sets this bit: The LSI53C895 is executing a Wait Disconnect instruction and the SCSI REQ line is asserted without a disconnect occurring ...
Page 138
Register: 0x0D SCSI Status Zero (SSTAT0) Read Only 7 ILF 0 ILF ORF 5-40 Registers A Load/Store instruction is issued when the register address is not aligned with the memory address. A Load/Store instruction is issued with bit 5 in ...
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... SCSI device asserting the SEL/ signal. WOA Won Arbitration When set, WOA indicates that the LSI53C895 has detected a Bus Free condition, arbitrated for the SCSI bus and won arbitration. The arbitration mode selected in the SCSI Control Zero (SCNTL0) arbitration and selection for this bit to be set ...
Page 140
... Flags) These four bits, along with bit 4, define the number of bytes or words that currently reside in the LSI53C895 SCSI synchronous data FIFO. These bits are not latched, and they change as data moves through the FIFO. FF4 (SSTAT2 bit 4) FF3 ...
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FF4 (SSTAT2 bit SDP0L Latched SCSI Parity This bit reflects the SCSI parity signal (SDP0/), corresponding to the data latched ...
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MSG C/D I/O Register: 0x0F SCSI Status Two (SSTAT2) Read Only 7 ILF1 0 LF1 ORF1 OLF1 5-44 Registers SCSI MSG/ Signal SCSI C_D/ Signal SCSI I_O/ Signal These SCSI phase status bits are latched on the asserting edge of ...
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... DM DIFFSENS Mismatch This bit is set when the DIFFSENS pin detects LVD SCSI operating voltage level while the LSI53C895 is operating in high-power differential mode (by setting the DIF bit in the bit is reset, the DIFFSENS value matches the DIF bit setting. ...
Page 144
... This is the only register that can be accessed by the host CPU while the LSI53C895 is executing SCRIPTS (without interfering in the operation of the LSI53C895). It may be used to poll for interrupts if hardware interrupts are disabled. If there are stacked interrupts pending, read this register after servicing an interrupt to check for stacked interrupts. For more information on interrupt handling refer to Description.” ...
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... SRST Software Reset Setting this bit resets the LSI53C895. All operating registers are cleared to their respective default values and all SCSI signals are deasserted. Setting this bit does not cause the SCSI RST/ signal to be asserted. This reset does not clear the LSI53C700 family ID Mode bit or any of the PCI confi ...
Page 146
... LSI53C895 has responded to a bus-initiated selection or reselection also set after the LSI53C895 wins arbitration when operating in low-level mode. When this bit is clear, the LSI53C895 is not connected to the SCSI bus. Interrupt on the Fly This bit is asserted by an INTFLY instruction during SCRIPTS execution ...
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... SCSI Interrupt Status One (SIST1) DIP DMA Interrupt Pending This status bit is set when an interrupt condition is detected in the DMA portion of the LSI53C895. A DMA interrupt can occur under these conditions: A PCI parity error is detected A bus fault is detected An abort condition is detected A SCRIPTS instruction is executed in single-step ...
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Register: 0x18 Chip Test Zero (CTEST0) Read/Write 7 x CTEST0 Register: 0x19 Chip Test One (CTEST1) Read Only 7 FMT3 1 FMT[3:0] FFL[3:0] 5-50 Registers CTEST0 Chip Test Zero This was a general purpose read/write register in ...
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Register: 0x1A Chip Test Two (CTEST2) Read/Write DDIR SIGP CIO DDIR Data Transfer Direction (Read only) This status bit indicates which direction data is being transferred. When this bit is set, the data is ...
Page 150
... This bit indicates the status of the LSI53C895 internal TEOP signal. The TEOP signal acknowledges the completion of a transfer through the SCSI portion of the LSI53C895. When this bit is set, TEOP is active. When this bit is clear, TEOP is inactive. Data Request Status (Read only) This bit indicates the status of the LSI53C895 internal Data Request signal (DREQ) ...
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... TEMP SCSI Registers is not self clearing; once the LSI53C895 has successfully transferred the data, this bit should be reset. Polling of FIFO flags is allowed during flush operations. Clear DMA FIFO When this bit is set, all data pointers for the DMA FIFO are cleared. Any data in the FIFO is lost. This bit ...
Page 152
... Register: 0x20 (A0) DMA FIFO (DFIFO) Read Only 7 x BO[7:0] 5-54 Registers executed. Do not write to this register while the LSI53C895 is executing SCRIPTS. During any Memory to Memory Move operation, the contents of this register are preserved. The power-up value of this register is indeterminate. BO[7: Byte Offset Counter ...
Page 153
... Setting this bit causes the LSI53C895 to place all output and bidirectional pins into a high impedance state. In order to read data out of the LSI53C895, this bit must be cleared. This bit is intended for board-level testing only. Do not set this bit during normal system operation. ...
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... Master Parity Error Enable Setting this bit enables parity checking during master data phases. A parity error during a bus master read is detected by the LSI53C895. A parity error during a bus master write is detected by the target, and the LSI53C895 is informed of the error by the PERR/ pin being asserted by the target ...
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Register: 0x22 Chip Test Five (CTEST5) Read/Write ADCK BBCK DFS ADCK Clock Address Incrementor Setting this bit increments the address pointer contained in the DMA Next Address (DNAD) Next Address (DNAD) the DNAD contents ...
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BL2 BO[9:8] Register: 0x23 Chip Test Six (CTEST6) Read/Write 7 0 DF[7:0] 5-58 Registers the SCSI bus to the host bus. Deasserting the DMAWR signal transfers data from the host bus to the SCSI bus. Burst Length Bit 2 This ...
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... Counter (DBC) register is 0xFFFFFF. If the instruction is a Block Move and a value of 0x000000 is loaded into the DMA Byte Counter (DBC) interrupt occurs if the LSI53C895 is not in target mode, Command phase. Use the DMA Byte Counter (DBC) the least significant 24 bits of the first Dword of a SCRIPT fetch, and to hold the offset value during table indirect I/O SCRIPTS ...
Page 158
... DNAD 5-60 Registers DCMD DMA Command This 8-bit register determines the instruction for the LSI53C895 to execute. This register has a different format for each instruction. For complete descriptions, refer to Section 6.4, “I/O Instruction.” DNAD DMA Next Address This 32-bit register contains the general purpose address pointer ...
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Register: 0x2C–0x2F DMA SCRIPTS Pointer (DSP) Read/Write DSP Register: 0x30–0x33 DMA SCRIPTS Pointer Save (DSPS) Read/Write DSPS SCSI ...
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... DMA FIFO can accommodate a transfer of at least one burst size of data. Bus Request (REQ/) is also asserted during start-of-transfer and end-of-transfer cleanup and alignment, even though less than a full burst of transfers may be performed. The LSI53C895 inserts a “fairness delay” of four CLKs between burst-length x x ...
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... Command. If this bit is set, then the destination address is in I/O space. If reset, then the destination address is in memory space. This function is useful for memory to register operations using the Memory Move instruction when the LSI53C895 is I/O mapped. Bits 4 and 5 of the (CTEST2) register can be used to determine the confi ...
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... These conditions are described in Addressing.” Burst Op Code Fetch Enable Setting this bit causes the LSI53C895 to fetch instructions in burst mode. Specifically, the chip bursts in the first two Dwords of all instructions using a single bus ownership. If the instruction is a Memory to Memory Move type, the third Dword is accessed in a subsequent bus ownership ...
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... Interrupt Status (ISTAT) The LSI53C895 IRQ/ output is latched; once asserted, it remains asserted until the interrupt is cleared by reading the appropriate status register. Masking an interrupt after the IRQ/ output is asserted does not cause IRQ deasserted ...
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... SSM IRQM Cache Line Size Enable Setting this bit enables the LSI53C895 to sense and react to cache line boundaries set up by the (DMODE) or PCI Cache Line Size contains the smaller value. Clearing this bit disables the cache line size logic and the LSI53C895 monitors the cache line size by using the register ...
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... For normal SCSI SCRIPTS operation, this bit should be clear. To restart the LSI53C895 after it generates a SCRIPTS Step interrupt, the (ISTAT) and read to recognize and clear the interrupt and then the START DMA bit in this register should be set ...
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... For more information on interrupts, refer to Description.” 5-68 Registers LSI53C700 Family Compatibility When this bit is clear, the LSI53C895 behaves in a manner compatible with the LSI53C700 family in that selection/reselection IDs are stored in both the Selector ID (SSID) and registers. When this bit is set, the ID is stored only in the ...
Page 167
... LSI53C895 has been selected by a SCSI target device. RSL Reselected Setting this bit allows the LSI53C895 to generate an interrupt when the LSI53C895 has been reselected by a SCSI initiator device. SGE SCSI Gross Error Setting this bit allows the LSI53C895 to generate an interrupt when a SCSI Gross Error occurs ...
Page 168
... SRST/ pulse. SCSI Parity Error Setting this bit allows the LSI53C895 to generate an interrupt when the LSI53C895 detects a parity error while receiving or sending SCSI data. See the Disable Halt on Parity Error or SATN/ Condition bits in the ...
Page 169
... Timer One (STIME1) more information on the general purpose timer. HTH Handshake to Handshake Timer Expired Setting this bit allows the LSI53C895 to generate an interrupt when the handshake to handshake timer has expired. The time measured is the SCSI Request to Request (target) or Acknowledge to Acknowledge (initiator) period. See the description of the Zero (STIME0) the handshake to handshake timer ...
Page 170
... Reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register because additional interrupts may be pending (the LSI53C895 stacks interrupts). SCSI interrupt conditions may be individually masked through the Interrupt Enable Zero (SIEN0) ...
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... SEL Selected This bit is set when the LSI53C895 is selected by another SCSI device. The Enable Response to Selection bit must have been set in the the Response ID (RESPID) register must hold the chip ID) for the LSI53C895 to respond to selection attempts. RSL Reselected This bit is set when the LSI53C895 is reselected by another SCSI device ...
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... This bit is set when the LSI53C895 detects a parity error while receiving SCSI data. The Enable Parity Checking bit (bit 3 in the SCSI Control Zero (SCNTL0) must be set for this bit to become active. The LSI53C895 always generates parity when sending SCSI data ...
Page 173
... SCSI bus has switched between SE, LVD, or HVD modes. R Reserved STO Selection or Reselection Timeout The SCSI device which the LSI53C895 was attempting to select or reselect did not respond within the programmed timeout period. See the description of the Zero (STIME0) information on the timeout timer. GEN ...
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Data Bytes – 1. 11001100 2. 01010101 3. 00001111 4. 10010110 5-76 Registers any given time. When bit 5 in the (SCNTL2) (SLPMD) register is cleared, the chip XORs the high and low bytes of the (SLPAR) register together to ...
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This byte must then be sent across the SCSI bus. Note: Writing any value to this register resets it to zero. The longitudinal parity checks are ...
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DWR DRD PSCPT SCPTS Register: 0x47 General Purpose Pin Control (GPCNTL) Read/Write This register determines if the pins controlled by the (GPREG) to bits [4:0] in the ME 5-78 Registers Bits 3 through 0 of this register ...
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FE Fetch Enable The internal op code fetch signal will be presented on GPIO0 if this bit is set, regardless of the state of Bit 0 (GPIO0_EN). R Reserved GPIO_EN GPIO Enable General purpose control, corresponding to bits [4:2] in ...
Page 178
SEL[3:0] 5-80 Registers Table 5.8 Timeout Periods HTH[7:4], SEL[3:0], GEN[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1. These values are correct if the CCF bits in the Contr0l Three (SCNTL3) ...
Page 179
Register: 0x49 SCSI Timer One (STIME1) Read/Write HTHBA GENSF Reserved HTHBA Handshake to Handshake Timer Bus Activity Enable Setting this bit causes this timer to begin testing for SCSI REQ/ACK activity as ...
Page 180
Registers Table 5.9 Timeout Periods, 50 MHz Clock (Cont.) HTH[7:4], SEL[3:0], GEN[3:0] GENSF = 0 1101 409.6 ms 1110 819.2 ms 1111 1 These values are correct if the CCF bits in the Contr0l Three (SCNTL3) register ...
Page 181
HTHSF Handshake to Handshake Timer Scale Factor Setting this bit causes this timer to shift by a factor of 16. GEN[3:0] General Purpose Timer Period These bits select the period of the general purpose timer. The time measured is the ...
Page 182
... IDs that could be used to select the LSI53C895. During a SCSI selection or reselection phase when a valid ID has been put on the bus, and the LSI53C895 responds to that ID, the “selected as” written into these bits. These bits are used with the RESPID registers to allow response to multiple IDs on the bus ...
Page 183
... SLT Selection Response Logic Test This bit is set when the LSI53C895 is ready to be selected or reselected. This does not take into account the bus settle delay of 400 ns. This bit is used for functional test and fault purposes. ART Arbitration Priority Encoder Test This bit is always set when the LSI53C895 exhibits the highest priority ID asserted on the SCSI bus during arbitration ...
Page 184
... SISO R QEN QSEL R 5.2.0.1 Quadrupling the SCSI Clock Frequency The LSI53C895 SCSI clock quadrupler increases the frequency MHz SCSI clock to 160 MHz. Follow these steps to use the clock quadrupler: 1. Set the SCLK Quadrupler Enable bit bit 3). 2. Poll bit 5 of the this bit as soon as it locks in the 160 MHz frequency ...
Page 185
... SE or LVD operation. This bit should be set in the initialization routine if the HVD interface is used. SLB SCSI Loopback Mode Setting this bit allows the LSI53C895 to perform SCSI loopback diagnostics. That is, it enables the SCSI core to simultaneously perform as both initiator and target. SCSI Registers ...
Page 186
... This bit does not affect the filtering period when the Ultra Enable bit in the SCSI Contr0l Three (SCNTL3) is set. When the LSI53C895 is executing Ultra2 SCSI transfers, the filtering period is automatically set at 8 ns. When the LSI53C895 is executing Ultra SCSI transfers, the filtering period is automatically set at 15 ns. ...
Page 187
... LSI53C895 is driving these signals. Active deassertion of these signals will occur only when the LSI53C895 information transfer phase. When operating in a differential environment or at fast SCSI timings, TolerANT Active negation should be enabled to improve setup and deassertion times ...
Page 188
... If this bit is set, the LSI53C895 ignores all bus-initiated selection attempts that employ the single-initiator option from SCSI-1. In order to select the LSI53C895 while this bit is set, the LSI53C895 SCSI ID and the initiator SCSI ID must both be asserted. This bit should be asserted in SCSI-2 systems so that a single bit error on the SCSI bus is not interpreted as a single initiator response ...
Page 189
... SCSI bus can be read from this register. Data can be written to the Latch (SODL) LSI53C895 by reading this register to allow loopback testing. When receiving SCSI data, the data flows into this register and out to the host FIFO. This register differs ...
Page 190
... LVD SCSI Frequency Lock This bit is used when enabling the SCSI clock quadrupler, which allows the LSI53C895 to transfer data at Ultra2 SCSI rates. Poll this bit for determine that the clock quadrupler has locked to 160 MHz. For more information on enabling the clock quadrupler, refer to the descriptions ...
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Register: 0x54–0x55 (0xD4–0xD5) SCSI Output Data Latch (SODL) Read/Write SODL SCSI Output Data Latch This register is used primarily for diagnostic testing or programmed I/O operation. Data written to this register is ...
Page 192
... SCRATCHB Register: 0x60–0x7F (0xE0–0xFF) Scratch Registers C–J (SCRATCHC Read/Write These registers are general-purpose scratch registers for user-defined functions. The LSI53C895 cannot fetch SCRIPTS instructions from this location. The power-up value of these registers is indeterminate. 5-94 Registers SCRATCHB ...
Page 193
... Section 6.6, “Transfer Control Instruction,” page 6-26 Section 6.7, “Memory Move Instructions,” page 6-33 Section 6.8, “Load and Store Instructions,” page 6-36 After power up and initialization of the LSI53C895, the chip can be operated in the low-level register interface mode or in the high-level SCSI SCRIPTS mode. LSI53C895 PCI to Ultra2 SCSI I/O Processor ...
Page 194
... High-Level SCSI SCRIPTS Mode To operate in the SCSI SCRIPTS mode, the LSI53C895 requires only a SCRIPTS start address. The start address must Dword (four byte) boundary to align all the following SCRIPTS at a Dword boundary since all SCRIPTS are bytes long ...
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... The host CPU, through programmed I/O, gives the Pointer (DSP) address in main memory that points to a SCSI SCRIPTS program for execution. 2. Loading the LSI53C895 to fetch its first instruction at the address just loaded. High-Level SCSI SCRIPTS Mode shows the types of SCRIPTS instructions are implemented in SCRIPTS Instructions Description ...
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... DMA FIFO for transfer to memory. At this point, the LSI53C895 requests use of the PCI bus again to transfer the data. 5. When the LSI53C895 is granted the PCI bus, it executes (as a bus master) a burst transfer (programmable size) of data, decrements the internally stored remaining byte count, increments the address pointer, and then releases the PCI bus ...
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... Data Structure Message Buffer Command Buffer Data Buffer Status Buffer High-Level SCSI SCRIPTS Mode Write DSA S Y Write S DSP Fetch P LSI53C895 SCRIPTS C SCSI Bus I For details, see B block diagram in U Chapter 2 S Data 6-5 ...
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Block Move Instruction Performing a Block Move instruction, bit 5, Source I/O - Memory Enable (SIOM) and bit 4, Destination I/O - Memory Enable (DIOM) in the Mode (DMODE) address resides in memory or I/O space. When data is ...
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Direct Addressing The byte count and absolute address are: Command Indirect Addressing Use the fetched byte count, but fetch the data address from the address in the instruction. . Command Once the data pointer address is loaded executed ...
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... For a MOVE instruction, the 24-bit byte count is fetched from system memory. Then the 32-bit physical address is brought into the LSI53C895. Execution of the move begins at this point. SCRIPTS can directly execute operating system I/O data structures, saving time at the beginning of an I/O operation ...