AM486DX4-100V16BGI Advanced Micro Devices, AM486DX4-100V16BGI Datasheet

no-image

AM486DX4-100V16BGI

Manufacturer Part Number
AM486DX4-100V16BGI
Description
Enhanced Microprocessor
Manufacturer
Advanced Micro Devices
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AM486DX4-100V16BGI
Manufacturer:
RENESAS
Quantity:
154
Part Number:
AM486DX4-100V16BGI
Manufacturer:
AMD
Quantity:
3 359
Part Number:
AM486DX4-100V16BGI
Manufacturer:
AMD
Quantity:
1 286
Part Number:
AM486DX4-100V16BGI
Manufacturer:
AMD
Quantity:
295
Price:
1.00 USD
Part Number:
AM486DX4-100V16BGI25544�汾
Manufacturer:
AMD
Quantity:
1 286
DISTINCTIVE CHARACTERISTICS
Enhanced Am486
Microprocessor Family
GENERAL DESCRIPTION
The Enhanced Am486
addition to the AMD E86 family of embedded micropro-
cessors. This new family enhances system performance
by incorporating a 16-Kbyte write-back cache to the ex-
isting flexible clock control and enhanced SMM features
of a 486 CPU.
The Enhanced Am486DX microprocessor family en-
ables write-back configuration through software and
cacheable access control. On-chip cache lines are con-
figurable as either write-through or write-back. The CPU
clock control feature permits the CPU clock to be stopped
under controlled conditions, allowing reduced power
consumption during system inactivity. The SMM function
is implemented with an industry standard two-pin inter-
face.
Since the Enhanced Am486DX microprocessor family is
supported as an embedded product, customers can rely
on continued cost reduction, a long-term supply, and
extended temperature products.
In addition, customers have access to a large selection
of inexpensive development tools, compilers, and
chipsets. A large number of PC operating systems and
Real Time Operating Systems (RTOS) support the En-
This document contains information on a product under development at Advanced Micro Devices. The information is
intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
High-Performance Design
-
-
-
-
-
-
-
High On-Chip Integration
-
-
-
Enhanced System and Power Management
-
Industry-standard write-back cache support
Frequent instructions execute in one clock
105.6-million bytes/second burst bus at 33 MHz
Flexible write-through and write-back address
control
Advanced 0.35- CMOS-process technology
Dynamic bus sizing for 8-, 16-, and 32-bit buses
Supports “soft reset” capability
16-Kbyte unified code and data cache
Floating-point unit
Paged, virtual memory management
Stop clock control for reduced power
consumption
PRELIMINARY
®
DX Microprocessor Family is an
®
DX
hanced Am486DX microprocessor family. This results in
decreased development costs and improved time to mar-
ket.
Table 1 shows available processors in the Enhanced
Am486DX microprocessor family. See page 54 for in-
formation on how these parts differ from other Am486
processors.
Am486DX5-133
Am486DX5-133
Am486DX4-100
Am486DX4-100
Am486DX2-66
Am486DX2-66
Frequency
-
-
-
Complete 32-Bit Architecture
-
-
-
Standard Features
-
-
168-Pin PGA Package or 208-Pin SQFP Package
IEEE 1149.1 JTAG Boundary-Scan Compatibility
Operating
Industry-standard two-pin System Management
Interrupt (SMI) for power management indepen-
dent of processor operating mode and operating
system
Static design with Auto Halt power-down support
Wide range of chipsets supporting SMM avail-
able to allow product differentiation
Address and data buses
All registers
8-, 16-, and 32-bit data types
3-V core with 5-V tolerant I/O
Wide range of chipsets and support available
through the AMD FusionE86
Table 1. Clocking Options
Input Clock
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
Publication # 20736 Rev: B Amendment/0
Issue Date: March 1997
Available Package
SM
208-pin SQFP
208-pin SQFP
208-pin SQFP
168-pin PGA
168-pin PGA
168-pin PGA
Program

Related parts for AM486DX4-100V16BGI

AM486DX4-100V16BGI Summary of contents

Page 1

... Table 1 shows available processors in the Enhanced Am486DX microprocessor family. See page 54 for in- formation on how these parts differ from other Am486 processors. Table 1. Clocking Options Operating Input Clock Frequency Am486DX5-133 Am486DX5-133 Am486DX4-100 Am486DX4-100 Am486DX2-66 Am486DX2-66 SM Program Available Package 33 MHz 168-pin PGA 33 MHz 208-pin SQFP 33 MHz ...

Page 2

BLOCK DIAGRAM 32-Bit Data Bus Segmentation Barrel Shifter Unit Descriptor Register File Registers 24 Physical Limit and Address ALU Attribute PLA Micro-instruction Floating Central and Point Protection Unit Test Unit Floating Control Point Register ROM File 2 Enhanced Am486DX Microprocessor ...

Page 3

LOGIC SYMBOL CLK Clock STPCLK Stop Clock CLKMUL Clock Multiplier A20M Address Mask Upgrade UP Present VOLDET Voltage Detect A31–A4 28 A3–A2 2 Address Bus BE3–BE0 4 BS8 BS16 Bus Cycle ADS Control RDY M/IO D/C Bus Cycle W/R Definition ...

Page 4

... AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. AM486 DX 5 –133 W 16 Valid Combinations AM486DX2-66V16B AM486DX4-100V16B AM486DX5-133W16B HC GC AM486DX5-133V16B Enhanced Am486DX Microprocessor Family ...

Page 5

TABLE OF CONTENTS Distinctive Characteristics ......................................................................................................................................... 1 General Description .................................................................................................................................................. 1 Block Diagram........................................................................................................................................................... 2 Logic Symbol ........................................................................................................................................................... 3 Ordering Information ................................................................................................................................................. 4 Connection Diagrams and Pin Designations ............................................................................................................ 8 168-Pin PGA (Pin Grid Array) Package ............................................................................................................. 8 168-Pin PGA Designations ...

Page 6

LIST OF FIGURES Figure 1 Processor-Induced Line Transitions in Write-Back Mode .................................................................... 20 Figure 2 Snooping State Transitions .................................................................................................................. 20 Figure 3 Typical System Block Diagram for HOLD/HLDA Bus Arbitration ......................................................... 21 Figure 4 External Read ...................................................................................................................................... 22 Figure 5 ...

Page 7

LIST OF TABLES Table 1 Clocking Options .................................................................................................................................... 1 Table 2 CLKMUL Settings ................................................................................................................................. 13 Table 3 EADS Sample Time ............................................................................................................................. 14 Table 4 Cache Line Organization ..................................................................................................................... 18 Table 5 Legal Cache Line States ...................................................................................................................... 18 Table 6 MESI ...

Page 8

CONNECTION DIAGRAMS AND PIN DESIGNATIONS 1.1 168-Pin PGA (Pin Grid Array) Package 8 Enhanced Am486DX Microprocessor Family PIN SIDE VIEW ...

Page 9

PGA Designations (Functional Grouping) Address Data Pin Pin Pin Pin Name No. Name No. A2 Q-14 D0 P-1 A3 R-15 D1 N-2 A4 S-16 D2 N-1 A5 Q-12 D3 H-2 A6 S-15 D4 M-3 A7 Q-13 D5 J-2 ...

Page 10

SQFP (Shrink Quad Flat Pack) Package 10 Enhanced Am486DX Microprocessor Family TOP VIEW ...

Page 11

SQFP Designations (Functional Grouping) Address Data Pin Name Pin Pin Name No. A2 202 D0 144 A3 197 D1 143 A4 196 D2 142 A5 195 D3 141 A6 193 D4 140 A7 192 D5 130 A8 190 ...

Page 12

PIN DESCRIPTION The Enhanced Am486DX microprocessors provide the complete interface support offered by the Enhanced Am486 family. However, the CLKMUL pin settings have changed to accommodate the higher operating speed selection. For more information on how all Am486 pro- ...

Page 13

... Enhanced Am486DX Microprocessor Family Processor Am486DX2-66 Am486DX4-100 Am486DX5-133 2x indicates that the CPU runs at twice the system bus speed. 3x indicates that the CPU runs at three times the system bus speed. 4x indicates that the CPU runs at four times the system bus speed. ...

Page 14

INV is sampled in the same clock period that EADS is asserted. EADS has an internal weak pull- up. Table 3. EADS Sample Time Trigger EADS First Sampled AHOLD Second clock after AHOLD asserted HOLD First clock after ...

Page 15

EADS is active. INV has an internal weak pull-up. INV is ignored in Write-through mode. KEN Cache Enable (Active Low; Input) KEN determines whether the current cycle is cacheable. When the microprocessor generates a cacheable cycle and KEN is ...

Page 16

RDY is active during address hold. Data can be returned to the processor while AHOLD is active. RDY is active Low and does not have an internal pull- up resistor. RDY must satisfy setup and hold times t ...

Page 17

WB/WT Write-Back/Write-Through (Input) If the processor samples WB/WT High at RESET, the processor is configured in Write-back mode and all sub- sequent cache line fills sample WB/WT on the same clock edge in which it finds either RDY or the ...

Page 18

Write-Back Cache The microprocessor write-back cache architecture is characterized by the following: External read accesses are placed in the cache if they meet proper caching requirements. Subsequent reads to the data in the cache are made if the address ...

Page 19

Modified A modified line contains valid data for an external mem- ory location. However, the data does not match the data in the external location because the processor has mod- ified the data since it was loaded from the ...

Page 20

Invalid Read_Miss Read_Miss [(WB/ (PWT = 1) (WB/ (PWT = 0) Exclusive Read_Hit Write_Hit + Read_Hit Write_Hit Modified Read_Hit + Write_Hit Figure 1. Processor-Induced Line Transitions in Write-Back Mode If the PWT signal is 0, ...

Page 21

Difference Between Snooping Access Cases Snooping accesses are external accesses to the micro- processor. As described earlier, the snooping logic has a set of signals independent from the processor-related signals. Those signals are: EADS INV HITM In addition to ...

Page 22

CLK ADR M/IO W/R 1 ADS BLAST BRDY Data KEN WB/WT BOFF Note: The circled numbers in this figure represent the steps in section 4.8.2.2.2. CLK ADR M/IO W/R ADS BLAST BRDY Data WB/WT BOFF Note: The circled numbers in ...

Page 23

External Bus Master Snooping Actions The following scenarios describe the snooping actions of an external bus master. 3.8.3.1 Snoop Miss Scenario : A snoop of the on-chip cache does not hit a line, as shown in Figure 6. Step ...

Page 24

CLK ADR INV EADS HITM HOLD HLDA Note: The circled numbers in this figure represent the steps in section 4.8.3.2. Figure 7. Snoop of On-Chip Cache That Hits a Non-Modified Line CLK ADR n M/IO CACHE floating/three-stated W/R ADS BLAST ...

Page 25

Step 4 In the next clock, the core system logic deas- serts the HOLD signal in response to the HITM = 0 signal. The core system logic backs off the current bus master at the same time so that the ...

Page 26

Step 1 HOLD places the microprocessor in Snooping mode. HLDA must be High for a minimum of one clock cycle before EADS assertion. In the fastest case, this means that HOLD asserts one clock cycle before the HLDA response. Step ...

Page 27

Step 3 If RDY is returned instead of BRDY during a write-back, the HOLD signal can be reasserted at any time starting one clock after ADS goes active in the first transfer up to the final transfer when RDY is ...

Page 28

CLK ADR from CPU to CPU M/IO CACHE W/R 1 ADS BLAST 3 BRDY AHOLD 2 INV EADS HITM Data Note: The circled numbers in this figure represent the steps in section 4.8.5.3. Figure 12. Snoop Hit Cycle with Write-Back ...

Page 29

CLK ADR R1 from CPU W1 to CPU M/IO CACHE W/R ADS BLAST BRDY BOFF AHOLD INV EADS HITM Data Note: The circled numbers in this figure represent the steps in section 4.8.6. Figure 13. Cycle Reordering with BOFF (Write-Back) ...

Page 30

CLK 2 XXX A Write Buffer B original Cached Data AHOLD 1 EADS HITM ADS BLAST BRDY Data Note: The circled numbers in this figure represent the steps in section 4.8.7.1. Figure 14. Write Cycle Reordering Due to Buffering Step ...

Page 31

Cache Line Fills The microprocessor aborts a cache line fill during a burst read if BOFF is asserted during the access. Upon re- gaining the bus, the read access commences where it left off when BOFF was recognized. External ...

Page 32

Two special bus cycles follow the write-back of modified data upon execution of the WBINVD instruction: first the write-back, and then the flush special bus cycle. The INVD operates identically to the standard 486 micropro- cessor in that the flush ...

Page 33

CLK ADR M/IO W/R CACHE ADS BLAST BRDY Data CLK XX4 ADR XX0 M/IO W/R CACHE ADS BLAST BRDY BOFF Data XX0 XX4 to CPU Figure 17. Burst Read with BOFF Assertion CLK ADR XX0 XX4 M/IO W/R CACHE ADS ...

Page 34

CACHE is a cycle definition pin used when in Write-back mode (CACHE floats in Write-through mode). For pro- cessor-initiated cycles, the signal indicates: For a read cycle, the internal cacheability of the cycle For a write cycle, a burst write-back ...

Page 35

Empties all internal pipelines and write buffers Generates a Stop Grant bus cycle Stops the internal clock At this point the CPU is in the Stop Grant state. The CPU cannot respond to a STPCLK request from an HLDA state ...

Page 36

To achieve the lowest possible power consumption dur- ing the Stop Grant state, the system designer must en- sure that the input signals with pull-up resistors are not driven Low, and the input signals with pull-down resis- tors are not ...

Page 37

(valid for Write-back mode only) Figure 20. Stop Clock State Machine CLK STPCLK Sampled STPCLK t 20 NMI SMI Note Earliest time at which NMI or SMI ...

Page 38

Stop Clock State Stop Clock state is entered from the Stop Grant state by stopping the CLK input (either logic High or logic Low). None of the CPU input signals should change state while the CLK input is stopped. ...

Page 39

SMI: System Management Interrupt. This is the trig- ger mechanism for the SMM interface. When SMI is asserted (SMI pin asserted Low) it causes the pro- cessor to invoke SMM. The SMI pin is the only means of entering SMM. ...

Page 40

SMIACT CPU } SMI Figure 23. Basic SMI Hardware Interface 6.3.1 System Management Interrupt Processing SMI is a falling-edge-triggered, non-maskable interrupt request signal. SMI is an asynchronous signal, but setup and hold times must be met to guarantee recognition in ...

Page 41

T1 T2 CLK CLK2 SMI ADS RDY SMIACT A: Last RDY from non-SMM transfer to SMIACT assertion2 CLKs minimum B: SMIACT assertion to first ADS for SMM state save C: SMM state save (dependent on memory performance) 140 CLKs D: ...

Page 42

SMRAM State Save Map When SMI is recognized on an instruction boundary, the CPU core first sets the SMIACT signal Low, indicating to the system logic that accesses are now being made to the system-defined SMRAM areas. The CPU ...

Page 43

Entering System Management Mode SMM is one of the major operating modes, along with Protected mode, Real mode, and Virtual mode. Figure 27 shows how the processor can enter SMM from any of the three modes and then return. ...

Page 44

Table 12. SMM Initial CPU Core Register Settings Register SMM Initial State General Purpose Unmodified Registers EFLAGS 0000 0002h CR0 Bits and 31 cleared (PE, EM, TS, and PG); rest unmodified DR6 Unpredictable state DR7 0000 0400h ...

Page 45

EFLAGS register (using the STI instruction). Software interrupts are not blocked on entry to SMM, and the system software designer must provide an SMM-com- pliant interrupt handler before attempting to execute any software interrupt instructions. Note that in SMM mode, ...

Page 46

Table 16. HALT Auto Restart Configuration Value at Value Processor Action on Exit Entry at Exit 0 0 Returns to next instruction in interrupt- ed program 0 1 Unpredictable 1 0 Returns to instruction after HALT 1 1 Returns to ...

Page 47

SMRAM SMBASE + 8000h Start of State Save + 7FFFh SMI Handler Entry Point SMBASE + 8000h SMBASE Figure 31. SRAM Usage The SMBASE must be a 32-Kbyte aligned, 32-bit integer that indicates a base address for the SMRAM context ...

Page 48

State Save SMI SMIACT Figure 33. SMM Timing in Systems Using Non-Overlaid Memory Space and Write-Through Mode with Caching Enabled During SMM State Save SMI SMIACT WB/WT Note: For proper operation of systems configured in Write-back mode when caching during ...

Page 49

SMI State Save Instruction x SMI SMIACT FLUSH Cache contents invalidated Figure 36. SMM Timing in Systems Using Overlaid Memory Space and Write-Through Mode with Caching Enabled During SMM SMI State Save Instruction x SMI SMIACT FLUSH Cache contents invalidated ...

Page 50

Cache Flushes The CPU does not unconditionally flush its cache before entering SMM. Therefore, the designer must ensure that, for systems using overlaid SMRAM, the cache is flushed upon SMM entry and SMM exit if caching is enabled. Note: ...

Page 51

SMM space or normal memory space. This can be accomplished by saving the status of SMIACT with the address for each word in the write buffers. 6.8.6 Nested SMI and I/O Restart Special care must be taken ...

Page 52

Table 18. Test Register TR4 Bit Descriptions 31 30–29 28 27–26 EXT=0 Not STn Rsvd. ST3 EXT=1 used Table 19. Test Register TR5 Bit Descriptions 31–20 19 Write-Back Not used Ext Write-Through Notes: 1. Bit 19 in TR5 is EXT. ...

Page 53

Valid (bit 10): Read/Write, independent of the Ext bit in TR5. This is the Valid bit for the accessed entry cache look-up, Valid is a copy of one of the bits reported in bits 6– cache ...

Page 54

... Processor Standard Am486DX processors Am486DE2 processors Enhanced Am486 Microprocessor Family (Am486DX2, Am486DX4) Enhanced Am486DX Microprocessor Family (Am486DX2, Am486DX4, Am486DX5) 54 Enhanced Am486DX Microprocessor Family modified data to external memory prior to issuing the special bus cycle or reset. The RESET state is invoked either after power up or after the RESET signal is applied according to the standard 486DX microprocessor specification ...

Page 55

... RESET. The upper byte of DX (DH) contains 04 and the lower byte of DX (DL) contains a CPU type/stepping identifier (see Table 21). Table 21. CPU ID Codes Processor CLKMUL Am486DX2-66 0 (x2) Am486DX4-100 1 (x3) Am486DX5-133 0 (x4) 9.2 CPUID Instruction The Enhanced Am486DX microprocessors implement the CPUID instruction that makes information available to software about the family, model and stepping of the processor on which it is executing ...

Page 56

ELECTRICAL DATA The following sections describe recommended electri- cal connections and electrical specifications for the En- hanced Am486DX microprocessors. 10.1 Power and Grounding 10.1.1 Power Connections With 16 Kbyte of cache, the Enhanced Am486DX mi- croprocessors have modest power ...

Page 57

ABSOLUTE MAXIMUM RATINGS Case Temperature under Bias . . . – 65°C to +110°C Storage Temperature . . . . . . . . . . – 65°C to +150°C Voltage on any pin with respect to ground . . ...

Page 58

SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges The AC specifications, provided in the AC characteris- tics table, consist of output delays, input setup require- ments, and input hold requirements. All AC specifica- tions are relative to the rising edge ...

Page 59

AC Characteristics for Boundary Scan Test Signals at 25 MHz V = 3.3 V ± 0.3 V (see Note 4 unless otherwise specified L Symbol Parameter t TCK Frequency 24 t TCK Period 25 ...

Page 60

SWITCHING WAVEFORMS Waveform 60 Enhanced Am486DX Microprocessor Family Key to Switching Waveforms Inputs Outputs Must be steady Will be steady Will change May change from from ...

Page 61

Figure 41. Maximum Float Delay Timing Figure 42. PCHK Valid Delay Timing Enhanced Am486DX Microprocessor Family 61 ...

Page 62

Figure 44. RDY and BRDY Input Setup and Hold Timing 62 Enhanced Am486DX Microprocessor Family 18a Figure 43. Input Setup and Hold Timing ...

Page 63

Figure 45. TCK Waveforms Figure 46. Test Signal Timing Diagram Enhanced Am486DX Microprocessor Family 63 ...

Page 64

PACKAGE THERMAL SPECIFICATIONS The Enhanced Am486DX microprocessors are speci- fied for operation when T (the case temperature) is CASE within the range + CASE in any environment to determine whether the Enhanced Am486DX ...

Page 65

PHYSICAL DIMENSIONS 168-Pin PGA (CGM-168) Index Corner 1.600 BSC 1.735 1.765 Bottom View (Pins Facing Up) Notes: 1. All measurements are in inches. 2. Not to scale. For reference only. 3. BSC is an ANSI standard for Basic Space ...

Page 66

... AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Am486 is a registered trademark; and FusionE86 is a service mark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ...

Related keywords