MC68HC11E1FN Motorola, MC68HC11E1FN Datasheet

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MC68HC11E1FN

Manufacturer Part Number
MC68HC11E1FN
Description
M68HC11 Family of microcontroller units (MCUs)
Manufacturer
Motorola
Datasheet

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MC68HC11E1FN Summary of contents

Page 1

HC11 HC11 HC11 Order this document by M68HC11RM/AD M68HC11 Reference Manual Rev. 3.0 ...

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... Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended ...

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... System Development and Debug Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37 2.7.1 Load Instruction Register (LIR 2-37 2.7.2 Internal Read Visibility (IRV 2-37 2.7.3 MC68HC24 Port Replacement Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38 M68HC11 REFERENCE MANUAL Section 1 GENERAL DESCRIPTION Section 2 PINS AND CONNECTIONS and 2 and MODA/LIR 2-8 STBY , V , PE[7:0 2-18 REFL REFH Pin 2-31 PPBULK TABLE OF CONTENTS Page Number MOTOROLA iii ...

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... Conditions and Practices to Avoid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4.4.2 Using EEPROM to Select Product Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 4.4.3 Using EEPROM for Setpoint and Calibration Information . . . . . . . . . . . . . . . . . . . . 4-18 4.4.4 Using EEPROM during Product Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 4.4.5 Logging Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 4.4.6 Self-Adjusting Systems using EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 4.4.7 Software Methods to Extend Life Expectancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 MOTOROLA iv Section 3 Section 4 ON-CHIP MEMORY TABLE OF CONTENTS Page Number ...

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... Automatic Clearing Mechanisms on Some Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 6.1 Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1.1 Accumulators (A, B, and 6-1 6.1.2 Index Registers (X and 6-2 6.1.3 Stack Pointer (SP 6-3 6.1.4 Program Counter (PC 6-4 6.1.5 Condition Code Register (CCR 6-4 6.2 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.2.1 Immediate (IMM 6-6 M68HC11 REFERENCE MANUAL Section 5 RESETS AND INTERRUPTS Section 6 CENTRAL PROCESSING UNIT TABLE OF CONTENTS Page Number MOTOROLA v ...

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... Port C Single-Chip Mode Pin Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18 7.3.4.4 Port C Idealized Single-Chip Mode Timing 7-21 7.3.4.5 Special Considerations for Port C on MC68HC24 PRU . . . . . . . . . . . . . . . . . . 7-23 7.3.5 AS (STRA) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23 7.3.5.1 AS (STRA) Pin Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23 7.3.5.2 Special Considerations for STRA on MC68HC24 PRU . . . . . . . . . . . . . . . . . . 7-25 7.3.6 Port 7-25 7.3.6.1 PD0 (RxD) Pin Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25 MOTOROLA vi Section 7 PARALLEL INPUT/OUTPUT TABLE OF CONTENTS Page Number M68HC11 ...

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... Transmitter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.1.2 Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.2 SCI Registers and Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9.2.1 Port D Related Registers and Control Bits (PORTD, DDRD, SPCR 9-6 9.2.2 Baud-Rate Control Register (BAUD 9-7 9.2.3 SCI Control Register 1 (SCCR1 9-9 9.2.4 SCI Control Register 2 (SCCR2 9-10 M68HC11 REFERENCE MANUAL Section 8 Section 9 TABLE OF CONTENTS Page Number MOTOROLA vii ...

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... Establishing a Relationship between Software and an Event . . . . . . . . . . . . . . . 10-27 10.3.7 Other Uses for Input-Capture Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28 10.4 Output-Compare Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28 10.4.1 Normal I/O Pin Control Using OC[5: 10-32 10.4.2 Advanced I/O Pin Control Using OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-35 10.4.2.1 One Output Compare Controlling up to Five Pins . . . . . . . . . . . . . . . . . . . . 10-35 10.4.2.2 Two Output Compares Controlling One Pin . . . . . . . . . . . . . . . . . . . . . . . . . 10-36 MOTOROLA viii Section 10 TABLE OF CONTENTS Page Number M68HC11 ...

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... MC68HC11A8 Successive-Approximation A/D Converter . . . . . . . . . . . . . . . . . . 12-12 12.2.2 A/D Charge Pump and Resistor-Capacitor (RC) Oscillator . . . . . . . . . . . . . . . . . 12-13 12.2.3 MC68HC11A8 A/D System Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14 12.2.4 A/D Control/Status Register (ADCTL 12-15 12.2.5 A/D Result Registers (ADR[4:1 12-17 12.3 A/D Pin Connection Considerations 12-17 A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.2 Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 M68HC11 REFERENCE MANUAL Section 11 PULSE ACCUMULATOR Section 12 Appendix A INSTRUCTION SET DETAILS Appendix B BOOTLOADER LISTINGS INDEX TABLE OF CONTENTS Page Number MOTOROLA ix ...

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... MOTOROLA x TABLE OF CONTENTS M68HC11 REFERENCE MANUAL ...

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... Topological Arrangement of Bits in an EEPROM Byte ................................... 4-5 4-3 Condensed Schematic of EEPROM Array ..................................................... 4-6 4-4 EEPROM Cell Terminology ............................................................................ 4-7 4-5 Erasing an EEPROM Byte ............................................................................. 4-7 4-6 Programming an EEPROM Byte .................................................................... 4-8 4-7 Reading an EEPROM Byte ............................................................................ 4-9 4-8 Erase-Before-Write Programming Method ................................................... 4-24 M68HC11 REFERENCE MANUAL LIST OF FIGURES Title Connections .................................................... 2-11 STBY Pin .......................................................... 2-30 STBY Pin .......................................................... 2-31 PPBULK LIST OF FIGURES Page MOTOROLA xi ...

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... PD4 (SCK) Pin Logic .................................................................................... 7-34 7-21 PD5 (SS) Pin Logic ...................................................................................... 7-36 7-22 Idealized Port D Timing ................................................................................ 7-38 7-23 Port E Pin Logic ............................................................................................ 7-40 7-24 Idealized Port E Timing ................................................................................ 7-41 7-25 Idealized Timing for Simple Strobe Operations ............................................ 7-42 7-26 Idealized Timing for Full-Input Handshake ................................................... 7-44 7-27 Idealized Timing for Full-Output Handshake ................................................ 7-45 MOTOROLA xii Title LIST OF FIGURES Page M68HC11 REFERENCE MANUAL ...

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... Measuring a Pulse Width with Input Capture ............................................. 10-22 10-7 Timing Analysis for Example 10–2 ............................................................. 10-23 10-8 Measuring Long Periods with Input Capture and TOF (Sheet ........ 10-26 10-9 Simple Output-Compare Example .............................................................. 10-31 10-10 Generating a Square Wave with Output Compare ..................................... 10-33 10-11 Timing Analysis for Example 10–5 ............................................................. 10-34 M68HC11 REFERENCE MANUAL Title LIST OF FIGURES Page MOTOROLA xiii ...

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... PACNT Read and Write ............................................................................. 11-12 12-1 Basic Charge-Redistribution A/D .................................................................. 12-2 12-2 Charge-Redistribution A/D with 12-3 MC68HC11A8 A/D in Sample Mode .......................................................... 12-12 12-4 Timing Diagram for a Sequence of Four A/D Conversions ........................ 12-15 12-5 Electrical Model of an A/D Input Pin (Sample Mode) ................................. 12-17 12-6 Graphic Estimation of Analog Sample Level (Case 2) ............................... 12-21 MOTOROLA xiv Title 1/2 LSB Quantization Error ..................... 12-9 LIST OF FIGURES Page M68HC11 REFERENCE MANUAL ...

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... Baud Rates by Crystal Frequency, SCP[1:0] and SCR[2:0] .............................. 9-32 10-1 Crystal Frequency vs. PR1, PR0 Values ......................................................... 10-10 10-2 RTI Rates vs. RTR1, RTR0 for Various Crystal Frequencies.......................... 10-13 10-3 COP Time-Out vs. CR1, CR0 Values .............................................................. 10-14 10-4 Instruction Sequences To Clear TOF .............................................................. 10-15 11-1 Pulse Accumulator Timing Periods vs. Crystal Rate ......................................... 11-2 M68HC11 REFERENCE MANUAL LIST OF TABLES Title LIST OF TABLES Page MOTOROLA xv ...

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...

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... CENTRAL PROCESSING UNIT contain examples demonstrating efficient use of the instruction set. This manual is intended to complement Motorola’s official data sheet, not replace it. The information in the data sheet is current and is guaranteed by production testing. Although the information in this manual was checked against parts and design docu- mentation, the accuracy is not guaranteed like the data sheet is guaranteed ...

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... The exchange D with X and exchange D with Y instructions can be used to quickly get index values into the double accumulator (D) where 16-bit arithmetic can be used. Two 16-bit by 16-bit divide instructions are also included. MOTOROLA 1-2 GENERAL DESCRIPTION M68HC11 ...

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... CIRCUITRY ENCLOSED BY DOTTED LINE IS EQUIVALENT TO MC68HC24. M68HC11 REFERENCE MANUAL E IRQ/ XIRQ RESET INTERRUPT LOGIC CPU ADDRESS/DATA PARALLEL I/O CONTROL PORT C EXPANDED MODE Figure 1-1 Block Diagram GENERAL DESCRIPTION 8 KBYTES ROM V V 512 BYTES EEPROM V 256 BYTES RAM V SPI SCI A/D CONVERTER CONTROL PORT D PORT E MOTOROLA 1-3 ...

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... A 15 Figure 1-2 M68HC11 Programmer’s Model 1.3 Product Derivatives The M68HC11 Family of MCUs is composed of several members (see new members are being developed. bers are constructed. MOTOROLA 1 Figure 1-3 explains how the product part num- GENERAL DESCRIPTION 8-BIT ACCUMULATORS A & ...

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... SDIP MAXIMUM SPECIFIED CLOCK SPEED 2 — 2.0 MHz 3 — 3.0 MHz 4 — 4.0 MHz TAPE AND REEL OPTION NONE — STANDARD PACKAGING R2 — TAPE AND REEL PACKAGING M68HC11 REFERENCE MANUAL Figure 1-3 Part Numbering GENERAL DESCRIPTION 11XX HC11 PART NUMBERING MOTOROLA 1-5 ...

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... EEPROM is relocatable to the top of any 4 Kbyte memory page. Relocation is done with the upper four bits of the CONFIG register. 2. CONFIG register values in this table reflect the value programmed prior to shipment from Motorola the time of this printing a change was being considered that would make this value $0F. ...

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... DIP. The MC68HC11A1 and MC68HC11A0 devices also use the same die as the MC68HC11A8, except that the contents of the nonvolatile CONFIG register determine whether or not internal read-only memory (ROM) and/or electrically M68HC11 REFERENCE MANUAL SECTION 2 Connections. These basic systems can be used as the PINS AND CONNECTIONS and 2.6 Typical Ex- MOTOROLA 2-1 ...

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... EPROM instead of mask programmed ROM. The MC68HC711D3 is available as a one-time-programmable (OTP) MCU in an opaque plastic package ceramic windowed package for development applications. Figure 2-2 shows the pin assignments for the MC68HC11D3/711D3 in the 44-pin PLCC package and the 40-pin DIP package. MOTOROLA 2-2 PA7/PAI/OC1 1 PA6/OC2/OC1 2 PA5/OC3/OC1 3 PA4/OC4/OC1 ...

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... PA0/IC3 PD0/RxD 15 29 PA1/IC2 PD1/TxD 16 PD2/MISO 17 PD3/MOSI 18 19 PD4/SCK 20 PD5/SS PINS AND CONNECTIONS 40 XTAL EXTAL MODA/LIR 37 36 MODB/V STBY PB0/ADDR8 35 PB1/ADDR9 34 MC68HC(7)11D3 PB2/ADDR10 33 32 PB3/ADDR11 PB4/ADDR12 31 PB5/ADDR13 30 PB6/ADDR14 29 PB7/ADDR15 28 27 PA0/IC3 26 PA1/IC2 PA2/IC1 25 PA3/IC4/OC5/OC1 24 PA5/OC3/OC1 23 22 PA7/PAI/OC1 MOTOROLA 2-3 ...

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... MC68HC811E2 has a slightly more flexible timer system, which allows one output-compare channel to be reconfigured as a fourth input-capture channel. The 52-pin PLCC package version of the MC68HC811E2 has identical pin assign- ments to the MC68HC11E9 pin assignments shown in trates the pin assignments for the MC68HC811E2 in the 48-pin DIP. MOTOROLA 2 ...

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... PB1/A9 15 PB0/ PINS AND CONNECTIONS V DD PD5/SS PD4/SCK PD3/MOSI PD2/MISO PD1/TxD PD0/RxD IRQ XIRQ RESET PC7/A7/D7 PC6/A6/D6 PC5/A5/D5 PC4/A4/D4 PC3/A3/D3 PC2/A2/D2 PC1/A1/D1 PC0/A0/D0 XTAL EXTAL STRB/R/W E STRA/AS MODA/LIR MOTOROLA 2-5 ...

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... Figure 2-5 MC68HC11F1 Pin Assignments (68-Pin PLCC) 2.1.6 MC68HC24 Port Replacement Unit The MC68HC24 is available in either a 44-pin PLCC package or a 40-pin DIP. 2-6 shows the pin assignments for the MC68HC24 in the 44-pin PLCC package and the 40-pin DIP package. MOTOROLA 2-6 MC68HC11F1 PINS AND CONNECTIONS 60 PE4/AN4 ...

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... R RESET AD0 7 MC68HC24 AD1 33 8 AD2 32 9 AD3 AD4 11 29 AD5 12 AD6 28 13 AD7 IRQ 16 25 PB0 24 17 PB1 23 18 PB2 19 22 PB3 20 21 contains transistor-level SECTION 3 CONFIGU- is the positive power input, and MOTOROLA 2-7 ...

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... B selects between the normal variation and the special variation of the chosen operating mode. Bootstrap mode is the special variation of single-chip mode, and special test is the special variation of expanded mode. rizes the operation of the mode pins and mode control bits. MOTOROLA 2-8 and MODA/LIR) STBY ...

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... RAM contents when V STBY . Since the LIR output is open-drain, there is SS connection and the LIR signal that drives the pin low SS 4 33% duty cycle). PINS AND CONNECTIONS MDA IRV not present MOTOROLA 2-9 ...

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... RAM. The MODB/V pin method would be used in cases where there is a significant STBY amount of external circuitry operating from V supplies and added logic is justified by the power savings. MOTOROLA 2-10 74HC04 4.7K TO MODA/LIR OF M68HC11 MODA/LIR Connections ...

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... MHz), and Figure 2-10 shows connections for low-frequency operation (less than 1 MHz). M68HC11 REFERENCE MANUAL MAX 690 V DD 4.7K TO MODB/V STBY V OUT OF M68HC11 V BATT Connections STBY show the internal and external components that form the PINS AND CONNECTIONS load resistor to ground may MOTOROLA 2-11 ...

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... Higher frequency AT-cut crystals are designed for much higher drive levels. Figure 2-9 High-Frequency Crystal Connections Figure 2-10 Low-Frequency Crystal Connections Exact values for the external components are a function of wafer processing parame- ters, package capacitance, printed circuit board (PCB) capacitance and inductance, MOTOROLA 2-12 and C2 provide a phase shift STOP ...

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... Figure 2-11). Figure 2-11 Crystal Layout Example M68HC11 REFERENCE MANUAL S paths as shown in Figure SS SS CRYSTAL C2 C1 PIN 7 EXTAL R f PIN 8 XTAL M68HC11 MCU PINS AND CONNECTIONS will be discussed at the con- 2-11. These paths isolate paths ending under C1 and MOTOROLA 2-13 ...

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... MCU will be held in reset throughout the experiment. Because of the number of variables involved, use components with the exact proper- ties of those that will be used in production. For example, do not use a ceramic-pack- aged MCU prototype for the experiment when a plastic-packaged MCU will be used in MOTOROLA 2-14 (oscilloscope input) forms a resis- SS ...

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... M68HC11. Use a single inverter and connect the crystal feedback resistor and load M68HC11 REFERENCE MANUAL , observe the operating current ( Normally, a dip in current will occur. This dip is not S is not critical PINS AND CONNECTIONS ) of the DD at the buffered E-clock output. , C1, S MOTOROLA 2-15 ...

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... RESET pin of the MC68HC11A8. This device is connected and the RESET pin of the MCU. A pull-up resistor from RESET other component required for the reset circuit in most applications. a typical reset circuit. MOTOROLA 2-16 INTERRUPTS. pin whenever V is too low to support proper MCU oper below legal limits ...

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... EEPROM locations, the external 20-V power supply is needed to supplement the on-chip charge pump. The M68HC11 REFERENCE MANUAL RESET MC34064 GND RESET MC34164 GND 3 programming voltage source, PP PINS AND CONNECTIONS RESET OF M68HC11 MOTOROLA 2-17 ...

Page 40

... A/D reference and input pins are controlled by signals that switch between V about 7 V. This higher-than-V the charge pump used for programming on-chip EEPROM). There is no special re- quirement to keep V REFH good results up to approximately MOTOROLA 2- PE[7:0]) REFL REFH SYSTEM). These pins are normally ...

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... OC1 output pin. 2.2.9 Serial Port D Pins Port D includes six general-purpose, bidirectional I/O pins that can be individually con- figured as inputs or as outputs. When the serial communications interface (SCI) re- M68HC11 REFERENCE MANUAL REFH OF M68HC11 REFL OF M68HC11 PINS AND CONNECTIONS MOTOROLA 2-19 ...

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... To save pins, the low-order address and 8-bit data are time multiplexed on eight pins. During the first half of each bus cycle, address output signals, ADDR[7:0], are present on these eight pins; during the second half of each bus cycle, these eight MOTOROLA 2-20 PINS AND CONNECTIONS ...

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... Address Output Address Output Address Output Address Output Address Output Address Output Address Output Address Output Address/Data Multiplexed Address/Data Multiplexed Address/Data Multiplexed Address/Data Multiplexed Address/Data Multiplexed Address/Data Multiplexed Address/Data Multiplexed Address/Data Multiplexed Address Strobe (Out) Read/Write Select shows a CMOS inverter, which MOTOROLA 2-21 ...

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... Although input-only pins can be connected directly difficult to change the level at that input pull-up or pulldown resistor is used in- stead, a signal can easily be connected to the input later. The preferred method of ter- MOTOROLA 2- ...

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... V M68HC11 REFERENCE MANUAL . Many other factors, including ambient temperature SS pin is the reference point from SS pin is the main positive power supply DD greater than or equal battery- DD greater than 5 V when batteries are new DD PINS AND CONNECTIONS equal MOTOROLA 2-23 ...

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... On the other hand, any buses and signals wholly contained within the control module probably do not require any sort of protective interface because there is little chance that these sig- nals would be exposed to illegal levels few cases, a protective interface can even MOTOROLA 2- ...

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... REFERENCE MANUAL INPUT BUFFER [ [2] 2-15) is driven with voltages below the pin voltage is driven more SS , current increases. These currents have a tendency the protection device will begin to conduct and DD PINS AND CONNECTIONS , the thick-field SS , which conducts when the SS MOTOROLA 2-25 ...

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... Although the N-channel devices [4] eliminates the need for ex- ternal pull-up or pulldown resistors on unused port E pins, a conservative designer would still terminate these pins to help prevent static damage. MOTOROLA 2-26 . There should be some external series impedance be- SS ...

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... D will still respond in a predictable manner. There may be valid system design reasons for choosing a high external series resistance (e.g., to minimize power consumption in M68HC11 REFERENCE MANUAL [5] N ANALOG MULTIPLEXER [ [4] [2] are not necessarily a good idea on the analog inputs. DD REF PINS AND CONNECTIONS INPUT BUFFER is 5.12 V, leaving only about MOTOROLA 2-27 ...

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... Software would be arranged so that no more than one of these I/O pins is con- figured as an output at any time to avoid output driver contention. In these applications, the I/O pins should be configured for the open-drain mode so the output drivers are prevented from high-current contention. MOTOROLA 2-28 Considerations. , which is in parallel with the inherent diode of the thick- ...

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... MOS circuitry for a digital output-only pin. OUTPUT BUFFER Figure 2-19 Internal Circuitry — Output-Only Pin M68HC11 REFERENCE MANUAL Figure 2-18). These pins are similar , the N-channel output device DD [ PIN PIN N N PINS AND CONNECTIONS . In terms of DD INPUT BUFFER Figure 2-19 shows the MOTOROLA 2-29 ...

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... The MODB higher level than V DD SET should be driven low. [1] MODB/V STBY PIN [7] Figure 2-20 Internal Circuitry — MODB/V MOTOROLA 2-30 Pin STBY Figure 2-20). A MOS switch automatically pin, this illegal voltage is passed in to the in- STBY relative to V STBY ...

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... Normal users would not encounter this potential problem since the V only intended for use by Motorola. The current-limiting resistor has no adverse affect on the bulk programming process since the current requirements for EEPROM pro- gramming are very small ...

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... SYSTEM POWER 4.7 F 10M 8.0 MHz RESET MC34064 GND CONNECT JUMPER FOR BOOTSTRAP MODE V DD Figure 2-22 Basic Single-Chip-Mode Connections MOTOROLA 2-32 MC68HC11A8 PA3/OC5/OC1 V DD PA4/OC4/OC1 0.1 F PA5/OC3/OC1 PA6/OC2/OC1 PA7/PAI/OC1 V SS EXTAL XTAL 4.7K RESET V DD 4.7K XIRQ PD0/RxD 4.7K PD1/TxD IRQ PD2/MISO 4.7K PD3/MOSI ...

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... ROMON control bit in the CONFIG register. The potential for conflict with the EE- PROM poses no concern in normal expanded mode because the external MCU data bus is high impedance and ignored during reads of the internal EEPROM. In special M68HC11 REFERENCE MANUAL Figure 2-23 is for a fairly straightforward expanded-mode 3.5.3 Special Test PINS AND CONNECTIONS . DD Mode). MOTOROLA 2-33 ...

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... In this example system, the special test mode would only be in effect for a short time after reset, and reads of the internal EEPROM could easily be avoided during this time. MOTOROLA 2-34 2.7.2 Internal Read Visibility PINS AND CONNECTIONS (IRV) ...

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... PE0/AN0 PE1/AN1 PE2/AN2 PE3/AN3 V PE4/AN4 RH PE5/AN5 V PE6/AN6 RL PE7/AN7 PINS AND CONNECTIONS DATA BUS R/W 74HC373 A10 A11 A12 A13 A14 A15 CONTROL BUS MOTOROLA 2-35 ...

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... DATA BUS A10 A11 A12 A15 A13 E R/W R/W A13 A14 E A15 ADDRESS BUS CONTROL BUS Figure 2-24 Basic Expanded Mode Connections (Sheet MOTOROLA 2- A10 ...

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... IRV can be written to one at any time unless it has previously been written to zero. If the IRV bit is written to zero, the function becomes disabled until the next reset sequence. M68HC11 REFERENCE MANUAL PINS AND CONNECTIONS MOTOROLA 2-37 ...

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... The MC68HC24 copies this logic so that the registers in the MC68HC24 will au- tomatically track the internal remapping logic. Software written on an expanded system, including an MC68HC24, will operate exactly as it would in the internal ROM of an MC68HC11A8 in single-chip mode. MOTOROLA 2-38 PINS AND CONNECTIONS M68HC11 ...

Page 61

... The special test mode, which is intended primarily for factory testing, is seldom used by the user except for emulation, development other rare circumstances. M68HC11 CONFIGURATION AND MODES OF OPERATION REFERENCE MANUAL SECTION 3 MOTOROLA 3-1 ...

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... Can be written only while SMOD equals one 1 = Bootstrap ROM enabled at $BF40–$BFFF 0 = Bootstrap ROM disabled and not present in memory map The RBOOT control bit enables or disables the special bootstrap control ROM. This MOTOROLA CONFIGURATION AND MODES OF OPERATION 3-2 Table 3-1 summarizes the operation of the ...

Page 63

... PROM byte. During any reset, the contents of the EEPROM byte are transferred to the working static register over the data bus. Due to this mechanism, changes to the EE- PROM CONFIG location are not visible and do not alter the operation of the MCU until M68HC11 CONFIGURATION AND MODES OF OPERATION REFERENCE MANUAL MOTOROLA 3-3 ...

Page 64

... MCU. The contents are retained when the MCU is completely removed from a system (e.g., when shipped from the Motorola factory). In this way, the control bits in the CONFIG register are like mask-programmed options. Unlike mask options, the contents of this register can be altered after the MCU is manufactured to meet the customer’ ...

Page 65

... ROM. Similarly, the MC68HC11A0 version of the part comes with $0C in CONFIG to disable both the 8-Kbyte ROM and 512-byte EE- PROM. The CONFIG byte is not part of the 512-byte EEPROM. If the CONFIG register M68HC11 CONFIGURATION AND MODES OF OPERATION REFERENCE MANUAL SECTION MOTOROLA 3-5 ...

Page 66

... The erased state of the CONFIG register in the MC68HC811A2 version is $FF, which means the 2-Kbyte EEPROM is enabled in the area from $F800–$FFFF when the part comes from the Motorola factory. To use the part, the user must have a meaningful reset vector at $FFFE,FFFF or must connect the mode pins so the system will come out of reset in one of the special modes ...

Page 67

... The second reason for remapping RAM or registers would be to make the MCU compatible with the memory map of an existing system. For example, the MC6801 MCU is not compatible with the Motorola EXORciser . The MDOS operating system software requires RAM to exist from $0000–$7FFF, ROM routines to exist from $E800– ...

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... E clock divided by 16. In normal modes, this prescale rate can only be changed once within the first 64 bus cycles after reset, and the resulting count rate stays in effect until the next reset. MOTOROLA CONFIGURATION AND MODES OF OPERATION 3-8 5 ...

Page 69

... CONFIGURATION AND MODES OF OPERATION REFERENCE MANUAL PR0 Prescale Factor IRQE DLY CME before it enters the COP watchdog sys- 3-2. The columns at the right of the table show the resulting $1039 2 1 BIT 0 0 CR1 CR0 MOTOROLA 3-9 ...

Page 70

... E-clock frequency (no throughput penalty for external devices). The maximum bus frequency for the MC68HC11A8 is 2.1 MHz, which is comparable to the fastest external EPROMs available at the time the M68HC11 was introduced. MOTOROLA CONFIGURATION AND MODES OF OPERATION 3-10 SECTION 5 RESETS AND IN- ...

Page 71

... While in either special mode, these protections are over- ridden, and these control bits may be written as if they were ordinary control bits. For a detailed description of these protection mechanisms, see M68HC11 CONFIGURATION AND MODES OF OPERATION REFERENCE MANUAL 3.3 Protected Control MOTOROLA 3-11 ...

Page 72

... The following register and paragraphs discuss the TEST1 control register. Testing functions are not recommended for use by the user since they may change at any time to meet the manufacturing requirements of Motorola; however, brief descriptions of these testing functions will be presented. Occasionally, knowledge of these functions will help a user understand what is happening if one of these functions is accidentally invoked during development of an application ...

Page 73

... Overrides the specifications in the CONFIG register so that COP is enabled and ROM and EEPROM are in the memory map. If the OCCR bit is set to one, ROM is removed from the memory map, regardless of other control bits Configuration options are controlled by the CONFIG register. M68HC11 CONFIGURATION AND MODES OF OPERATION REFERENCE MANUAL NOTE MOTOROLA 3-13 ...

Page 74

... SECTION 9 ASYNCHRONOUS SERIAL COMMUNICATIONS 3.5.3 Special Test Mode The special test mode is primarily intended for Motorola internal production testing; however, there are a few cases where the user can utilize the test mode. These spe- cial cases include programming the CONFIG register, programming calibration data into the EEPROM, and development situations such as emulation and debug ...

Page 75

... SMOD control bit back to zero so interrupt and reset vectors return to $FFC0–$FFFF. M68HC11 CONFIGURATION AND MODES OF OPERATION REFERENCE MANUAL 3.6 Test and Bootstrap Mode Applications), which just MOTOROLA 3-15 ...

Page 76

... Because the SCI receiver and transmitter have been enabled, the user must disable them if the PD0 or PD1 pins are to be used as general-purpose I/O pins. The port D wired-OR mode (DWOM) control bit in the SPCR has been written to one MOTOROLA CONFIGURATION AND MODES OF OPERATION 3-16 ...

Page 77

... When an SWI request is encountered, the registers are stacked, and the vector in the bootstrap ROM passes control to $00F4, which, in turn, contains a jump instruction to the user’s SWI service routine. M68HC11 CONFIGURATION AND MODES OF OPERATION REFERENCE MANUAL 3-3). These RAM locations are called pseudo-vectors be- MOTOROLA 3-17 ...

Page 78

... Another bootloader firmware option allows a direct jump to the start of RAM, but this feature is probably not very useful to the user since it assumes there is already a meaningful program in the internal RAM at the time of reset. This option is invoked by sending a $55 character to the SCI instead of the $FF or break characters previously MOTOROLA CONFIGURATION AND MODES OF OPERATION 3-18 Address SCI $00E5– ...

Page 79

... MCU whether the MCU is reset in special test mode or normal expanded mode with the internal ROM disabled. Several subtle benefits to this feature are evident. First, it means no decode changes are needed to alternate between nor- M68HC11 CONFIGURATION AND MODES OF OPERATION REFERENCE MANUAL Figure 3 relatively simple expanded-mode is too low to DD MOTOROLA 3-19 ...

Page 80

... AS/STRA pin acts as an address strobe that clocks at the E-clock fre- quency even while RESET is still low (part does not have to be out of reset to check for security). If security is not activated, the AS/STRA pin acts as the strobe A high- impedance input. MOTOROLA CONFIGURATION AND MODES OF OPERATION 3-20 Figure 3-3 ...

Page 81

... PE0/AN0 PE1/AN1 PE2/AN2 PE3/AN3 V PE4/AN4 PE5/AN5 V PE6/AN6 RL PE7/AN7 Figure 3-3 (Sheet 10K TYP AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AS R A10 A11 A12 A13 A15 10K TYP PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 MOTOROLA 3-21 ...

Page 82

... HC00 A8 A9 A10 A11 A12 A13 A13 A15 HC00 A15 V DD 10K TYP PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 Figure 3-2 Schematic for MOTOROLA CONFIGURATION AND MODES OF OPERATION 3-22 10K TYP DATA BUS ...

Page 83

... Branch to self (hangs till pwr off or rst) subroutines follow Save X (not required in this ex I just do) #$0D06 3334 6~ * 500nS/~ = l0mS [3] in []s is cycles for that instruc DLOOP [3] cont. for 3334 times (loop time = 6~) Recover X value **RETURN** $BFFE $A000 Point to start of program * * * MOTOROLA 3-23 ...

Page 84

... MOTOROLA CONFIGURATION AND MODES OF OPERATION 3-24 M68HC11 REFERENCE MANUAL ...

Page 85

... MCUs. The user places an order for produc- tion units with the pattern of instructions and data to be programmed into the on-chip ROM. Motorola then translates this pattern into a photographic mask to be used during processing of silicon wafers. Motorola then produces a small batch of these parts and returns them to the customer for verification ...

Page 86

... Depending upon the application, maximum efficiency can be achieved by hav- ing RAM, I/O registers, or both in this premium address space. MOTOROLA 4-2 3.2 EEPROM-Based CONFIG Regis- ON-CHIP MEMORY ...

Page 87

... In some CMOS systems, even the sequencing of power supplies is critical, which DD M68HC11 REFERENCE MANUAL 3.3.1 RAM and I/O Mapping Register pin for standby power in a mostly hard- STBY method of RAM standby allows V STBY ON-CHIP MEMORY (INIT). that cannot be easily DD must be turned off to re MOTOROLA 4-3 ...

Page 88

... Although some Family members (e.g., MC68HC811E2) allow remapping of the on- chip EEPROM, the 512-byte EEPROM in the MC68HC11A8 is fixed at locations $B600–$B7FF. This 512-byte block is logically arranged into 32 rows of 16 bytes each. The first row occupies the locations $B600–$B60F, the second row occupies $B610– MOTOROLA 4-4 relative to MODB/V DD ...

Page 89

... BIT 7 BIT B600 B610 ON-CHIP MEMORY B61E B61F B63F B65F B67F B69F B6BF B6DF ARRAY B6FF RIGHT HALF B71F B73F B75F B77F B79F B7BF B7DF B7FE B7FF CONFIG ROW FOR RIGHT HALF BIT 0 BIT B611 Figure 4-3, a MOTOROLA 4-5 ...

Page 90

... BYTE ROW (0) ROW (N) COL (0) COL (N) V ERASE I/O (7) I/O (0) Figure 4-3 Condensed Schematic of EEPROM Array MOTOROLA 4-6 show an EEPROM byte being erased, programmed, is nominally 5 V and developed from V with an on-chip charge pump ON-CHIP MEMORY Figure is about ...

Page 91

... EEPROM byte being programmed to the value $55 (0101 0101) M68HC11 REFERENCE MANUAL BIT LINE BIT-SELECT ROW DEVICE SELECT FLOATING GATE D G CONTROL FLOATING-GATE GATE DEVICE S ARRAY GROUND NOT DRIVEN 4-5), the array ground is connected to V ON-CHIP MEMORY ARRAY GROUND . The row and SS PP MOTOROLA 4-7 ...

Page 92

... PROM operations are actually much more complicated than this discussion suggests, but the following general statements may be useful to designers using the EEPROM. 1) Since no high voltages are present during read operations, no degradation of data MOTOROLA 4-8 for bits not being programmed (ones) and to DD ...

Page 93

... The clock source driving the charge pump is software selectable. When the clock se- M68HC11 REFERENCE MANUAL PRECHARGE THEN SENSE from V uses MOS capacitors, which PP DD and the frequency of the driving clock. The load de- DD ON-CHIP MEMORY 1 0 ARRAY GROUND MOTOROLA 4-9 ...

Page 94

... The user may write these bits back to one at any time to inhibit further EE- PROM changes. Once this protection is re-enabled, it remains in effect until another reset. There is no BPROT register in the MC68HC11A8. MOTOROLA 4-10 equal to 3 Vdc and CSEL equals one to enable the ...

Page 95

... M68HC11 REFERENCE MANUAL BYTE ROW ERASE pin. The intended purpose of this PPBULK ROW Type of Erase 0 Bulk Erase (All 512 Bytes) 1 Row Erase (16-Byte Row) 0 Byte Erase 1 Byte Erase ON-CHIP MEMORY $103B 1 BIT 0 EELAT EEPGM 0 0 MOTOROLA 4-11 ...

Page 96

... STAB JSR CLR " " 4.3.5.2 Bulk Erase The following program segment demonstrates how to bulk erase the 512-byte EEPROM. The CONFIG register is not affected in this example. MOTOROLA 4-12 power supply to the EEPROM logic for programming PP is off; when EEPGM is one #$02 $103B Set EELAT bit (EEPGM=0) ...

Page 97

... Delay 10 mS $103B Turn off high voltage & set to read mode #$16 $103B Set to BYTE erase mode 0,X Write any data to address to be erased #$17 $103B Turn on high voltage DLY10 Delay 10 mS $103B Turn off high voltage & set to read mode ON-CHIP MEMORY MOTOROLA 4-13 ...

Page 98

... ROM. Since this option is enabled or disabled during physical manufacturing of the silicon die, the choice must be made prior to manufacturing. Although this first level of enable makes the MCU capable of being secured, it does not activate the security mode. The second requirement to en- MOTOROLA 4-14 Information. #$06 ...

Page 99

... Another approach would be to program a vital subroutine entirely within the EEPROM. This approach is better than the previous key-checking approach because the ROM M68HC11 REFERENCE MANUAL ON-CHIP MEMORY MOTOROLA 4-15 ...

Page 100

... This procedure is only possible when the new value has no ones where the EEPROM lo- cation already has a zero. A method called ‘write-more-zeros’ can be used to program additional bits in an EEPROM location without erasing the location first, which elimi- MOTOROLA 4-16 ON-CHIP MEMORY M68HC11 ...

Page 101

... PROM operations to be completed prior to system shutdown. Other systems may have battery backup of RAM so programming status could be maintained in this mem- ory. Upon reset, this status (in RAM) could be checked, and any operation that was in M68HC11 REFERENCE MANUAL Expectancy. ON-CHIP MEMORY 4.4.7 Soft- MOTOROLA 4-17 ...

Page 102

... The home thermostat example can also benefit from a calibration table in EEPROM. There are many types of temperature sensors with various degrees of accuracy and linearity; however, the most accurate and most linear devices also tend to be the most expensive. Since the application dictates a minimum degree of accura- MOTOROLA 4-18 ON-CHIP MEMORY M68HC11 ...

Page 103

... When such a device is returned to the factory for repair, the historical data can be read out of the EEPROM. Even if batteries and other power sources failed, this information could be valid. In this context, logging means to make a semi-permanent record of data not requiring power or other normal operating conditions to remain valid. In many cases, there is M68HC11 REFERENCE MANUAL ON-CHIP MEMORY MOTOROLA 4-19 ...

Page 104

... In this manner, the tasks requiring the most frequent ser- vice would become the set of tasks that are serviced on every main loop pass. Al- though both the fixed priority and the dynamically adaptive priority schemes would accomplish the same amount of work, the adaptive scheme is more responsive. Be- MOTOROLA 4-20 ON-CHIP MEMORY M68HC11 ...

Page 105

... Temperature has a dramatic effect on write-erase endurance. An EEPROM having a life expectancy of 5,000 write-erase cycles at 125 C typically has a life expectancy of 100,000 write-erase cycles Motorola publishes a quarterly reliability report which includes the latest life-expectancy data for this rapidly changing technology. The quality of the thin oxides (processing) is maintained at a very high level, but there is still some lot-to-lot variation affecting write-erase endur- ance ...

Page 106

... The erase-before-write method is used in production testing and for ongoing reliability monitoring. Every part that Motorola ships is exposed to a significant number of write- erase cycles at high temperature to eliminate parts having infant mortality problems and to identify any lots having processing problems. In addition, sample batches of parts are endurance tested to monitor processing quality ...

Page 107

... Only considerable characterization data can prove or disprove these theories, but preliminary data supports the suggestion that the extra programming time on some bits has no detrimental effects. M68HC11 REFERENCE MANUAL NOTE 4.3.2 Basic Operation of the ON-CHIP MEMORY EEPROM. Figure 4-8 MOTOROLA 4-23 ...

Page 108

... Figure 4-8 Erase-Before-Write Programming Method Figure 4-9 Program-More-Zeros Programming Method Figure 4-10 shows the selective-write method being used to change an EEPROM lo- MOTOROLA 4-24 NOT DRIVEN ERASE FIRST ...

Page 109

... The failure also shows Figure ON-CHIP MEMORY to the array DD to the how ARRAY GROUND (NOT DRIVEN) Figure 4-11 shows the volt low enough level to pre- without producing any notice- 4-10), the path from V DD MOTOROLA 4-25 ...

Page 110

... To extend the write-erase lifetime of a variable even further, using multiple EEPROM locations would allow switching to a different location when the current location ap- proached wear-out. The problem is to decide when a location is approaching wear-out. MOTOROLA 4- ...

Page 111

... The life expectancy is approximately 100,000 write-erase cycles even though it is only 5,000 at 125 C. M68HC11 REFERENCE MANUAL ON-CHIP MEMORY MOTOROLA 4-27 ...

Page 112

... MOTOROLA 4-28 ON-CHIP MEMORY M68HC11 REFERENCE MANUAL ...

Page 113

... MCU cannot advance past the first step of this sequence. Even with no clock present, a RESET signal will cause some changes. Most important, an unclocked RE- M68HC11 REFERENCE MANUAL SECTION 5 RESETS AND INTERRUPTS 5.7 Interrupts from In- MOTOROLA 5-1 ...

Page 114

... Port B and bits [6:3] of port A have their directions fixed as outputs, and their reset state is logic zero. 5.1.1.4 Timer During reset, the timer system is initialized to a count of $0000. The prescaler bits are cleared, and all output-compare registers are initialized to $FFFF. All input-capture MOTOROLA 5-2 RESETS AND INTERRUPTS M68HC11 REFERENCE MANUAL ...

Page 115

... The SPI system is disabled by reset. The port pins associated with this function default to being general-purpose I/O lines. 5.1.1.10 Analog-to-Digital (A/D) Converter The A/D converter system configuration is indeterminate after reset. The conversion complete flag is cleared by reset. The A/D power-up (ADPU) bit is cleared by reset, disabling the A/D system. M68HC11 REFERENCE MANUAL RESETS AND INTERRUPTS MOTOROLA 5-3 ...

Page 116

... COP watchdog timer, and engages/disengages the security option. The CONFIG register and mechanism are described in greater detail in tion of CONFIG Mechanism. The features enabled by the CONFIG register can be thought of as mask-programmed options that do not require software service. MOTOROLA 5-4 RESETS AND INTERRUPTS 3.2.1 Opera- M68HC11 ...

Page 117

... Depending on the cause of reset and the mode of operation, the reset vector may be fetched from any of six possible locations. In older Motorola MCUs, there was only one reset vector at $FFFE,FFFF. 5.2 Causes Of Reset In the MC68HC11A8, there are on-chip systems that can detect MCU system failures and generate a low level out the RESET pin to reinitialize other peripherals in the sys- tem ...

Page 118

... MCU clock frequency. If the MCU clock stops or is running too slow, a system reset is generated. Finally, a user can initiate an external reset by momentarily driving the RE- SET pin low. The COP and clock monitor features can be disabled. The power-on re- MOTOROLA 5-6 Normal Mode Vector $FFFE,FFFF ...

Page 119

... Unlike a programmed mask option, the COP enable may be changed by the end user. The requirements for M68HC11 REFERENCE MANUAL has discharged therefore, the internal DD rise time, the internal POR times out well before DD RESETS AND INTERRUPTS is applied to the DD DD MOTOROLA 5-7 ...

Page 120

... Placing the COP service instructions in an interrupt service routine is bad practice. In such a case, the interrupt could occur often enough to keep the COP system satisfied even if the main-line program was no longer functioning. The implementation of the COP timer causes a tolerance on the time-out period. The MOTOROLA 5-8 Table 5-3). The columns at the right of the ...

Page 121

... It is possible to use the clock monitor in systems that also use the STOP instruction. In such a system, the CME control bit would be written to zero to disable the clock M68HC11 REFERENCE MANUAL 15 clock will reach the COP timer stages. This 15 clock. This tolerance varies with E-clock frequen- contain additional information RESETS AND INTERRUPTS MOTOROLA 5-9 ...

Page 122

... M68HC11 systems. The external POR delay and manual re- set switch are optional. For many applications, the voltage detector [1] and the pull-up resistor [4] are the only external components needed for reset. MOTOROLA 5-10 is below operating level. The LVI device ...

Page 123

... The remaining interrupt sources are maskable by the interrupt mask bit (I) in the M68HC11 REFERENCE MANUAL RESET [1] MC34064 GND RESET [2] MC34164 GND 3 RESETS AND INTERRUPTS V DD [4] 4 RESET OF M68HC11 MOTOROLA 5-11 ...

Page 124

... CCR. After the CCR value is stacked, the I bit in the CCR (and the X bit if XIRQ is pending) is set to inhibit further interrupts. The interrupt sequence then proceeds to the priority resolution step. 5.3.2 Selecting Interrupt Vectors After the CCR has been stacked, the CPU evaluates all pending interrupt requests to MOTOROLA 5-12 RESETS AND INTERRUPTS M68HC11 REFERENCE MANUAL ...

Page 125

... RBOOT bit may be written to one while in special test mode. SMOD — Special Mode May be written to zero but not back to one M68HC11 REFERENCE MANUAL MDA IRV PSEL3 PSEL2 (Refer to Table 5-1) RESETS AND INTERRUPTS $103C 2 1 BIT 0 PSEL1 PSEL0 MOTOROLA 5-13 ...

Page 126

... Figure 5-2, Figure 5-4, and MOTOROLA 5-14 PSEL1 PSEL0 Interrupt Source Promoted 0 0 Timer Overflow 0 1 Pulse Accumulator Overflow 1 0 Pulse, Accumulator Input Edge 1 1 SPI Transfer Complete 0 0 SCI Serial System 0 1 Reserved (Default to IRQ) ...

Page 127

... Figure 5-2, shows how interrupt priority is resolved. of the SCI interrupt block in the SCI subsystem. M68HC11 REFERENCE MANUAL shows how the CPU begins from a reset and how in- Figure Figure 5-4, shows the resolution of interrupt sources within RESETS AND INTERRUPTS 5-4, an expansion of a Figure 5-6, an expansion MOTOROLA 5-15 ...

Page 128

... DELAY 4064 E CYCLES EXTERNAL RESET LOAD PROGRAM COUNTER WITH CONTENTS OF $FFFE, $FFFF (VECTOR FETCH) 1A Figure 5-2 Processing Flow out of Resets (Sheet MOTOROLA 5-16 CLOCK MONITOR FAIL (WITH CME = 1) LOAD PROGRAM COUNTER WITH CONTENTS OF $FFFC, $FFFD (VECTOR FETCH) SET BITS S, I, AND X ...

Page 129

... OPCODE? N WAI Y STACK CPU INSTRUCTION? REGISTERS N SWI Y N INSTRUCTION? INTERRUPT PENDING? N RTI SET BIT I IN CCR Y INSTRUCTION? RESOLVE INTERRUPT N PRIORITY AND FETCH VECTOR FOR HIGHEST EXECUTE THIS PENDING SOURCE INSTRUCTION SEE FIGURE 5–3 1A RESETS AND INTERRUPTS STACK CPU REGISTERS ANY Y MOTOROLA 5-17 ...

Page 130

... NO YES IC1I = YES IC2I = YES IC3I = YES OC1I = Figure 5-4 Interrupt Priority Resolution (Sheet MOTOROLA 5-18 YES XIRQ PIN SET X BIT IN CCR LOW ? FETCH VECTOR $FFF4, FFF5 NO FETCH VECTOR FETCH VECTOR $FFF2, FFF3 YES REAL-TIME FETCH VECTOR INTERRUPT ...

Page 131

... FETCH VECTOR TOF = 1? $FFDE, $FFDF N Y FLAG FETCH VECTOR PAOVF = 1 $FFDC, $FFDD N Y FLAG FETCH VECTOR PAIF = 1? $FFDA, $FFDB N FLAGS Y FETCH VECTOR SPIF = 1? OR $FFD8, $FFD9 MODF = 1? N FETCH VECTOR $FFD6, $FFD7 FETCH VECTOR $FFF2, $FFF3 RESETS AND INTERRUPTS 2B END MOTOROLA 5-19 ...

Page 132

... The last value to be pulled from the stack is the pro- gram counter, which causes processing to resume where it was interrupted. 5.4 Non-Maskable Interrupts This subsection discusses the illegal opcode fetch interrupt, the SWI instruction, and MOTOROLA 5-20 Y RIE = ...

Page 133

... D-type flip-flop. The set input is connected to the OR of reset and XIRQ acknowledge. The reset input is connected to the AND of a CCR write and data bit 6 equals zero attempt is made to TAP or unstack a one to the X bit, neither M68HC11 REFERENCE MANUAL RESETS AND INTERRUPTS MOTOROLA 5-21 ...

Page 134

... The return address would need to be manually changed since it points to the illegal opcode rather than to the instruction that follows the illegal opcode. The TEST Instruction (opcode $00 legal opcode in special test and bootstrap modes, but especially offensive illegal opcode in normal operating modes. The MOTOROLA 5-22 RESETS AND INTERRUPTS M68HC11 ...

Page 135

... I bit is set, interrupts can become pending but will not be honored. When the I bit is clear, interrupts are enabled to interrupt normal program flow when an interrupt source requests service. The I bit is set during reset to prevent interrupts from being honored until minimum sys- M68HC11 REFERENCE MANUAL NOTE RESETS AND INTERRUPTS MOTOROLA 5-23 ...

Page 136

... I bit is later cleared. When the I bit is cleared by a CLI or TAP instruction, the actual clear operation is delayed for one bus cycle so the instruction following the CLI or TAP will always be executed. This procedure implies that the following loop can never be interrupted by a maskable interrupt: MOTOROLA 5-24 RESETS AND INTERRUPTS M68HC11 ...

Page 137

... IRQ pin configuration (IRQE = 0 for low level sensitive and IRQE = 1 for low- going edge sensitive). The IRQE control bit is time-protected, which means it can only M68HC11 REFERENCE MANUAL CLI Enable Interrupts SEI Disable Interrupts BRA LOOP Repeat CLI Enable Interrupts WAI Wait for an Interrupt RESETS AND INTERRUPTS 2.2.6 In- MOTOROLA 5-25 ...

Page 138

... Interrupts from Internal Peripheral Subsystems The following paragraphs discuss common aspects of the interrupts generated by on- chip peripheral systems. The interrupt sources for on-chip peripheral systems are dis- cussed in greater detail in the sections for each peripheral system. MOTOROLA 5-26 RESETS AND INTERRUPTS M68HC11 ...

Page 139

... SCI transmitter. Though it is not obvious, this action can satisfy the second step of the automatic clearing mechanism for the RDRF flag because clearing of the SCI transmit data register involves a read of the SCI data M68HC11 REFERENCE MANUAL Flags. RESETS AND INTERRUPTS MOTOROLA 5-27 ...

Page 140

... MOTOROLA 5-28 RESETS AND INTERRUPTS M68HC11 REFERENCE MANUAL ...

Page 141

... Accumulators A and B are general-purpose 8-bit accumulators used to hold operands and results of arithmetic calculations or data manipulations. Some instructions treat the combination of these two 8-bit accumulators as a 16-bit double accumulator (ac- cumulator D). M68HC11 REFERENCE MANUAL SECTION 6 APPENDIX A INSTRUCTION SET CENTRAL PROCESSING UNIT DETAILS. These MOTOROLA 6-1 ...

Page 142

... In the earlier M6800 and M6801, the programmer had to store the index to some temporary location so the second index value could be loaded into the index register. MOTOROLA 6 ...

Page 143

... This method is a simple way to assure a register(s) will be the same after returning from the subroutine as it was before starting the subroutine. The most important aspect of the stack is that it is completely automatic. A program- M68HC11 REFERENCE MANUAL CENTRAL PROCESSING UNIT MOTOROLA 6-3 ...

Page 144

... CPU to adjust the result of an 8-bit BCD addition correct BCD for- mat, even though the add was a binary operation. This H bit, which is only updated by the ABA, ADD, and ADC instructions, is used by the DAA instruction to compensate the result in accumulator A to correct BCD format. MOTOROLA 6-4 6.3.1.2 Arithmetic Operations), is only affected by the add ...

Page 145

... N, Z, and V condition code flags. (In some other architectures, very few instructions affect the condition code bits; thus, it takes two instructions to load and test a variable.) The challenge in a Motorola proces- sor lies in finding instructions that specifically do not alter the condition codes in rare cases where that is desirable ...

Page 146

... Examples of several assembly-language statements using the immediate addressing mode are shown. Symbols and expression used in these statements are defined immediately after the examples. MOTOROLA 6-6 CENTRAL PROCESSING UNIT M68HC11 ...

Page 147

... LDAA #’A LDX #REGS Prefix Definition None Decimal $ Hexadecimal @ Octal % Binary ’ Single ASCII Character CENTRAL PROCESSING UNIT Comments CAT SAME AS 7 SET LOCATION COUNTER ADDR(REGS) IS $1000 DECIMAL 22 ACCA ($16) XOR ($34,ACCB) ACCB RIGHT ALIGNED BINARY 7 ACCA 7 ACCA:ACCB OCTAL ASCII ADDR(REGS) X MOTOROLA 6-7 ...

Page 148

... Machine Code Label CAT the previous example, the first reference to the CAT label is a forward reference, and the assembler selected the extended addressing mode. The second reference, MOTOROLA 6-8 Operation Operand Comments SUBD CAT FWD REF TO CAT EQU ...

Page 149

... CAT Bit-manipulation instructions support direct and indexed addressing modes but not ex- M68HC11 REFERENCE MANUAL Operation Operand Comments ADDD X EA=(X) ADDD ,X EA=(X) ADDD 0,X EA=(X) ADDD 4,X EA=(X)+4 EQU 7 DEFINE CAT=7 ADDD CAT,X EA=(X)+7 ADDD $22,X EA=(X)+$22 ADDD CAT*8/2+6,X EA=(X)+(CAT*8 2+6) CENTRAL PROCESSING UNIT MOTOROLA 6-9 ...

Page 150

... Indexed Y addressing mode BRCLR and BRSET in- structions are five-byte instructions; thus, an offset byte of $FB will cause the instruc- tion to execute repeatedly until the bit test becomes false. MOTOROLA 6-10 Operation Operand ...

Page 151

... M68HC11 REFERENCE MANUAL Operation Operand Comments BRA WHERE FORWARD BRANCH BHI THERE BACKWARD BRANCH BCC LBCC L-O-N-G BCC BEQ HANG BRANCH TO SELF BEQ * "*" MEANS "HERE" JMP $1000 BSR HANG APPENDIX A INSTRUCTION SET CENTRAL PROCESSING UNIT DETAILS. 6.3.2 Stack and Index MOTOROLA 6-11 ...

Page 152

... Compare instructions perform a subtract within the CPU to update the condi- tion code bits without altering either operand. Although test instructions are provided, they are seldom needed since almost all other operations automatically update the condition code bits. MOTOROLA 6-12 Mnemonic IMM ...

Page 153

... CENTRAL PROCESSING UNIT EXT INDX INDY INH INH MOTOROLA 6-13 ...

Page 154

... The arithmetic shift right (ASR) instruction maintains the original value of the MSB of the operand, which facilitates manipulation of two’s-complement (signed) numbers. MOTOROLA 6-14 Mnemon- IMM ...

Page 155

... ASR ASRA ASRB (LSL) (LSLA) (LSLB) (LSLD) LSR LSRA LSRB LSRD ROL ROLA ROLB ROR RORA RORB CENTRAL PROCESSING UNIT EXT INDX INDY INH MOTOROLA 6-15 ...

Page 156

... This fact explains why the value in the stack pointer is incremented during transfers to an index register. There is a corresponding decrement of a 16-bit value trans- ferred from an index register to the stack pointer. MOTOROLA 6-16 Mnemonic IMM ...

Page 157

... Program Control Instructions This group of instructions, which is used to control the flow of a program rather than to M68HC11 REFERENCE MANUAL Function Mnemonic Clear Carry Bit CLC CLI CLV Set Carry Bit SEC SEI SEV TAP TPA CENTRAL PROCESSING UNIT INH MOTOROLA 6-17 ...

Page 158

... For example program contained the following instruction BHI where TINBUK2 was out of the –128/+127 location range, the following instruction se- quence could be substituted: BLS JMP AROUND EQU MOTOROLA 6-18 Mnemonic REL DIR BCC X BCS X ...

Page 159

... NOP instructions into loops, longer delays can be produced. M68HC11 REFERENCE MANUAL Mnemonic DIR EXT INDX JMP X X Mnemonic REL DIR BSR X JSR X RTS Function Mnemonic RTI Software Interrupt SWI Wait for Interrupt WAI CENTRAL PROCESSING UNIT INDY INH X X EXT INDX INDY INH INH MOTOROLA 6-19 ...

Page 160

... The TEST instruction is used only during factory testing and is treated as an illegal op- code in normal operating modes of the MCU. This instruction causes unusual behavior on the address bus (counts backwards), which prevents its use in any normal system. MOTOROLA 6-20 Function Mnemonic ...

Page 161

... For the vast majority of applications, these differences are irrelevant. For the benefit of those rare cases where a problem could arise, the differences will be explained in the detailed descriptions of these ports and pins in 7.3 Detailed I/O Pin M68HC11 REFERENCE MANUAL SECTION 7 Descriptions. PARALLEL INPUT/OUTPUT 7.3 Detailed MOTOROLA 7-1 ...

Page 162

... The remaining four port D pins are alternately used by the synchronous serial periph- eral interface (SPI) subsystem. The primary direction of data flow at each of the port D pins is selected by a corresponding bit in the data direction register for port D (DDRD). Port D can be configured for wired-OR operation by setting the port D wired- MOTOROLA 7-2 PARALLEL INPUT/OUTPUT 7.4 ...

Page 163

... Bit 5 — — PAMOD PEDGE 0 DWOM MSTR CPOL CPHA PARALLEL INPUT/OUTPUT 2 1 Bit 0 — — Bit 0 PORTA EGA INVB PIOC — — Bit 0 PORTC — — Bit 0 PORTB — — Bit 0 DDRD 0 RTR1 RTR0 PACTL SPR1 SPR0 SPCR MOTOROLA 7-3 ...

Page 164

... Writes to port bits that are fixed-direction input pins have no mean- ing or effect. PORTCL, a special port register associated with port C, is part of the handshake I/O subsystem. Reads of this address return data from an 8-bit port C latch. The inputs to MOTOROLA 7 ...

Page 165

... C. In these cases, the value at the pin itself does not necessarily reflect the value last written to the port; therefore important to read the level inside the output buffer rather than the level at the pin. M68HC11 REFERENCE MANUAL PARALLEL INPUT/OUTPUT MOTOROLA 7-5 ...

Page 166

... MC68HC11A8. Numbers in square brackets are references for the text descriptions. THICK-FIELD PROTECTION DEVICE TRANSMISSION GATE HFF HALF FLIP-FLOP Figure 7-3 Special Symbols used in Pin Logic Diagrams MOTOROLA 7-6 Figure 7-3 shows some of the symbols used to V range. Although transmission gates are ac PARALLEL INPUT/OUTPUT [3] — REFERENCE NUMBER DDRA7 — ...

Page 167

... During a port A read, transmission gate [1] is enabled to couple logic state [2] to the internal data bus. M68HC11 REFERENCE MANUAL [1] S TIMER INPUT-CAPTURE EDGE DETECT PARALLEL INPUT/OUTPUT 7.3.1.4 [2] PA2–PA0 PIN (IC1–IC3) IC1–IC3 TRIGGER MOTOROLA 7-7 ...

Page 168

... DDR control bit has no effect on the source of the data for the read. During a port A read, transmission gate [2] is enabled so the buffered state of the PA7 pin is driven onto the internal data bus. MOTOROLA 7-8 Logic. Reads of port A bit 7 always return PARALLEL INPUT/OUTPUT ...

Page 169

... CLEAR 1 0 SET 1 1 OM5 OL5 OM4 OL4 OM3 OL3 [14] OM2 OL2 Figure 7-5 PA[6:3] (OC[5:2]) Pin Logic M68HC11 REFERENCE MANUAL [2] [3] [4] [11] [10] PREVIOUS [12] TIMER OUT STATE R [13] S PARALLEL INPUT/OUTPUT PA6–PA3 PIN (OC2–OC5) N [5] [6] Q NEXT TIMER OUT STATE Q MOTOROLA 7-9 ...

Page 170

... When the OC1M7 control bit is one, control gate [8] is disabled and control gate [9] is enabled. While control gate [9] is enabled, a successful OC1 compare (OC1CMP force OC1 (FOC1) will enable transmission gate [6]. Transmission gate [6] causes the OC1D7 state to be transferred to cheater latch [4]. MOTOROLA 7- ...

Page 171

... B is used for general-purpose output or for simple strobe output. The following paragraphs describe the port B pin logic and the idealized timing for selected port B signals. M68HC11 REFERENCE MANUAL READ FROM PORT A VALID DATA REQUIRED AT CPU WRITE TO PORT A PARALLEL INPUT/OUTPUT NEW PORT A DATA MOTOROLA 7-11 ...

Page 172

... In expanded modes, the MDA control bit is one, enabling AND gate [4] and disabling AND gate [3], which couples high-order addresses to HFF [5]. In expanded modes, HFF [5] is transparent while address strobe (AS) is high and latched while AS is low. The output of HFF [5] is buffered and driven out the port B pins. MOTOROLA 7-12 [6] [5] ...

Page 173

... Special Considerations For Port B On MC68HC24 PRU The external PRU does not have access to the internal PH2 clock of the M68HC11 REFERENCE MANUAL READ FROM PORT B VALID DATA REQUIRED AT CPU WRITE TO PORT B HIGH ORDER ADDRESS PARALLEL INPUT/OUTPUT NEW PORT B DATA NEW PORT B DATA Connections. Port B logic MOTOROLA 7-13 ...

Page 174

... Q of cross-coupled latch [6] is coupled to the STRB pin, and STRB signals are active low. When the INVB control bit is one, the Q of cross-coupled latch [6] is coupled to the STRB pin and STRB signals are active high. MOTOROLA 7-14 Figure 7-9 for differences in timing for writes to port B of the 2 ...

Page 175

... B is config- ured for pulsed-mode operation. The second condition causing ENDSTRB to be asserted corresponds to the full-handshake modes where strobe B has been config- M68HC11 REFERENCE MANUAL HFF [1] [2] [4] [5] PARALLEL INPUT/OUTPUT R/W PIN (STRB) N MOTOROLA 7-15 ...

Page 176

... C or read into port C. Refer to discussion. Pin output buffer [1] can be enabled or disabled by the PTCTSC signal. This signal is driven to zero when address or data information needs to be driven out of port C. When PTCTSC is one, the output buffer is disabled so port C pins become high-im- MOTOROLA 7-16 Connections. PARALLEL INPUT/OUTPUT Figure 7-11 ...

Page 177

... C pins will not cause the relatively high currents normally expected for CMOS inputs. 7.3.4.2 Summary of Port C Idealized Expanded-Mode Timing Port C expanded-mode timing includes four types of bus cycles. Write cycles look M68HC11 REFERENCE MANUAL [ HFF PARALLEL INPUT/OUTPUT PIN PC7–PC0 N MOTOROLA 7-17 ...

Page 178

... When a port C bit is logic one, it becomes high impedance since neither the N- nor P-channel devices are active customary to have an external pull-up resistor on lines that are driven by open-drain devices. Port C can only be configured for wired- OR operation when the MCU single-chip mode of operation. MOTOROLA 7-18 2.6 Typical Expanded-Mode-System Connec- 7.3.4.1 Port C Pin Logic for ...

Page 179

... RDATEN ADDRESS (IRV=1) WDATEN PORT C OSCCLK PH1 PH2 ADDRESS, R/W DATA FROM CPU DATA TO CPU Figure 7-12 Summary of Idealized Port C Expanded-Mode Timing M68HC11 REFERENCE MANUAL ADDR ADDR ADDR ADDR VALID PARALLEL INPUT/OUTPUT DATA NEXT ADDR DATA NEXT ADDR DATA VALID MUST BE VALID MOTOROLA 7-19 ...

Page 180

... AND gate [5]. While AND gate [5] is enabled, a one from exclusive-OR gate [7] will force output buffer [ enabled, regardless of the state of the DDRC bit from HFF [1]. The EGA control bit specifies the level required at the STRA pin to force port C pins to be outputs. MOTOROLA 7-20 CWOM [4] ...

Page 181

... STRA will wake the MCU from the wait mode, valid data will not be latched into PORTCL because strobe input buffers [13] were disabled at the time of the asyn- chronous edge at STRA. 7.3.4.4 Port C Idealized Single-Chip Mode Timing Figure 7-14 shows the idealized timing for important port C control signals. Because M68HC11 REFERENCE MANUAL PARALLEL INPUT/OUTPUT MOTOROLA 7-21 ...

Page 182

... DDRC value to change in the same cycle it is being read. The timing for the RPORTCL signal is the same as that for the RDDRC signal. Unlike MOTOROLA 7-22 READ FROM PORT C VALID DATA REQUIRED AT CPU ...

Page 183

... While the MCU is operating in an expanded mode, the MDA control bit enables the output driver logic. As long as the MCU is not in stop mode, the AS signal is buffered and driven out the AS pin. M68HC11 REFERENCE MANUAL shows the differences between internal MC68HC11A8 PARALLEL INPUT/OUTPUT MOTOROLA 7-23 ...

Page 184

... C pins into the PORTCL register. In response to the asynchronous pulse from block [7], the block of logic [8] produces a pulse that is synchronized to the internal PH2 clock. Provided the asynchronous pulse meets a setup time before the rising edge of PH2, the output of block [8] will go MOTOROLA 7-24 [1] [2] ...

Page 185

... D enable transmission gate [6], coupling the buffered pin state from in- verters [7] to the internal data bus. When the DDRD bit from HFF [1] is one, transmis- M68HC11 REFERENCE MANUAL Subsystem. depicts the MC68HC11A8, there is a similar block of PARALLEL INPUT/OUTPUT Fig- MOTOROLA 7-25 ...

Page 186

... D pins. When the output of AND gate [3] is zero, the output driver is completely disabled; thus, this pin is configured as a high-impedance input. AND gate [3] will output a zero to dis- able the output driver whenever the corresponding DDRD bit is zero from HFF [1]. MOTOROLA 7-26 DWOM [9] ...

Page 187

... Also, when the DDRD bit is zero, transmission gate [5] is enabled. In this case, reads of port D enable transmis- sion gate [6], which couples the buffered pin state from inverters [7] to the internal data bus. M68HC11 REFERENCE MANUAL PARALLEL INPUT/OUTPUT MOTOROLA 7-27 ...

Page 188

... DDRD bit is zero from HFF [1] and the SCI transmitter is disabled by the XMITON signal. The state of the DDRD bit still influences the source of read data when the XMITON signal is forcing the pin to the output configuration. MOTOROLA 7-28 DWOM [10] ...

Page 189

... DDRD bit to one to enable slave data output from this pin when the SPI sys- tem is enabled for slave operation. The uses and implications of this logic are discussed in greater detail in INTERFACE. M68HC11 REFERENCE MANUAL for the following discussion. The data direction specifi- SECTION 8 SYNCHRONOUS SERIAL PERIPHERAL PARALLEL INPUT/OUTPUT MOTOROLA 7-29 ...

Page 190

... NAND gate [3] to control the direction of output buffer [9] based on the state of the DDRD bit from HFF [1]. Output driver [9] can be placed in a wired-OR configuration by the DWOM control bit. This control bit simultaneously affects all six port D pins. When DWOM is one, the P- MOTOROLA 7-30 DWOM [11] ...

Page 191

... HFF [1] controls direction. This last condition means that the user must set the corre- sponding DDRD bit to one to enable master data output from this pin when the SPI M68HC11 REFERENCE MANUAL for the following discussion. The data direction specifi- PARALLEL INPUT/OUTPUT MOTOROLA 7-31 ...

Page 192

... DDRD bit at HFF [1]. When the SPI system is enabled as a master, SPE is one and MSTRON is one. This configuration causes NAND gate [12] to output a one, which enables NAND gate [3] to control the direction of output buffer [9] based on the state MOTOROLA 7-32 SECTION 8 SYNCHRONOUS SERIAL PERIPHERAL ...

Page 193

... D pins associated with the SPI are immediately forced to their input configuration. The actual data direction for this port D pin is determined by the logic output of NAND gate [3]. When the SPI system is disabled, the DDRD bit from HFF [1] controls direc- M68HC11 REFERENCE MANUAL Figure 7-20 for the following discussion. The data direc- PARALLEL INPUT/OUTPUT MOTOROLA 7-33 ...

Page 194

... When the SPI system is disabled, SPE is zero, which makes the output of NAND gate [12] a one. This enables NAND gate [3] so that the DDRD bit from HFF [1] can enable or disable driver [9]. When the SPI system is enabled as a slave, SPE is MOTOROLA 7-34 SECTION 8 SYNCHRONOUS SERIAL PERIPHER- ...

Page 195

... Un- like the other three pins associated with the SPI system, the direction of this pin is not affected by mode faults. M68HC11 REFERENCE MANUAL for the following discussion. The data direction specifica- PARALLEL INPUT/OUTPUT MOTOROLA 7-35 ...

Page 196

... When the output of NAND gate [3] is one, driver [9] is disabled; thus, the pin is config- ured as a high-impedance input. To enable pin driver [9], both inputs to NAND gate [3] must be ones. When the SPI system is disabled, SPE is zero, making the output of NAND gate [10] a one. This configuration enables NAND gate [3] so that the DDRD MOTOROLA 7-36 DWOM [12] ...

Page 197

... This information is useful for understanding the basis for data-sheet timing specifications so timing information can be extrapolated for bus frequencies other than that used for the data sheet. Timing information con- cerning the SPI system is included in RIPHERAL INTERFACE. M68HC11 REFERENCE MANUAL SECTION 8 SYNCHRONOUS SERIAL PE- PARALLEL INPUT/OUTPUT MOTOROLA 7-37 ...

Page 198

... The timing for writes to DDRD is such that the pin configuration will change at the fall- ing edge of the internal PH2 clock. This edge corresponds to the middle of the E-clock high time. MOTOROLA 7-38 READ FROM PORT D VALID DATA REQUIRED AT CPU ...

Page 199

... N- and the P-channel devices can be partially turned on simultaneously, creating a low-impedance path between V this path is interrupted by extra N-channel device [4]. M68HC11 REFERENCE MANUAL SECTION 12 ANALOG-TO-DIGITAL CONVERTER to V REFL REFH PARALLEL INPUT/OUTPUT range, even REFH and V . For port E pins MOTOROLA 7-39 ...

Page 200

... Idealized Port E Timing Figure 7-24 shows the idealized timing for important port E control signals. This timing diagram, which does not consider any propagation delays, cannot be used as a sub- stitute for data-sheet timing specifications. This information is useful for understanding MOTOROLA 7- [ [5] ...

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